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Data Structures | Macros | Typedefs | Enumerations | Functions | Variables
riscv.c File Reference
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Data Structures

struct  csr_info
 
struct  trigger
 

Macros

#define CSR_BPCONTROL_BPACTION   (0xff<<11)
 
#define CSR_BPCONTROL_BPMATCH   (0xf<<7)
 
#define CSR_BPCONTROL_H   (1<<5)
 
#define CSR_BPCONTROL_M   (1<<6)
 
#define CSR_BPCONTROL_R   (1<<2)
 
#define CSR_BPCONTROL_S   (1<<4)
 
#define CSR_BPCONTROL_U   (1<<3)
 
#define CSR_BPCONTROL_W   (1<<1)
 
#define CSR_BPCONTROL_X   (1<<0)
 
#define DBUS   0x11
 
#define DBUS_ADDRESS_START   36
 
#define DBUS_ADDRESS_UNKNOWN   0xffff
 
#define DBUS_DATA_SIZE   34
 
#define DBUS_DATA_START   2
 
#define DBUS_OP_SIZE   2
 
#define DBUS_OP_START   0
 
#define DEBUG_RAM_START   0x400
 
#define DEBUG_ROM_EXCEPTION   (DEBUG_ROM_START + 8)
 
#define DEBUG_ROM_RESUME   (DEBUG_ROM_START + 4)
 
#define DEBUG_ROM_START   0x800
 
#define DECLARE_CSR(name, number)   { number, #name },
 
#define DMCONTROL   0x10
 
#define DMCONTROL_ACCESS   (7<<12)
 
#define DMCONTROL_AUTOINCREMENT   (1<<15)
 
#define DMCONTROL_BUSERROR   (7<<19)
 
#define DMCONTROL_FULLRESET   1
 
#define DMCONTROL_HALTNOT   (((uint64_t)1)<<32)
 
#define DMCONTROL_HARTID   (0x3ff<<2)
 
#define DMCONTROL_INTERRUPT   (((uint64_t)1)<<33)
 
#define DMCONTROL_NDRESET   (1<<1)
 
#define DMCONTROL_SERIAL   (3<<16)
 
#define DMINFO   0x11
 
#define DMINFO_ABUSSIZE   (0x7fU<<25)
 
#define DMINFO_ACCESS128   (1<<20)
 
#define DMINFO_ACCESS16   (1<<17)
 
#define DMINFO_ACCESS32   (1<<18)
 
#define DMINFO_ACCESS64   (1<<19)
 
#define DMINFO_ACCESS8   (1<<16)
 
#define DMINFO_AUTHBUSY   (1<<4)
 
#define DMINFO_AUTHENTICATED   (1<<5)
 
#define DMINFO_AUTHTYPE   (3<<2)
 
#define DMINFO_DRAMSIZE   (0x3f<<10)
 
#define DMINFO_SERIALCOUNT   (0xf<<21)
 
#define DMINFO_VERSION   3
 
#define DRAM_CACHE_SIZE   16
 
#define DTMCONTROL   0x10
 
#define DTMCONTROL_ADDRBITS   (0xf<<4)
 
#define DTMCONTROL_DBUS_RESET   (1<<16)
 
#define DTMCONTROL_IDLE   (7<<10)
 
#define DTMCONTROL_VERSION   (0xf)
 
#define get_field(reg, mask)   (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
 
#define MAX_HWBPS   16
 
#define set_field(reg, mask, val)   (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
 
#define SETHALTNOT   0x10c
 

Typedefs

typedef enum slot slot_t
 

Enumerations

enum  { RO_NORMAL , RO_REVERSED }
 
enum  dbus_op_t {
  DBUS_OP_NOP = 0 , DBUS_OP_READ = 1 , DBUS_OP_WRITE = 2 , DBUS_OP_NOP = 0 ,
  DBUS_OP_READ = 1 , DBUS_OP_WRITE = 2
}
 
enum  dbus_status_t {
  DBUS_STATUS_SUCCESS = 0 , DBUS_STATUS_FAILED = 2 , DBUS_STATUS_BUSY = 3 , DBUS_STATUS_SUCCESS = 0 ,
  DBUS_STATUS_FAILED = 2 , DBUS_STATUS_BUSY = 3
}
 
enum  riscv_poll_hart { RPH_NO_CHANGE , RPH_DISCOVERED_HALTED , RPH_DISCOVERED_RUNNING , RPH_ERROR }
 
enum  slot {
  SLOT0 , SLOT1 , SLOT_LAST , SLOT0 ,
  SLOT1 , SLOT_LAST , SLOT0 , SLOT1 ,
  SLOT_LAST
}
 

Functions

static int add_trigger (struct target *target, struct trigger *trigger)
 
static int cmp_csr_info (const void *p1, const void *p2)
 
 COMMAND_HANDLER (handle_info)
 
 COMMAND_HANDLER (riscv_authdata_read)
 
 COMMAND_HANDLER (riscv_authdata_write)
 
 COMMAND_HANDLER (riscv_dmi_read)
 
 COMMAND_HANDLER (riscv_dmi_write)
 
 COMMAND_HANDLER (riscv_reset_delays)
 
 COMMAND_HANDLER (riscv_resume_order)
 
 COMMAND_HANDLER (riscv_set_command_timeout_sec)
 
 COMMAND_HANDLER (riscv_set_ebreakm)
 
 COMMAND_HANDLER (riscv_set_ebreaks)
 
 COMMAND_HANDLER (riscv_set_ebreaku)
 
 COMMAND_HANDLER (riscv_set_enable_virt2phys)
 
 COMMAND_HANDLER (riscv_set_enable_virtual)
 
 COMMAND_HANDLER (riscv_set_expose_csrs)
 
 COMMAND_HANDLER (riscv_set_expose_custom)
 
 COMMAND_HANDLER (riscv_set_ir)
 
 COMMAND_HANDLER (riscv_set_mem_access)
 
 COMMAND_HANDLER (riscv_set_reset_timeout_sec)
 
 COMMAND_HANDLER (riscv_use_bscan_tunnel)
 
 COMMAND_HELPER (riscv_print_info_line, const char *section, const char *key, unsigned int value)
 
static int disable_triggers (struct target *target, riscv_reg_t *state)
 
static uint32_t dtmcontrol_scan (struct target *target, uint32_t out)
 
uint32_t dtmcontrol_scan_via_bscan (struct target *target, uint32_t out)
 
static int enable_triggers (struct target *target, riscv_reg_t *state)
 
static bool gdb_regno_cacheable (enum gdb_regno regno, bool write)
 If write is true: return true iff we are guaranteed that the register will contain exactly the value we just wrote when it's read. More...
 
const char * gdb_regno_name (enum gdb_regno regno)
 
static struct target_type * get_target_type (struct target *target)
 
static int halt_finish (struct target *target)
 
static int halt_go (struct target *target)
 
static int halt_prep (struct target *target)
 
static int maybe_add_trigger_t1 (struct target *target, struct trigger *trigger, uint64_t tdata1)
 
static int maybe_add_trigger_t2 (struct target *target, struct trigger *trigger, uint64_t tdata1)
 
static int maybe_add_trigger_t6 (struct target *target, struct trigger *trigger, uint64_t tdata1)
 
static int old_or_new_riscv_poll (struct target *target)
 
static int old_or_new_riscv_step (struct target *target, bool current, target_addr_t address, bool handle_breakpoints)
 
static int oldriscv_poll (struct target *target)
 
static int oldriscv_step (struct target *target, bool current, uint32_t address, bool handle_breakpoints)
 
static int parse_ranges (struct list_head *ranges, const char *tcl_arg, const char *reg_type, unsigned int max_val)
 
static int read_by_given_size (struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer, uint32_t access_size)
 Read one memory item of given "size". More...
 
static int register_get (struct reg *reg)
 
static int register_set (struct reg *reg, uint8_t *buf)
 
static int remove_trigger (struct target *target, struct trigger *trigger)
 
static int resume_finish (struct target *target)
 
static int resume_go (struct target *target, bool current, target_addr_t address, bool handle_breakpoints, bool debug_execution)
 Resume all the harts that have been prepped, as close to instantaneous as possible. More...
 
static int resume_prep (struct target *target, bool current, target_addr_t address, bool handle_breakpoints, bool debug_execution)
 Get everything ready to resume. More...
 
static int riscv_add_breakpoint (struct target *target, struct breakpoint *breakpoint)
 
void riscv_add_bscan_tunneled_scan (struct target *target, struct scan_field *field, riscv_bscan_tunneled_scan_context_t *ctxt)
 
int riscv_add_watchpoint (struct target *target, struct watchpoint *watchpoint)
 
static int riscv_address_translate (struct target *target, target_addr_t virtual, target_addr_t *physical)
 
static int riscv_arch_state (struct target *target)
 
static int riscv_assert_reset (struct target *target)
 
static int riscv_checksum_memory (struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
 
int riscv_count_harts (struct target *target)
 
static int riscv_create_target (struct target *target, Jim_Interp *interp)
 
int riscv_current_hartid (const struct target *target)
 
static unsigned int riscv_data_bits (struct target *target)
 
static int riscv_deassert_reset (struct target *target)
 
size_t riscv_debug_buffer_size (struct target *target)
 
static void riscv_deinit_target (struct target *target)
 
int riscv_dmi_write_u64_bits (struct target *target)
 
int riscv_enumerate_triggers (struct target *target)
 Count triggers, and initialize trigger_count for each hart. More...
 
static int riscv_examine (struct target *target)
 
int riscv_execute_debug_buffer (struct target *target)
 
void riscv_fill_dmi_nop_u64 (struct target *target, char *buf)
 
void riscv_fill_dmi_read_u64 (struct target *target, char *buf, int a)
 
void riscv_fill_dmi_write_u64 (struct target *target, char *buf, int a, uint64_t d)
 
static void riscv_free_registers (struct target *target)
 
static const char * riscv_get_gdb_arch (const struct target *target)
 
static int riscv_get_gdb_reg_list (struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
 
static int riscv_get_gdb_reg_list_internal (struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class, bool read)
 
static int riscv_get_gdb_reg_list_noread (struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
 
int riscv_get_register (struct target *target, riscv_reg_t *value, enum gdb_regno regid)
 Get register, from the cache if it's in there. More...
 
int riscv_halt (struct target *target)
 
static int riscv_halt_go_all_harts (struct target *target)
 
static enum riscv_halt_reason riscv_halt_reason (struct target *target, int hartid)
 
static int riscv_hit_watchpoint (struct target *target, struct watchpoint **hit_watchpoint)
 
static void riscv_info_init (struct target *target, struct riscv_info *r)
 
int riscv_init_registers (struct target *target)
 
static int riscv_init_target (struct command_context *cmd_ctx, struct target *target)
 
static void riscv_invalidate_register_cache (struct target *target)
 
bool riscv_is_halted (struct target *target)
 
static int riscv_mmu (struct target *target, int *enabled)
 
int riscv_openocd_poll (struct target *target)
 
int riscv_openocd_step (struct target *target, bool current, target_addr_t address, bool handle_breakpoints)
 
static enum riscv_poll_hart riscv_poll_hart (struct target *target, int hartid)
 
int riscv_read_by_any_size (struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 Read one memory item using any memory access size that will work. More...
 
riscv_insn_t riscv_read_debug_buffer (struct target *target, int index)
 
static int riscv_read_memory (struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 
static int riscv_read_phys_memory (struct target *target, target_addr_t phys_address, uint32_t size, uint32_t count, uint8_t *buffer)
 
static int riscv_remove_breakpoint (struct target *target, struct breakpoint *breakpoint)
 
int riscv_remove_watchpoint (struct target *target, struct watchpoint *watchpoint)
 
static int riscv_resume (struct target *target, bool current, target_addr_t address, bool handle_breakpoints, bool debug_execution, bool single_hart)
 
static int riscv_resume_go_all_harts (struct target *target)
 
static int riscv_resume_prep_all_harts (struct target *target)
 
static int riscv_run_algorithm (struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
 
static void riscv_sample_buf_maybe_add_timestamp (struct target *target, bool before)
 
int riscv_select_current_hart (struct target *target)
 
int riscv_set_current_hartid (struct target *target, int hartid)
 
int riscv_set_register (struct target *target, enum gdb_regno regid, riscv_reg_t value)
 This function is called when the debug user wants to change the value of a register. More...
 
static int riscv_step_rtos_hart (struct target *target)
 
bool riscv_supports_extension (struct target *target, char letter)
 
static int riscv_target_resume (struct target *target, bool current, target_addr_t address, bool handle_breakpoints, bool debug_execution)
 
static int riscv_virt2phys (struct target *target, target_addr_t virtual, target_addr_t *physical)
 
int riscv_write_by_any_size (struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 Write one memory item using any memory access size that will work. More...
 
int riscv_write_debug_buffer (struct target *target, int index, riscv_insn_t insn)
 
static int riscv_write_memory (struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
 
static int riscv_write_phys_memory (struct target *target, target_addr_t phys_address, uint32_t size, uint32_t count, const uint8_t *buffer)
 
unsigned int riscv_xlen (const struct target *target)
 
static unsigned int riscv_xlen_nonconst (struct target *target)
 
static int sample_memory (struct target *target)
 
void select_dmi_via_bscan (struct target *target)
 
static int set_debug_reason (struct target *target, enum riscv_halt_reason halt_reason)
 
static void trigger_from_breakpoint (struct trigger *trigger, const struct breakpoint *breakpoint)
 
static void trigger_from_watchpoint (struct trigger *trigger, const struct watchpoint *watchpoint)
 
static int write_by_given_size (struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer, uint32_t access_size)
 Write one memory item of given "size". More...
 

Variables

static struct scan_field _bscan_tunnel_data_register_select_dmi []
 
static struct scan_field _bscan_tunnel_nested_tap_select_dmi []
 
static const uint8_t bscan_one [4] = {1}
 
static struct scan_field * bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi
 
static uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi)
 
int bscan_tunnel_ir_width
 
static struct scan_field * bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi
 
static uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi)
 
static bscan_tunnel_type_t bscan_tunnel_type
 
static uint8_t bscan_tunneled_ir_width [4] = {5}
 
static const uint8_t bscan_zero [4] = {0}
 
static uint8_t ir_dbus [4] = {DBUS}
 
static uint8_t ir_dtmcontrol [4] = {DTMCONTROL}
 
static uint8_t ir_idcode [4] = {0x1}
 
static uint8_t ir_user4 [4]
 
static enum { ... }  resume_order
 
static const struct command_registration riscv_command_handlers []
 
int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC
 
bool riscv_ebreakm = true
 
bool riscv_ebreaks = true
 
bool riscv_ebreaku = true
 
static bool riscv_enable_virt2phys = true
 
bool riscv_enable_virtual
 
static const struct command_registration riscv_exec_command_handlers []
 
static struct reg_arch_type riscv_reg_arch_type
 
int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC
 
struct target_type riscv_target
 
struct scan_field select_dbus
 
struct scan_field select_dtmcontrol
 
struct scan_field select_idcode
 
static struct scan_field select_user4
 
static const virt2phys_info_t sv32
 
static const virt2phys_info_t sv39
 
static const virt2phys_info_t sv48
 

Macro Definition Documentation

◆ CSR_BPCONTROL_BPACTION

#define CSR_BPCONTROL_BPACTION   (0xff<<11)

Definition at line 38 of file riscv.c.

◆ CSR_BPCONTROL_BPMATCH

#define CSR_BPCONTROL_BPMATCH   (0xf<<7)

Definition at line 37 of file riscv.c.

◆ CSR_BPCONTROL_H

#define CSR_BPCONTROL_H   (1<<5)

Definition at line 35 of file riscv.c.

◆ CSR_BPCONTROL_M

#define CSR_BPCONTROL_M   (1<<6)

Definition at line 36 of file riscv.c.

◆ CSR_BPCONTROL_R

#define CSR_BPCONTROL_R   (1<<2)

Definition at line 32 of file riscv.c.

◆ CSR_BPCONTROL_S

#define CSR_BPCONTROL_S   (1<<4)

Definition at line 34 of file riscv.c.

◆ CSR_BPCONTROL_U

#define CSR_BPCONTROL_U   (1<<3)

Definition at line 33 of file riscv.c.

◆ CSR_BPCONTROL_W

#define CSR_BPCONTROL_W   (1<<1)

Definition at line 31 of file riscv.c.

◆ CSR_BPCONTROL_X

#define CSR_BPCONTROL_X   (1<<0)

Definition at line 30 of file riscv.c.

◆ DBUS

#define DBUS   0x11

Definition at line 55 of file riscv.c.

◆ DBUS_ADDRESS_START

#define DBUS_ADDRESS_START   36

Definition at line 70 of file riscv.c.

◆ DBUS_ADDRESS_UNKNOWN

#define DBUS_ADDRESS_UNKNOWN   0xffff

Definition at line 107 of file riscv.c.

◆ DBUS_DATA_SIZE

#define DBUS_DATA_SIZE   34

Definition at line 69 of file riscv.c.

◆ DBUS_DATA_START

#define DBUS_DATA_START   2

Definition at line 68 of file riscv.c.

◆ DBUS_OP_SIZE

#define DBUS_OP_SIZE   2

Definition at line 57 of file riscv.c.

◆ DBUS_OP_START

#define DBUS_OP_START   0

Definition at line 56 of file riscv.c.

◆ DEBUG_RAM_START

#define DEBUG_RAM_START   0x400

Definition at line 43 of file riscv.c.

◆ DEBUG_ROM_EXCEPTION

#define DEBUG_ROM_EXCEPTION   (DEBUG_ROM_START + 8)

Definition at line 42 of file riscv.c.

◆ DEBUG_ROM_RESUME

#define DEBUG_ROM_RESUME   (DEBUG_ROM_START + 4)

Definition at line 41 of file riscv.c.

◆ DEBUG_ROM_START

#define DEBUG_ROM_START   0x800

Definition at line 40 of file riscv.c.

◆ DECLARE_CSR

#define DECLARE_CSR (   name,
  number 
)    { number, #name },

◆ DMCONTROL

#define DMCONTROL   0x10

Definition at line 80 of file riscv.c.

◆ DMCONTROL_ACCESS

#define DMCONTROL_ACCESS   (7<<12)

Definition at line 86 of file riscv.c.

◆ DMCONTROL_AUTOINCREMENT

#define DMCONTROL_AUTOINCREMENT   (1<<15)

Definition at line 85 of file riscv.c.

◆ DMCONTROL_BUSERROR

#define DMCONTROL_BUSERROR   (7<<19)

Definition at line 83 of file riscv.c.

◆ DMCONTROL_FULLRESET

#define DMCONTROL_FULLRESET   1

Definition at line 89 of file riscv.c.

◆ DMCONTROL_HALTNOT

#define DMCONTROL_HALTNOT   (((uint64_t)1)<<32)

Definition at line 82 of file riscv.c.

◆ DMCONTROL_HARTID

#define DMCONTROL_HARTID   (0x3ff<<2)

Definition at line 87 of file riscv.c.

◆ DMCONTROL_INTERRUPT

#define DMCONTROL_INTERRUPT   (((uint64_t)1)<<33)

Definition at line 81 of file riscv.c.

◆ DMCONTROL_NDRESET

#define DMCONTROL_NDRESET   (1<<1)

Definition at line 88 of file riscv.c.

◆ DMCONTROL_SERIAL

#define DMCONTROL_SERIAL   (3<<16)

Definition at line 84 of file riscv.c.

◆ DMINFO

#define DMINFO   0x11

Definition at line 91 of file riscv.c.

◆ DMINFO_ABUSSIZE

#define DMINFO_ABUSSIZE   (0x7fU<<25)

Definition at line 92 of file riscv.c.

◆ DMINFO_ACCESS128

#define DMINFO_ACCESS128   (1<<20)

Definition at line 94 of file riscv.c.

◆ DMINFO_ACCESS16

#define DMINFO_ACCESS16   (1<<17)

Definition at line 97 of file riscv.c.

◆ DMINFO_ACCESS32

#define DMINFO_ACCESS32   (1<<18)

Definition at line 96 of file riscv.c.

◆ DMINFO_ACCESS64

#define DMINFO_ACCESS64   (1<<19)

Definition at line 95 of file riscv.c.

◆ DMINFO_ACCESS8

#define DMINFO_ACCESS8   (1<<16)

Definition at line 98 of file riscv.c.

◆ DMINFO_AUTHBUSY

#define DMINFO_AUTHBUSY   (1<<4)

Definition at line 101 of file riscv.c.

◆ DMINFO_AUTHENTICATED

#define DMINFO_AUTHENTICATED   (1<<5)

Definition at line 100 of file riscv.c.

◆ DMINFO_AUTHTYPE

#define DMINFO_AUTHTYPE   (3<<2)

Definition at line 102 of file riscv.c.

◆ DMINFO_DRAMSIZE

#define DMINFO_DRAMSIZE   (0x3f<<10)

Definition at line 99 of file riscv.c.

◆ DMINFO_SERIALCOUNT

#define DMINFO_SERIALCOUNT   (0xf<<21)

Definition at line 93 of file riscv.c.

◆ DMINFO_VERSION

#define DMINFO_VERSION   3

Definition at line 103 of file riscv.c.

◆ DRAM_CACHE_SIZE

#define DRAM_CACHE_SIZE   16

Definition at line 110 of file riscv.c.

◆ DTMCONTROL

#define DTMCONTROL   0x10

Definition at line 49 of file riscv.c.

◆ DTMCONTROL_ADDRBITS

#define DTMCONTROL_ADDRBITS   (0xf<<4)

Definition at line 52 of file riscv.c.

◆ DTMCONTROL_DBUS_RESET

#define DTMCONTROL_DBUS_RESET   (1<<16)

Definition at line 50 of file riscv.c.

◆ DTMCONTROL_IDLE

#define DTMCONTROL_IDLE   (7<<10)

Definition at line 51 of file riscv.c.

◆ DTMCONTROL_VERSION

#define DTMCONTROL_VERSION   (0xf)

Definition at line 53 of file riscv.c.

◆ get_field

#define get_field (   reg,
  mask 
)    (((reg) & (mask)) / ((mask) & ~((mask) << 1)))

Definition at line 26 of file riscv.c.

◆ MAX_HWBPS

#define MAX_HWBPS   16

Definition at line 109 of file riscv.c.

◆ set_field

#define set_field (   reg,
  mask,
  val 
)    (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))

Definition at line 27 of file riscv.c.

◆ SETHALTNOT

#define SETHALTNOT   0x10c

Definition at line 45 of file riscv.c.

Typedef Documentation

◆ slot_t

typedef enum slot slot_t

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
RO_NORMAL 
RO_REVERSED 

Definition at line 215 of file riscv.c.

◆ dbus_op_t

enum dbus_op_t
Enumerator
DBUS_OP_NOP 
DBUS_OP_READ 
DBUS_OP_WRITE 
DBUS_OP_NOP 
DBUS_OP_READ 
DBUS_OP_WRITE 

Definition at line 58 of file riscv.c.

◆ dbus_status_t

enum dbus_status_t
Enumerator
DBUS_STATUS_SUCCESS 
DBUS_STATUS_FAILED 
DBUS_STATUS_BUSY 
DBUS_STATUS_SUCCESS 
DBUS_STATUS_FAILED 
DBUS_STATUS_BUSY 

Definition at line 63 of file riscv.c.

◆ riscv_poll_hart

enum riscv_poll_hart
Enumerator
RPH_NO_CHANGE 
RPH_DISCOVERED_HALTED 
RPH_DISCOVERED_RUNNING 
RPH_ERROR 

Definition at line 2077 of file riscv.c.

◆ slot

enum slot
Enumerator
SLOT0 
SLOT1 
SLOT_LAST 
SLOT0 
SLOT1 
SLOT_LAST 
SLOT0 
SLOT1 
SLOT_LAST 

Definition at line 72 of file riscv.c.

Function Documentation

◆ add_trigger()

static int add_trigger ( struct target *  target,
struct trigger *  trigger 
)
static

Definition at line 689 of file riscv.c.

References target::coreid, ERROR_FAIL, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, GDB_REGNO_TDATA1, GDB_REGNO_TSELECT, get_field, LOG_DEBUG, LOG_ERROR, maybe_add_trigger_t1(), maybe_add_trigger_t2(), maybe_add_trigger_t6(), MCONTROL_TYPE, riscv_enumerate_triggers(), riscv_get_register(), RISCV_INFO, riscv_set_register(), riscv_xlen(), type, and trigger::unique_id.

Referenced by riscv_add_breakpoint(), and riscv_add_watchpoint().

◆ cmp_csr_info()

static int cmp_csr_info ( const void *  p1,
const void *  p2 
)
static

Definition at line 3783 of file riscv.c.

Referenced by riscv_init_registers().

◆ COMMAND_HANDLER() [1/19]

COMMAND_HANDLER ( handle_info  )

Definition at line 2844 of file riscv.c.

References CALL_COMMAND_HANDLER, CMD, CMD_CTX, get_current_target(), riscv_enumerate_triggers(), RISCV_INFO, and riscv_xlen().

◆ COMMAND_HANDLER() [2/19]

COMMAND_HANDLER ( riscv_authdata_read  )

Definition at line 2593 of file riscv.c.

References CMD, CMD_ARGC, CMD_ARGV, CMD_CTX, COMMAND_PARSE_NUMBER, command_print_sameline(), ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, get_current_target(), LOG_ERROR, and RISCV_INFO.

◆ COMMAND_HANDLER() [3/19]

COMMAND_HANDLER ( riscv_authdata_write  )

Definition at line 2629 of file riscv.c.

References CMD_ARGC, CMD_ARGV, CMD_CTX, COMMAND_PARSE_NUMBER, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, get_current_target(), LOG_ERROR, and RISCV_INFO.

◆ COMMAND_HANDLER() [4/19]

COMMAND_HANDLER ( riscv_dmi_read  )

Definition at line 2655 of file riscv.c.

References address, CMD, CMD_ARGC, CMD_ARGV, CMD_CTX, COMMAND_PARSE_NUMBER, command_print(), ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, get_current_target(), LOG_ERROR, and RISCV_INFO.

◆ COMMAND_HANDLER() [5/19]

COMMAND_HANDLER ( riscv_dmi_write  )

Definition at line 2688 of file riscv.c.

References address, CMD_ARGC, CMD_ARGV, CMD_CTX, COMMAND_PARSE_NUMBER, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, get_current_target(), LOG_ERROR, and RISCV_INFO.

◆ COMMAND_HANDLER() [6/19]

COMMAND_HANDLER ( riscv_reset_delays  )

Definition at line 2710 of file riscv.c.

References CMD_ARGC, CMD_ARGV, CMD_CTX, COMMAND_PARSE_NUMBER, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, get_current_target(), LOG_ERROR, and RISCV_INFO.

◆ COMMAND_HANDLER() [7/19]

COMMAND_HANDLER ( riscv_resume_order  )

Definition at line 2750 of file riscv.c.

References CMD_ARGC, CMD_ARGV, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, LOG_ERROR, resume_order, RO_NORMAL, and RO_REVERSED.

◆ COMMAND_HANDLER() [8/19]

COMMAND_HANDLER ( riscv_set_command_timeout_sec  )

Definition at line 2333 of file riscv.c.

References CMD_ARGC, CMD_ARGV, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, LOG_ERROR, and riscv_command_timeout_sec.

◆ COMMAND_HANDLER() [9/19]

COMMAND_HANDLER ( riscv_set_ebreakm  )

Definition at line 2805 of file riscv.c.

References CMD_ARGC, CMD_ARGV, COMMAND_PARSE_ON_OFF, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, LOG_ERROR, and riscv_ebreakm.

◆ COMMAND_HANDLER() [10/19]

COMMAND_HANDLER ( riscv_set_ebreaks  )

Definition at line 2815 of file riscv.c.

References CMD_ARGC, CMD_ARGV, COMMAND_PARSE_ON_OFF, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, LOG_ERROR, and riscv_ebreaks.

◆ COMMAND_HANDLER() [11/19]

COMMAND_HANDLER ( riscv_set_ebreaku  )

Definition at line 2825 of file riscv.c.

References CMD_ARGC, CMD_ARGV, COMMAND_PARSE_ON_OFF, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, LOG_ERROR, and riscv_ebreaku.

◆ COMMAND_HANDLER() [12/19]

COMMAND_HANDLER ( riscv_set_enable_virt2phys  )

Definition at line 2795 of file riscv.c.

References CMD_ARGC, CMD_ARGV, COMMAND_PARSE_ON_OFF, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, LOG_ERROR, and riscv_enable_virt2phys.

◆ COMMAND_HANDLER() [13/19]

COMMAND_HANDLER ( riscv_set_enable_virtual  )

Definition at line 2418 of file riscv.c.

References CMD_ARGC, CMD_ARGV, COMMAND_PARSE_ON_OFF, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, LOG_ERROR, and riscv_enable_virtual.

◆ COMMAND_HANDLER() [14/19]

COMMAND_HANDLER ( riscv_set_expose_csrs  )

Definition at line 2553 of file riscv.c.

References CMD_ARGC, CMD_ARGV, CMD_CTX, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, get_current_target(), info, LOG_ERROR, parse_ranges(), and RISCV_INFO.

◆ COMMAND_HANDLER() [15/19]

COMMAND_HANDLER ( riscv_set_expose_custom  )

Definition at line 2573 of file riscv.c.

References CMD_ARGC, CMD_ARGV, CMD_CTX, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, get_current_target(), info, LOG_ERROR, parse_ranges(), and RISCV_INFO.

◆ COMMAND_HANDLER() [16/19]

COMMAND_HANDLER ( riscv_set_ir  )

Definition at line 2728 of file riscv.c.

References buf_set_u32(), CMD_ARGC, CMD_ARGV, COMMAND_PARSE_NUMBER, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, ir_dbus, ir_dtmcontrol, ir_idcode, and LOG_ERROR.

◆ COMMAND_HANDLER() [17/19]

COMMAND_HANDLER ( riscv_set_mem_access  )

Definition at line 2366 of file riscv.c.

References CMD_ARGC, CMD_ARGV, CMD_CTX, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, get_current_target(), LOG_ERROR, RISCV_INFO, RISCV_MEM_ACCESS_ABSTRACT, RISCV_MEM_ACCESS_PROGBUF, RISCV_MEM_ACCESS_SYSBUS, RISCV_MEM_ACCESS_UNSPECIFIED, and RISCV_NUM_MEM_ACCESS_METHODS.

◆ COMMAND_HANDLER() [18/19]

COMMAND_HANDLER ( riscv_set_reset_timeout_sec  )

Definition at line 2350 of file riscv.c.

References CMD_ARGC, CMD_ARGV, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, LOG_ERROR, and riscv_reset_timeout_sec.

◆ COMMAND_HANDLER() [19/19]

COMMAND_HANDLER ( riscv_use_bscan_tunnel  )

Definition at line 2769 of file riscv.c.

References BSCAN_TUNNEL_DATA_REGISTER, bscan_tunnel_ir_width, BSCAN_TUNNEL_NESTED_TAP, bscan_tunnel_type, CMD_ARGC, CMD_ARGV, COMMAND_PARSE_NUMBER, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, LOG_ERROR, and LOG_INFO.

◆ COMMAND_HELPER()

COMMAND_HELPER ( riscv_print_info_line  ,
const char *  section,
const char *  key,
unsigned int  value 
)

Definition at line 2835 of file riscv.c.

References CMD, and command_print().

◆ disable_triggers()

static int disable_triggers ( struct target *  target,
riscv_reg_t *  state 
)
static

Definition at line 1308 of file riscv.c.

References ERROR_FAIL, ERROR_OK, GDB_REGNO_TDATA1, GDB_REGNO_TSELECT, watchpoint::is_set, LOG_DEBUG, MCONTROL_DMODE, watchpoint::next, riscv_enumerate_triggers(), riscv_get_register(), RISCV_INFO, riscv_remove_watchpoint(), riscv_set_register(), riscv_xlen(), state, and target::watchpoints.

Referenced by resume_prep(), and riscv_openocd_step().

◆ dtmcontrol_scan()

static uint32_t dtmcontrol_scan ( struct target *  target,
uint32_t  out 
)
static

Definition at line 377 of file riscv.c.

References bscan_tunnel_ir_width, buf_get_u32(), buf_set_u32(), dtmcontrol_scan_via_bscan(), ERROR_OK, scan_field::in_value, jtag_add_dr_scan(), jtag_add_ir_scan(), jtag_execute_queue(), LOG_DEBUG, LOG_ERROR, scan_field::num_bits, scan_field::out_value, select_dbus, select_dtmcontrol, target::tap, and TAP_IDLE.

Referenced by riscv_examine().

◆ dtmcontrol_scan_via_bscan()

uint32_t dtmcontrol_scan_via_bscan ( struct target *  target,
uint32_t  out 
)

Definition at line 293 of file riscv.c.

References ARRAY_SIZE, bscan_one, BSCAN_TUNNEL_DATA_REGISTER, bscan_tunnel_ir_width, bscan_tunnel_type, bscan_zero, buf_get_u32(), buf_set_u32(), ERROR_OK, scan_field::in_value, ir_dtmcontrol, jtag_add_dr_scan(), jtag_add_ir_scan(), jtag_execute_queue(), LOG_DEBUG, LOG_ERROR, NULL, scan_field::num_bits, scan_field::out_value, select_dmi_via_bscan(), select_user4, target::tap, and TAP_IDLE.

Referenced by dtmcontrol_scan().

◆ enable_triggers()

static int enable_triggers ( struct target *  target,
riscv_reg_t *  state 
)
static

Definition at line 1356 of file riscv.c.

References ERROR_FAIL, ERROR_OK, GDB_REGNO_TDATA1, GDB_REGNO_TSELECT, LOG_DEBUG, watchpoint::next, riscv_add_watchpoint(), riscv_get_register(), RISCV_INFO, riscv_set_register(), state, and target::watchpoints.

Referenced by resume_prep(), and riscv_openocd_step().

◆ gdb_regno_cacheable()

static bool gdb_regno_cacheable ( enum gdb_regno  regno,
bool  write 
)
static

If write is true: return true iff we are guaranteed that the register will contain exactly the value we just wrote when it's read.

If write is false: return true iff we are guaranteed that the register will read the same value in the future as the value we just read.

Definition at line 3261 of file riscv.c.

References GDB_REGNO_DCSR, GDB_REGNO_DPC, GDB_REGNO_DSCRATCH0, GDB_REGNO_FPR0, GDB_REGNO_FPR31, GDB_REGNO_MCAUSE, GDB_REGNO_MEPC, GDB_REGNO_MISA, GDB_REGNO_MSTATUS, GDB_REGNO_SATP, GDB_REGNO_TDATA1, GDB_REGNO_TDATA2, GDB_REGNO_TSELECT, GDB_REGNO_V0, GDB_REGNO_V31, GDB_REGNO_VL, GDB_REGNO_VLENB, GDB_REGNO_VSTART, GDB_REGNO_VTYPE, GDB_REGNO_VXRM, GDB_REGNO_VXSAT, and GDB_REGNO_XPR31.

Referenced by register_get(), register_set(), riscv_get_register(), and riscv_set_register().

◆ gdb_regno_name()

const char* gdb_regno_name ( enum gdb_regno  regno)

Definition at line 3513 of file riscv.c.

References GDB_REGNO_A0, GDB_REGNO_A1, GDB_REGNO_A2, GDB_REGNO_A3, GDB_REGNO_A4, GDB_REGNO_A5, GDB_REGNO_A6, GDB_REGNO_A7, GDB_REGNO_CSR0, GDB_REGNO_CSR4095, GDB_REGNO_DCSR, GDB_REGNO_DPC, GDB_REGNO_DSCRATCH0, GDB_REGNO_FPR0, GDB_REGNO_FPR31, GDB_REGNO_GP, GDB_REGNO_MCAUSE, GDB_REGNO_MEPC, GDB_REGNO_MISA, GDB_REGNO_MSTATUS, GDB_REGNO_PC, GDB_REGNO_PRIV, GDB_REGNO_RA, GDB_REGNO_S0, GDB_REGNO_S1, GDB_REGNO_S10, GDB_REGNO_S11, GDB_REGNO_S2, GDB_REGNO_S3, GDB_REGNO_S4, GDB_REGNO_S5, GDB_REGNO_S6, GDB_REGNO_S7, GDB_REGNO_S8, GDB_REGNO_S9, GDB_REGNO_SATP, GDB_REGNO_SP, GDB_REGNO_T0, GDB_REGNO_T1, GDB_REGNO_T2, GDB_REGNO_T3, GDB_REGNO_T4, GDB_REGNO_T5, GDB_REGNO_T6, GDB_REGNO_TDATA1, GDB_REGNO_TDATA2, GDB_REGNO_TP, GDB_REGNO_TSELECT, GDB_REGNO_V0, GDB_REGNO_V1, GDB_REGNO_V10, GDB_REGNO_V11, GDB_REGNO_V12, GDB_REGNO_V13, GDB_REGNO_V14, GDB_REGNO_V15, GDB_REGNO_V16, GDB_REGNO_V17, GDB_REGNO_V18, GDB_REGNO_V19, GDB_REGNO_V2, GDB_REGNO_V20, GDB_REGNO_V21, GDB_REGNO_V22, GDB_REGNO_V23, GDB_REGNO_V24, GDB_REGNO_V25, GDB_REGNO_V26, GDB_REGNO_V27, GDB_REGNO_V28, GDB_REGNO_V29, GDB_REGNO_V3, GDB_REGNO_V30, GDB_REGNO_V31, GDB_REGNO_V4, GDB_REGNO_V5, GDB_REGNO_V6, GDB_REGNO_V7, GDB_REGNO_V8, GDB_REGNO_V9, GDB_REGNO_VL, GDB_REGNO_VTYPE, GDB_REGNO_XPR31, and GDB_REGNO_ZERO.

Referenced by access_register_command(), read_remote_csr(), register_get(), register_read(), register_read_direct(), register_set(), register_write(), register_write_direct(), riscv013_get_register(), riscv013_set_register(), riscv_get_register(), riscv_run_algorithm(), and riscv_set_register().

◆ get_target_type()

static struct target_type* get_target_type ( struct target *  target)
static

Definition at line 411 of file riscv.c.

References target::arch_info, info, LOG_ERROR, NULL, riscv011_target, riscv013_target, and RISCV_INFO.

Referenced by halt_go(), oldriscv_poll(), oldriscv_step(), resume_go(), riscv_arch_state(), riscv_assert_reset(), riscv_deassert_reset(), riscv_deinit_target(), riscv_examine(), riscv_halt(), riscv_write_memory(), and riscv_write_phys_memory().

◆ halt_finish()

static int halt_finish ( struct target *  target)
static

Definition at line 1219 of file riscv.c.

References target_call_event_callbacks(), and TARGET_EVENT_HALTED.

Referenced by riscv_halt().

◆ halt_go()

static int halt_go ( struct target *  target)
static

Definition at line 1202 of file riscv.c.

References DBG_REASON_DBGRQ, DBG_REASON_NOTHALTED, target::debug_reason, get_target_type(), target_type::halt, riscv_halt_go_all_harts(), RISCV_INFO, target::state, and TARGET_HALTED.

Referenced by riscv_halt().

◆ halt_prep()

static int halt_prep ( struct target *  target)
static

Definition at line 1164 of file riscv.c.

References target::debug_reason, ERROR_FAIL, ERROR_OK, LOG_DEBUG, RISCV_INFO, riscv_is_halted(), riscv_select_current_hart(), and target_name().

Referenced by riscv_halt().

◆ maybe_add_trigger_t1()

static int maybe_add_trigger_t1 ( struct target *  target,
struct trigger *  trigger,
uint64_t  tdata1 
)
static

Definition at line 534 of file riscv.c.

References trigger::address, BIT, ERROR_FAIL, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, trigger::execute, GDB_REGNO_TDATA1, GDB_REGNO_TDATA2, LOG_DEBUG, trigger::read, riscv_get_register(), RISCV_INFO, riscv_set_register(), set_field, and trigger::write.

Referenced by add_trigger().

◆ maybe_add_trigger_t2()

static int maybe_add_trigger_t2 ( struct target *  target,
struct trigger *  trigger,
uint64_t  tdata1 
)
static

Definition at line 587 of file riscv.c.

References trigger::address, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, trigger::execute, GDB_REGNO_TDATA1, GDB_REGNO_TDATA2, LOG_DEBUG, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE, MCONTROL_DMODE, MCONTROL_EXECUTE, MCONTROL_LOAD, MCONTROL_M, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL, MCONTROL_S, MCONTROL_STORE, MCONTROL_U, trigger::read, riscv_get_register(), RISCV_INFO, riscv_set_register(), riscv_xlen(), set_field, and trigger::write.

Referenced by add_trigger().

◆ maybe_add_trigger_t6()

static int maybe_add_trigger_t6 ( struct target *  target,
struct trigger *  trigger,
uint64_t  tdata1 
)
static

Definition at line 637 of file riscv.c.

References trigger::address, CSR_MCONTROL6_ACTION, CSR_MCONTROL6_EXECUTE, CSR_MCONTROL6_LOAD, CSR_MCONTROL6_M, CSR_MCONTROL6_MATCH, CSR_MCONTROL6_S, CSR_MCONTROL6_STORE, CSR_MCONTROL6_U, CSR_MCONTROL6_VS, CSR_MCONTROL6_VU, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, trigger::execute, GDB_REGNO_TDATA1, GDB_REGNO_TDATA2, LOG_DEBUG, MCONTROL_ACTION_DEBUG_MODE, MCONTROL_DMODE, MCONTROL_MATCH_EQUAL, trigger::read, riscv_get_register(), RISCV_INFO, riscv_set_register(), riscv_xlen(), set_field, and trigger::write.

Referenced by add_trigger().

◆ old_or_new_riscv_poll()

static int old_or_new_riscv_poll ( struct target *  target)
static

Definition at line 1150 of file riscv.c.

References oldriscv_poll(), RISCV_INFO, and riscv_openocd_poll().

Referenced by riscv_run_algorithm().

◆ old_or_new_riscv_step()

static int old_or_new_riscv_step ( struct target *  target,
bool  current,
target_addr_t  address,
bool  handle_breakpoints 
)
static

Definition at line 1106 of file riscv.c.

References address, LOG_DEBUG, oldriscv_step(), RISCV_INFO, and riscv_openocd_step().

Referenced by resume_prep().

◆ oldriscv_poll()

static int oldriscv_poll ( struct target *  target)
static

Definition at line 1144 of file riscv.c.

References get_target_type(), and target_type::poll.

Referenced by old_or_new_riscv_poll().

◆ oldriscv_step()

static int oldriscv_step ( struct target *  target,
bool  current,
uint32_t  address,
bool  handle_breakpoints 
)
static

Definition at line 1099 of file riscv.c.

References address, get_target_type(), and target_type::step.

Referenced by old_or_new_riscv_step().

◆ parse_ranges()

static int parse_ranges ( struct list_head *  ranges,
const char *  tcl_arg,
const char *  reg_type,
unsigned int  max_val 
)
static

Definition at line 2428 of file riscv.c.

References ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, list_add(), list_for_each_entry, LOG_ERROR, LOG_WARNING, low, range_list_t::low, name, range_list_t::name, and NULL.

Referenced by COMMAND_HANDLER().

◆ read_by_given_size()

static int read_by_given_size ( struct target *  target,
target_addr_t  address,
uint32_t  size,
uint8_t *  buffer,
uint32_t  access_size 
)
static

Read one memory item of given "size".

Use memory access of given "access_size". Read larger section of memory and pick out the required portion, if needed.

Definition at line 778 of file riscv.c.

References address, buffer, ERROR_FAIL, ERROR_OK, size, and target_read_memory().

Referenced by riscv_read_by_any_size().

◆ register_get()

static int register_get ( struct reg *  reg)
static

Definition at line 3695 of file riscv.c.

References reg::arch_info, buf_set_u64(), buf_to_hex_str(), ERROR_FAIL, ERROR_OK, gdb_regno_cacheable(), gdb_regno_name(), GDB_REGNO_V0, GDB_REGNO_V31, LOG_DEBUG, LOG_ERROR, reg::name, reg::number, riscv_get_register(), RISCV_INFO, reg::size, riscv_reg_info_t::target, target_name(), reg::valid, and reg::value.

◆ register_set()

static int register_set ( struct reg *  reg,
uint8_t *  buf 
)
static

Definition at line 3725 of file riscv.c.

References reg::arch_info, buf_get_u64(), buf_to_hex_str(), DIV_ROUND_UP, ERROR_FAIL, ERROR_OK, gdb_regno_cacheable(), gdb_regno_name(), GDB_REGNO_TDATA1, GDB_REGNO_TDATA2, GDB_REGNO_V0, GDB_REGNO_V31, GDB_REGNO_ZERO, LOG_DEBUG, LOG_ERROR, reg::name, reg::number, riscv_enumerate_triggers(), RISCV_INFO, riscv_set_register(), reg::size, riscv_reg_info_t::target, target_name(), reg::valid, and reg::value.

◆ remove_trigger()

static int remove_trigger ( struct target *  target,
struct trigger *  trigger 
)
static

Definition at line 913 of file riscv.c.

References target::coreid, ERROR_FAIL, ERROR_OK, GDB_REGNO_TDATA1, GDB_REGNO_TSELECT, LOG_DEBUG, LOG_ERROR, riscv_enumerate_triggers(), riscv_get_register(), RISCV_INFO, riscv_set_register(), and trigger::unique_id.

Referenced by riscv_remove_breakpoint(), and riscv_remove_watchpoint().

◆ resume_finish()

static int resume_finish ( struct target *  target)
static

Definition at line 1451 of file riscv.c.

References DBG_REASON_NOTHALTED, target::debug_reason, target::reg_cache, register_cache_invalidate(), target::state, target_call_event_callbacks(), TARGET_EVENT_RESUMED, and TARGET_RUNNING.

Referenced by riscv_resume().

◆ resume_go()

static int resume_go ( struct target *  target,
bool  current,
target_addr_t  address,
bool  handle_breakpoints,
bool  debug_execution 
)
static

Resume all the harts that have been prepped, as close to instantaneous as possible.

Definition at line 1435 of file riscv.c.

References address, get_target_type(), target_type::resume, RISCV_INFO, and riscv_resume_go_all_harts().

Referenced by riscv_resume().

◆ resume_prep()

static int resume_prep ( struct target *  target,
bool  current,
target_addr_t  address,
bool  handle_breakpoints,
bool  debug_execution 
)
static

Get everything ready to resume.

Definition at line 1396 of file riscv.c.

References address, target::coreid, DBG_REASON_WATCHPOINT, target::debug_reason, disable_triggers(), enable_triggers(), ERROR_FAIL, ERROR_OK, GDB_REGNO_PC, LOG_DEBUG, old_or_new_riscv_step(), RISCV_INFO, RISCV_MAX_HWBPS, riscv_resume_prep_all_harts(), and riscv_set_register().

Referenced by riscv_resume().

◆ riscv_add_breakpoint()

static int riscv_add_breakpoint ( struct target *  target,
struct breakpoint *  breakpoint 
)
static
Todo:
check RVC for size/alignment

Definition at line 865 of file riscv.c.

References add_trigger(), breakpoint::address, BKPT_HARD, BKPT_SOFT, buf_set_u32(), target::coreid, ebreak(), ebreak_c(), ERROR_FAIL, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, breakpoint::is_set, breakpoint::length, LOG_DEBUG, LOG_ERROR, LOG_INFO, breakpoint::orig_instr, riscv_read_by_any_size(), riscv_write_by_any_size(), TARGET_PRIxADDR, trigger_from_breakpoint(), and breakpoint::type.

◆ riscv_add_bscan_tunneled_scan()

void riscv_add_bscan_tunneled_scan ( struct target *  target,
struct scan_field *  field,
riscv_bscan_tunneled_scan_context_t *  ctxt 
)

Definition at line 4416 of file riscv.c.

References ARRAY_SIZE, bscan_one, BSCAN_TUNNEL_DATA_REGISTER, bscan_tunnel_type, bscan_zero, scan_field::in_value, jtag_add_dr_scan(), jtag_add_ir_scan(), scan_field::num_bits, scan_field::out_value, select_user4, target::tap, TAP_IDLE, riscv_bscan_tunneled_scan_context_t::tunneled_dr, and riscv_bscan_tunneled_scan_context_t::tunneled_dr_width.

Referenced by dmi_scan(), and riscv_batch_run().

◆ riscv_add_watchpoint()

int riscv_add_watchpoint ( struct target *  target,
struct watchpoint *  watchpoint 
)

Definition at line 988 of file riscv.c.

References add_trigger(), ERROR_OK, watchpoint::is_set, and trigger_from_watchpoint().

Referenced by enable_triggers(), and strict_step().

◆ riscv_address_translate()

static int riscv_address_translate ( struct target *  target,
target_addr_t  virtual,
target_addr_t *  physical 
)
static

Definition at line 1568 of file riscv.c.

References buf_get_u32(), buf_get_u64(), buffer, ERROR_FAIL, ERROR_OK, GDB_REGNO_SATP, get_field, info, LOG_DEBUG, LOG_ERROR, mask, mode, PTE_PPN_SHIFT, PTE_R, PTE_V, PTE_W, PTE_X, riscv_get_register(), RISCV_INFO, RISCV_PGSHIFT, RISCV_SATP_MODE, RISCV_SATP_PPN, riscv_xlen(), SATP_MODE_OFF, SATP_MODE_SV32, SATP_MODE_SV39, SATP_MODE_SV48, sv32, sv39, sv48, and TARGET_PRIxADDR.

Referenced by riscv_virt2phys().

◆ riscv_arch_state()

static int riscv_arch_state ( struct target *  target)
static

Definition at line 1821 of file riscv.c.

References target_type::arch_state, and get_target_type().

◆ riscv_assert_reset()

static int riscv_assert_reset ( struct target *  target)
static

Definition at line 1271 of file riscv.c.

References target_type::assert_reset, target::coreid, get_target_type(), LOG_DEBUG, and riscv_invalidate_register_cache().

◆ riscv_checksum_memory()

static int riscv_checksum_memory ( struct target *  target,
target_addr_t  address,
uint32_t  count,
uint32_t *  checksum 
)
static

Definition at line 1989 of file riscv.c.

References address, working_area::address, buf_get_u32(), buf_set_u64(), count, destroy_reg_param(), ERROR_FAIL, ERROR_OK, init_reg_param(), LOG_DEBUG, LOG_ERROR, NULL, PARAM_IN_OUT, PARAM_OUT, riscv_xlen(), working_area::size, TARGET_ADDR_FMT, target_alloc_working_area(), target_free_working_area(), TARGET_PRIxADDR, target_run_algorithm(), target_write_buffer(), and reg_param::value.

◆ riscv_count_harts()

int riscv_count_harts ( struct target *  target)

Definition at line 3243 of file riscv.c.

References RISCV_INFO.

Referenced by deassert_reset(), and examine().

◆ riscv_create_target()

static int riscv_create_target ( struct target *  target,
Jim_Interp *  interp 
)
static

Definition at line 430 of file riscv.c.

References target::arch_info, ERROR_FAIL, ERROR_OK, LOG_DEBUG, LOG_ERROR, and riscv_info_init().

◆ riscv_current_hartid()

int riscv_current_hartid ( const struct target *  target)

Definition at line 3237 of file riscv.c.

References RISCV_INFO.

Referenced by register_read_direct(), register_write_direct(), riscv013_halt_reason(), riscv_hit_watchpoint(), riscv_openocd_poll(), and riscv_set_current_hartid().

◆ riscv_data_bits()

static unsigned int riscv_data_bits ( struct target *  target)
static

Definition at line 3061 of file riscv.c.

References RISCV_INFO, and riscv_xlen().

◆ riscv_deassert_reset()

static int riscv_deassert_reset ( struct target *  target)
static

Definition at line 1279 of file riscv.c.

References target::coreid, target_type::deassert_reset, get_target_type(), and LOG_DEBUG.

◆ riscv_debug_buffer_size()

size_t riscv_debug_buffer_size ( struct target *  target)

Definition at line 3389 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_program_ebreak(), riscv_program_exec(), and riscv_program_insert().

◆ riscv_deinit_target()

static void riscv_deinit_target ( struct target *  target)
static

Definition at line 489 of file riscv.c.

References target::arch_info, target_type::deinit_target, get_target_type(), info, list_for_each_entry_safe, LOG_DEBUG, range_list_t::name, NULL, and riscv_free_registers().

◆ riscv_dmi_write_u64_bits()

int riscv_dmi_write_u64_bits ( struct target *  target)

Definition at line 3432 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_batch_add_dmi_read(), riscv_batch_add_dmi_write(), and riscv_batch_add_nop().

◆ riscv_enumerate_triggers()

int riscv_enumerate_triggers ( struct target *  target)

Count triggers, and initialize trigger_count for each hart.

trigger_count is initialized even if this function fails to discover something. Disable any hardware triggers that have dmode set. We can't have set them ourselves. Maybe they're left over from some killed debug session.

Definition at line 3445 of file riscv.c.

References ERROR_OK, GDB_REGNO_TDATA1, GDB_REGNO_TSELECT, get_field, LOG_DEBUG, LOG_INFO, MCONTROL_DMODE, MCONTROL_TYPE, riscv_get_register(), RISCV_INFO, RISCV_MAX_TRIGGERS, riscv_set_register(), riscv_xlen(), target_name(), and type.

Referenced by add_trigger(), COMMAND_HANDLER(), disable_triggers(), handle_halt(), register_set(), and remove_trigger().

◆ riscv_examine()

static int riscv_examine ( struct target *  target)
static

Definition at line 1117 of file riscv.c.

References dtmcontrol_scan(), DTMCONTROL_VERSION, ERROR_FAIL, ERROR_OK, target_type::examine, get_field, get_target_type(), info, target_type::init_target, LOG_DEBUG, RISCV_INFO, and target_was_examined().

◆ riscv_execute_debug_buffer()

int riscv_execute_debug_buffer ( struct target *  target)

Definition at line 3408 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_program_exec().

◆ riscv_fill_dmi_nop_u64()

void riscv_fill_dmi_nop_u64 ( struct target *  target,
char *  buf 
)

Definition at line 3426 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_batch_add_dmi_read(), riscv_batch_add_dmi_write(), and riscv_batch_add_nop().

◆ riscv_fill_dmi_read_u64()

void riscv_fill_dmi_read_u64 ( struct target *  target,
char *  buf,
int  a 
)

Definition at line 3420 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_batch_add_dmi_read().

◆ riscv_fill_dmi_write_u64()

void riscv_fill_dmi_write_u64 ( struct target *  target,
char *  buf,
int  a,
uint64_t  d 
)

Definition at line 3414 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_batch_add_dmi_write().

◆ riscv_free_registers()

static void riscv_free_registers ( struct target *  target)
static

Definition at line 472 of file riscv.c.

References reg::arch_info, GDB_REGNO_COUNT, reg_cache::num_regs, target::reg_cache, reg_cache::reg_list, and reg::value.

Referenced by riscv_deinit_target(), and riscv_init_registers().

◆ riscv_get_gdb_arch()

static const char* riscv_get_gdb_arch ( const struct target *  target)
static

Definition at line 1745 of file riscv.c.

References LOG_ERROR, NULL, and riscv_xlen().

◆ riscv_get_gdb_reg_list()

static int riscv_get_gdb_reg_list ( struct target *  target,
struct reg **  reg_list[],
int *  reg_list_size,
enum target_register_class  reg_class 
)
static

Definition at line 1813 of file riscv.c.

References riscv_get_gdb_reg_list_internal().

◆ riscv_get_gdb_reg_list_internal()

static int riscv_get_gdb_reg_list_internal ( struct target *  target,
struct reg **  reg_list[],
int *  reg_list_size,
enum target_register_class  reg_class,
bool  read 
)
static

Definition at line 1757 of file riscv.c.

References ERROR_FAIL, ERROR_OK, reg::exist, reg_arch_type::get, LOG_DEBUG, LOG_ERROR, reg_cache::num_regs, target::reg_cache, REG_CLASS_ALL, REG_CLASS_GENERAL, reg_cache::reg_list, RISCV_INFO, riscv_select_current_hart(), reg::size, target_name(), reg::type, and reg::valid.

Referenced by riscv_get_gdb_reg_list(), and riscv_get_gdb_reg_list_noread().

◆ riscv_get_gdb_reg_list_noread()

static int riscv_get_gdb_reg_list_noread ( struct target *  target,
struct reg **  reg_list[],
int *  reg_list_size,
enum target_register_class  reg_class 
)
static

Definition at line 1805 of file riscv.c.

References riscv_get_gdb_reg_list_internal().

◆ riscv_get_register()

int riscv_get_register ( struct target *  target,
riscv_reg_t *  value,
enum gdb_regno  regid 
)

Get register, from the cache if it's in there.

Definition at line 3332 of file riscv.c.

References buf_get_u64(), ERROR_FAIL, ERROR_OK, reg::exist, gdb_regno_cacheable(), gdb_regno_name(), GDB_REGNO_XPR15, GDB_REGNO_XPR31, keep_alive(), LOG_DEBUG, target::reg_cache, reg_cache::reg_list, RISCV_INFO, riscv_supports_extension(), reg::size, target_name(), reg::valid, and reg::value.

Referenced by add_trigger(), disable_triggers(), enable_triggers(), maybe_add_trigger_t1(), maybe_add_trigger_t2(), maybe_add_trigger_t6(), register_get(), remove_trigger(), riscv_address_translate(), riscv_enumerate_triggers(), riscv_hit_watchpoint(), riscv_mmu(), riscv_program_exec(), and riscv_run_algorithm().

◆ riscv_halt()

int riscv_halt ( struct target *  target)

Definition at line 1224 of file riscv.c.

References target::coreid, ERROR_FAIL, ERROR_OK, foreach_smp_target, get_target_type(), target_type::halt, halt_finish(), halt_go(), halt_prep(), LOG_DEBUG, riscv_info::prepped, riscv_info(), RISCV_INFO, target::smp, target::smp_targets, and target_list::target.

Referenced by riscv013_step_or_resume_current_hart(), riscv_openocd_poll(), and riscv_run_algorithm().

◆ riscv_halt_go_all_harts()

static int riscv_halt_go_all_harts ( struct target *  target)
static

Definition at line 1184 of file riscv.c.

References ERROR_FAIL, ERROR_OK, LOG_DEBUG, RISCV_INFO, riscv_invalidate_register_cache(), riscv_is_halted(), riscv_select_current_hart(), and target_name().

Referenced by halt_go().

◆ riscv_halt_reason()

static enum riscv_halt_reason riscv_halt_reason ( struct target *  target,
int  hartid 
)
static

Definition at line 3370 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_openocd_poll().

◆ riscv_hit_watchpoint()

static int riscv_hit_watchpoint ( struct target *  target,
struct watchpoint **  hit_watchpoint 
)
static

Definition at line 1023 of file riscv.c.

References watchpoint::address, buffer, ERROR_FAIL, ERROR_OK, GDB_REGNO_DPC, length, LOG_DEBUG, LOG_ERROR, MATCH_LB, MATCH_SB, watchpoint::next, riscv_current_hartid(), riscv_get_register(), TARGET_PRIxADDR, target_read_buffer(), and target::watchpoints.

◆ riscv_info_init()

static void riscv_info_init ( struct target *  target,
struct riscv_info *  r 
)
static

Definition at line 3121 of file riscv.c.

References riscv_info::common_magic, target::coreid, riscv_info::current_hartid, riscv_info::dtm_version, riscv_info::expose_csr, riscv_info::expose_custom, INIT_LIST_HEAD(), riscv_info::mem_access_abstract_warn, riscv_info::mem_access_methods, riscv_info::mem_access_progbuf_warn, riscv_info::mem_access_sysbus_warn, NULL, RISCV_COMMON_MAGIC, RISCV_MEM_ACCESS_ABSTRACT, RISCV_MEM_ACCESS_PROGBUF, RISCV_MEM_ACCESS_SYSBUS, riscv_info::trigger_unique_id, riscv_info::version_specific, and riscv_info::xlen.

Referenced by riscv_create_target().

◆ riscv_init_registers()

int riscv_init_registers ( struct target *  target)

Definition at line 3788 of file riscv.c.

References reg::arch_info, ARRAY_SIZE, reg::caller_save, cmp_csr_info(), CSR_CYCLEH, CSR_FCSR, CSR_FFLAGS, CSR_FRM, CSR_HPMCOUNTER10H, CSR_HPMCOUNTER11H, CSR_HPMCOUNTER12H, CSR_HPMCOUNTER13H, CSR_HPMCOUNTER14H, CSR_HPMCOUNTER15H, CSR_HPMCOUNTER16H, CSR_HPMCOUNTER17H, CSR_HPMCOUNTER18H, CSR_HPMCOUNTER19H, CSR_HPMCOUNTER20H, CSR_HPMCOUNTER21H, CSR_HPMCOUNTER22H, CSR_HPMCOUNTER23H, CSR_HPMCOUNTER24H, CSR_HPMCOUNTER25H, CSR_HPMCOUNTER26H, CSR_HPMCOUNTER27H, CSR_HPMCOUNTER28H, CSR_HPMCOUNTER29H, CSR_HPMCOUNTER30H, CSR_HPMCOUNTER31H, CSR_HPMCOUNTER3H, CSR_HPMCOUNTER4H, CSR_HPMCOUNTER5H, CSR_HPMCOUNTER6H, CSR_HPMCOUNTER7H, CSR_HPMCOUNTER8H, CSR_HPMCOUNTER9H, CSR_INSTRETH, CSR_MCYCLEH, CSR_MEDELEG, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H, CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MIDELEG, CSR_MINSTRETH, CSR_PMPCFG1, CSR_PMPCFG3, CSR_SATP, CSR_SCAUSE, CSR_SCOUNTEREN, CSR_SEPC, CSR_SIE, CSR_SIP, CSR_SSCRATCH, CSR_SSTATUS, CSR_STVAL, CSR_STVEC, CSR_TIMEH, CSR_VL, CSR_VLENB, CSR_VSTART, CSR_VTYPE, CSR_VXRM, CSR_VXSAT, reg::dirty, DIV_ROUND_UP, ERROR_FAIL, ERROR_OK, reg::exist, reg::feature, reg_data_type_union::fields, GDB_REGNO_A0, GDB_REGNO_A1, GDB_REGNO_A2, GDB_REGNO_A3, GDB_REGNO_A4, GDB_REGNO_A5, GDB_REGNO_A6, GDB_REGNO_A7, GDB_REGNO_COUNT, GDB_REGNO_CSR0, GDB_REGNO_CSR4095, GDB_REGNO_FA0, GDB_REGNO_FA1, GDB_REGNO_FA2, GDB_REGNO_FA3, GDB_REGNO_FA4, GDB_REGNO_FA5, GDB_REGNO_FA6, GDB_REGNO_FA7, GDB_REGNO_FP, GDB_REGNO_FPR0, GDB_REGNO_FPR31, GDB_REGNO_FS0, GDB_REGNO_FS1, GDB_REGNO_FS10, GDB_REGNO_FS11, GDB_REGNO_FS2, GDB_REGNO_FS3, GDB_REGNO_FS4, GDB_REGNO_FS5, GDB_REGNO_FS6, GDB_REGNO_FS7, GDB_REGNO_FS8, GDB_REGNO_FS9, GDB_REGNO_FT0, GDB_REGNO_FT1, GDB_REGNO_FT10, GDB_REGNO_FT11, GDB_REGNO_FT2, GDB_REGNO_FT3, GDB_REGNO_FT4, GDB_REGNO_FT5, GDB_REGNO_FT6, GDB_REGNO_FT7, GDB_REGNO_FT8, GDB_REGNO_FT9, GDB_REGNO_GP, GDB_REGNO_PC, GDB_REGNO_PRIV, GDB_REGNO_RA, GDB_REGNO_S1, GDB_REGNO_S10, GDB_REGNO_S11, GDB_REGNO_S2, GDB_REGNO_S3, GDB_REGNO_S4, GDB_REGNO_S5, GDB_REGNO_S6, GDB_REGNO_S7, GDB_REGNO_S8, GDB_REGNO_S9, GDB_REGNO_SP, GDB_REGNO_T0, GDB_REGNO_T1, GDB_REGNO_T2, GDB_REGNO_T3, GDB_REGNO_T4, GDB_REGNO_T5, GDB_REGNO_T6, GDB_REGNO_TP, GDB_REGNO_V0, GDB_REGNO_V31, GDB_REGNO_XPR15, GDB_REGNO_XPR31, GDB_REGNO_ZERO, reg::group, range_list_t::high, info, list_empty(), list_first_entry, list_for_each_entry, list_rotate_left(), LOG_DEBUG, range_list_t::low, reg_feature::name, reg::name, reg_cache::name, csr_info::name, range_list_t::name, NULL, reg_cache::num_regs, number, reg::number, target::reg_cache, reg::reg_data_type, reg_cache::reg_list, REG_TYPE_ARCH_DEFINED, REG_TYPE_CLASS_UNION, REG_TYPE_CLASS_VECTOR, REG_TYPE_IEEE_DOUBLE, REG_TYPE_IEEE_SINGLE, REG_TYPE_UINT128, REG_TYPE_UINT16, REG_TYPE_UINT32, REG_TYPE_UINT64, REG_TYPE_UINT8, riscv_free_registers(), RISCV_INFO, riscv_reg_arch_type, riscv_supports_extension(), riscv_xlen(), reg::size, target, riscv_reg_info_t::target, reg_data_type::type, reg::type, reg::valid, and reg::value.

Referenced by examine(), and init_target().

◆ riscv_init_target()

static int riscv_init_target ( struct command_context *  cmd_ctx,
struct target *  target 
)
static

Definition at line 442 of file riscv.c.

References BSCAN_TUNNEL_DATA_REGISTER, bscan_tunnel_data_register_select_dmi, bscan_tunnel_ir_width, bscan_tunnel_nested_tap_select_dmi, bscan_tunnel_type, bscan_tunneled_ir_width, DBG_REASON_DBGRQ, target::debug_reason, ERROR_OK, h_u32_to_le(), info, jtag_tap::ir_length, ir_user4, LOG_DEBUG, scan_field::num_bits, RISCV_INFO, riscv_semihosting_init(), select_dbus, select_dtmcontrol, select_idcode, select_user4, and target::tap.

◆ riscv_invalidate_register_cache()

static void riscv_invalidate_register_cache ( struct target *  target)
static

Definition at line 3227 of file riscv.c.

References target::coreid, LOG_DEBUG, reg_cache::num_regs, target::reg_cache, reg_cache::reg_list, register_cache_invalidate(), and reg::valid.

Referenced by riscv_assert_reset(), riscv_halt_go_all_harts(), riscv_resume_go_all_harts(), and riscv_step_rtos_hart().

◆ riscv_is_halted()

bool riscv_is_halted ( struct target *  target)

Definition at line 3370 of file riscv.c.

Referenced by examine(), halt_prep(), register_write_direct(), riscv013_halt_go(), riscv013_step_or_resume_current_hart(), riscv_halt_go_all_harts(), riscv_resume_go_all_harts(), riscv_resume_prep_all_harts(), and riscv_step_rtos_hart().

◆ riscv_mmu()

static int riscv_mmu ( struct target *  target,
int *  enabled 
)
static

Definition at line 1523 of file riscv.c.

References ERROR_FAIL, ERROR_OK, GDB_REGNO_MSTATUS, GDB_REGNO_PRIV, GDB_REGNO_SATP, get_field, LOG_DEBUG, LOG_ERROR, MSTATUS_MPP, MSTATUS_MPRV, priv, PRV_M, riscv_enable_virt2phys, riscv_get_register(), RISCV_SATP_MODE, riscv_xlen(), and SATP_MODE_OFF.

Referenced by riscv_virt2phys().

◆ riscv_openocd_poll()

int riscv_openocd_poll ( struct target *  target)

Definition at line 2182 of file riscv.c.

References riscv_info::current_hartid, DBG_REASON_BREAKPOINT, DBG_REASON_NOTHALTED, target::debug_reason, ERROR_FAIL, ERROR_OK, foreach_smp_target, riscv_info::halt_reason, LOG_DEBUG, LOG_WARNING, riscv_current_hartid(), riscv_halt(), RISCV_HALT_BREAKPOINT, RISCV_HALT_GROUP, riscv_halt_reason(), riscv_info(), riscv_resume(), riscv_semihosting(), RPH_DISCOVERED_HALTED, RPH_DISCOVERED_RUNNING, RPH_ERROR, RPH_NO_CHANGE, sample_memory(), SEMIHOSTING_ERROR, SEMIHOSTING_HANDLED, SEMIHOSTING_NONE, SEMIHOSTING_WAITING, set_debug_reason(), target::smp, target::smp_targets, target::state, target_list::target, target_call_event_callbacks(), TARGET_EVENT_HALTED, TARGET_HALTED, and TARGET_RUNNING.

Referenced by old_or_new_riscv_poll().

◆ riscv_openocd_step()

int riscv_openocd_step ( struct target *  target,
bool  current,
target_addr_t  address,
bool  handle_breakpoints 
)

Definition at line 2301 of file riscv.c.

References address, DBG_REASON_SINGLESTEP, target::debug_reason, disable_triggers(), enable_triggers(), ERROR_FAIL, ERROR_OK, GDB_REGNO_PC, LOG_DEBUG, LOG_ERROR, target::reg_cache, register_cache_invalidate(), RISCV_MAX_HWBPS, riscv_set_register(), riscv_step_rtos_hart(), target::state, target_call_event_callbacks(), TARGET_EVENT_HALTED, TARGET_EVENT_RESUMED, TARGET_HALTED, and TARGET_RUNNING.

Referenced by old_or_new_riscv_step().

◆ riscv_poll_hart()

static enum riscv_poll_hart riscv_poll_hart ( struct target *  target,
int  hartid 
)
static

Definition at line 1989 of file riscv.c.

◆ riscv_read_by_any_size()

int riscv_read_by_any_size ( struct target *  target,
target_addr_t  address,
uint32_t  size,
uint8_t *  buffer 
)

Read one memory item using any memory access size that will work.

Read larger section of memory and pick out the required portion, if needed.

Definition at line 837 of file riscv.c.

References address, buffer, ERROR_FAIL, ERROR_OK, read_by_given_size(), and size.

Referenced by riscv_add_breakpoint().

◆ riscv_read_debug_buffer()

riscv_insn_t riscv_read_debug_buffer ( struct target *  target,
int  index 
)

Definition at line 3402 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_program_exec().

◆ riscv_read_memory()

static int riscv_read_memory ( struct target *  target,
target_addr_t  address,
uint32_t  size,
uint32_t  count,
uint8_t *  buffer 
)
static

Definition at line 1698 of file riscv.c.

References address, buffer, count, ERROR_FAIL, ERROR_OK, LOG_WARNING, RISCV_INFO, riscv_select_current_hart(), size, TARGET_PRIxADDR, target::type, and target_type::virt2phys.

◆ riscv_read_phys_memory()

static int riscv_read_phys_memory ( struct target *  target,
target_addr_t  phys_address,
uint32_t  size,
uint32_t  count,
uint8_t *  buffer 
)
static

Definition at line 1689 of file riscv.c.

References buffer, count, ERROR_FAIL, ERROR_OK, RISCV_INFO, riscv_select_current_hart(), and size.

Referenced by sample_memory().

◆ riscv_remove_breakpoint()

static int riscv_remove_breakpoint ( struct target *  target,
struct breakpoint *  breakpoint 
)
static

Definition at line 945 of file riscv.c.

References breakpoint::address, BKPT_HARD, BKPT_SOFT, ERROR_FAIL, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, breakpoint::is_set, breakpoint::length, LOG_ERROR, LOG_INFO, breakpoint::orig_instr, remove_trigger(), riscv_write_by_any_size(), TARGET_PRIxADDR, trigger_from_breakpoint(), and breakpoint::type.

◆ riscv_remove_watchpoint()

int riscv_remove_watchpoint ( struct target *  target,
struct watchpoint *  watchpoint 
)

Definition at line 1001 of file riscv.c.

References watchpoint::address, target::coreid, ERROR_OK, watchpoint::is_set, LOG_DEBUG, remove_trigger(), TARGET_PRIxADDR, and trigger_from_watchpoint().

Referenced by disable_triggers(), and strict_step().

◆ riscv_resume()

static int riscv_resume ( struct target *  target,
bool  current,
target_addr_t  address,
bool  handle_breakpoints,
bool  debug_execution,
bool  single_hart 
)
static
single_hart When true, only resume a single hart even if SMP is
configured. This is used to run algorithms on just one hart.

Definition at line 1464 of file riscv.c.

References address, ERROR_FAIL, ERROR_OK, foreach_smp_target_direction, LOG_DEBUG, riscv_info::prepped, resume_finish(), resume_go(), resume_order, resume_prep(), riscv_info(), RO_NORMAL, target::smp, target::smp_targets, and target_list::target.

Referenced by riscv_openocd_poll(), riscv_run_algorithm(), and riscv_target_resume().

◆ riscv_resume_go_all_harts()

static int riscv_resume_go_all_harts ( struct target *  target)
static

Definition at line 3147 of file riscv.c.

References ERROR_FAIL, ERROR_OK, LOG_DEBUG, RISCV_INFO, riscv_invalidate_register_cache(), riscv_is_halted(), riscv_select_current_hart(), and target_name().

Referenced by resume_go().

◆ riscv_resume_prep_all_harts()

static int riscv_resume_prep_all_harts ( struct target *  target)
static

Definition at line 1286 of file riscv.c.

References ERROR_FAIL, ERROR_OK, LOG_DEBUG, RISCV_INFO, riscv_is_halted(), riscv_select_current_hart(), and target_name().

Referenced by resume_prep().

◆ riscv_run_algorithm()

static int riscv_run_algorithm ( struct target *  target,
int  num_mem_params,
struct mem_param *  mem_params,
int  num_reg_params,
struct reg_param *  reg_params,
target_addr_t  entry_point,
target_addr_t  exit_point,
unsigned int  timeout_ms,
void *  arch_info 
)
static

Definition at line 1828 of file riscv.c.

References ARRAY_SIZE, buf_cpy(), buf_get_u64(), buf_set_u64(), direction, ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_HALTED, ERROR_TARGET_TIMEOUT, GDB_REGNO_A0, GDB_REGNO_A1, GDB_REGNO_A2, GDB_REGNO_A3, GDB_REGNO_A4, GDB_REGNO_A5, GDB_REGNO_A6, GDB_REGNO_A7, GDB_REGNO_FP, GDB_REGNO_GP, GDB_REGNO_MCAUSE, GDB_REGNO_MEPC, GDB_REGNO_MSTATUS, gdb_regno_name(), GDB_REGNO_PC, GDB_REGNO_RA, GDB_REGNO_S1, GDB_REGNO_S10, GDB_REGNO_S11, GDB_REGNO_S2, GDB_REGNO_S3, GDB_REGNO_S4, GDB_REGNO_S5, GDB_REGNO_S6, GDB_REGNO_S7, GDB_REGNO_S8, GDB_REGNO_S9, GDB_REGNO_SP, GDB_REGNO_T0, GDB_REGNO_T1, GDB_REGNO_T2, GDB_REGNO_T3, GDB_REGNO_T4, GDB_REGNO_T5, GDB_REGNO_T6, GDB_REGNO_TP, GDB_REGNO_XPR31, reg_arch_type::get, info, LOG_DEBUG, LOG_ERROR, LOG_TARGET_ERROR, MSTATUS_HIE, MSTATUS_MIE, MSTATUS_SIE, MSTATUS_UIE, reg::name, reg::number, old_or_new_riscv_poll(), PARAM_IN, PARAM_IN_OUT, PARAM_OUT, target::reg_cache, reg_param::reg_name, register_get_by_name(), riscv_get_register(), riscv_halt(), RISCV_INFO, riscv_resume(), riscv_select_current_hart(), reg_arch_type::set, set_field, reg_param::size, reg::size, start, target::state, TARGET_HALTED, TARGET_PRIxADDR, timeval_ms(), reg::type, reg_param::value, and reg::value.

◆ riscv_sample_buf_maybe_add_timestamp()

static void riscv_sample_buf_maybe_add_timestamp ( struct target *  target,
bool  before 
)
static

Definition at line 264 of file riscv.c.

References RISCV_INFO, RISCV_SAMPLE_BUF_TIMESTAMP_AFTER, RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE, and timeval_ms().

Referenced by sample_memory().

◆ riscv_select_current_hart()

int riscv_select_current_hart ( struct target *  target)

Definition at line 1159 of file riscv.c.

References target::coreid, and riscv_set_current_hartid().

Referenced by halt_prep(), riscv013_get_register(), riscv013_get_register_buf(), riscv013_set_register_buf(), riscv_get_gdb_reg_list_internal(), riscv_halt_go_all_harts(), riscv_read_memory(), riscv_read_phys_memory(), riscv_resume_go_all_harts(), riscv_resume_prep_all_harts(), riscv_run_algorithm(), riscv_step_rtos_hart(), riscv_write_memory(), and riscv_write_phys_memory().

◆ riscv_set_current_hartid()

int riscv_set_current_hartid ( struct target *  target,
int  hartid 
)

Definition at line 3211 of file riscv.c.

References ERROR_FAIL, ERROR_OK, LOG_DEBUG, riscv_current_hartid(), and RISCV_INFO.

Referenced by examine(), and riscv_select_current_hart().

◆ riscv_set_register()

int riscv_set_register ( struct target *  target,
enum gdb_regno  regid,
riscv_reg_t  value 
)

This function is called when the debug user wants to change the value of a register.

Set register, updating the cache.

The new value may be cached, and may not be written until the hart is resumed.

Definition at line 3306 of file riscv.c.

References buf_set_u64(), ERROR_OK, gdb_regno_cacheable(), gdb_regno_name(), GDB_REGNO_XPR15, GDB_REGNO_XPR31, keep_alive(), LOG_DEBUG, reg::name, target::reg_cache, reg_cache::reg_list, RISCV_INFO, riscv_supports_extension(), reg::size, target_name(), reg::valid, and reg::value.

Referenced by add_trigger(), disable_triggers(), enable_triggers(), maybe_add_trigger_t1(), maybe_add_trigger_t2(), maybe_add_trigger_t6(), read_memory_progbuf(), read_memory_progbuf_one(), register_set(), remove_trigger(), resume_prep(), riscv013_on_step_or_resume(), riscv_enumerate_triggers(), riscv_openocd_step(), riscv_program_exec(), and riscv_semihosting_post_result().

◆ riscv_step_rtos_hart()

static int riscv_step_rtos_hart ( struct target *  target)
static

Definition at line 3168 of file riscv.c.

References ERROR_FAIL, ERROR_OK, LOG_DEBUG, LOG_ERROR, RISCV_INFO, riscv_invalidate_register_cache(), riscv_is_halted(), riscv_select_current_hart(), and target_name().

Referenced by riscv_openocd_step().

◆ riscv_supports_extension()

bool riscv_supports_extension ( struct target *  target,
char  letter 
)

Definition at line 3192 of file riscv.c.

References BIT, and RISCV_INFO.

Referenced by examine(), register_read_direct(), register_write_direct(), riscv_get_register(), riscv_init_registers(), and riscv_set_register().

◆ riscv_target_resume()

static int riscv_target_resume ( struct target *  target,
bool  current,
target_addr_t  address,
bool  handle_breakpoints,
bool  debug_execution 
)
static

Definition at line 1516 of file riscv.c.

References address, and riscv_resume().

◆ riscv_virt2phys()

static int riscv_virt2phys ( struct target *  target,
target_addr_t  virtual,
target_addr_t *  physical 
)
static

Definition at line 1675 of file riscv.c.

References ERROR_FAIL, ERROR_OK, riscv_address_translate(), and riscv_mmu().

◆ riscv_write_by_any_size()

int riscv_write_by_any_size ( struct target *  target,
target_addr_t  address,
uint32_t  size,
uint8_t *  buffer 
)

Write one memory item using any memory access size that will work.

Utilize read-modify-write, if needed.

Definition at line 805 of file riscv.c.

References address, buffer, ERROR_FAIL, ERROR_OK, size, and write_by_given_size().

Referenced by riscv_add_breakpoint(), and riscv_remove_breakpoint().

◆ riscv_write_debug_buffer()

int riscv_write_debug_buffer ( struct target *  target,
int  index,
riscv_insn_t  insn 
)

Definition at line 3395 of file riscv.c.

References ERROR_OK, and RISCV_INFO.

Referenced by riscv_program_write().

◆ riscv_write_memory()

static int riscv_write_memory ( struct target *  target,
target_addr_t  address,
uint32_t  size,
uint32_t  count,
const uint8_t *  buffer 
)
static

Definition at line 1726 of file riscv.c.

References address, buffer, count, ERROR_FAIL, ERROR_OK, get_target_type(), LOG_WARNING, riscv_select_current_hart(), size, TARGET_PRIxADDR, target::type, target_type::virt2phys, and target_type::write_memory.

◆ riscv_write_phys_memory()

static int riscv_write_phys_memory ( struct target *  target,
target_addr_t  phys_address,
uint32_t  size,
uint32_t  count,
const uint8_t *  buffer 
)
static

Definition at line 1717 of file riscv.c.

References buffer, count, ERROR_FAIL, ERROR_OK, get_target_type(), riscv_select_current_hart(), size, and target_type::write_memory.

◆ riscv_xlen()

unsigned int riscv_xlen ( const struct target *  target)

Definition at line 3205 of file riscv.c.

References RISCV_INFO.

Referenced by add_trigger(), cache_get(), cache_set(), COMMAND_HANDLER(), disable_triggers(), examine(), execute_resume(), fespi_write(), get_register(), handle_halt_routine(), load(), maybe_add_trigger_t2(), maybe_add_trigger_t6(), mem_should_skip_abstract(), mem_should_skip_progbuf(), prep_for_vector_access(), read_memory_abstract(), read_memory_progbuf(), read_memory_progbuf_inner(), read_memory_progbuf_one(), register_read_direct(), register_size(), register_write(), register_write_direct(), riscv013_data_bits(), riscv013_get_register_buf(), riscv013_set_register_buf(), riscv_address_translate(), riscv_checksum_memory(), riscv_data_bits(), riscv_enumerate_triggers(), riscv_get_gdb_arch(), riscv_init_registers(), riscv_mmu(), riscv_program_init(), riscv_xlen_nonconst(), scans_add_read(), scans_new(), slot_offset(), step(), store(), write_memory_abstract(), and write_memory_progbuf().

◆ riscv_xlen_nonconst()

static unsigned int riscv_xlen_nonconst ( struct target *  target)
static

Definition at line 3056 of file riscv.c.

References riscv_xlen().

◆ sample_memory()

static int sample_memory ( struct target *  target)
static

Definition at line 2134 of file riscv.c.

References ARRAY_SIZE, ERROR_NOT_IMPLEMENTED, ERROR_OK, LOG_DEBUG, LOG_INFO, RISCV_INFO, riscv_read_phys_memory(), riscv_sample_buf_maybe_add_timestamp(), RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE, start, TARGET_DEFAULT_POLLING_INTERVAL, and timeval_ms().

Referenced by riscv_openocd_poll().

◆ select_dmi_via_bscan()

void select_dmi_via_bscan ( struct target *  target)

Definition at line 282 of file riscv.c.

References BSCAN_TUNNEL_DATA_REGISTER, bscan_tunnel_data_register_select_dmi, bscan_tunnel_data_register_select_dmi_num_fields, bscan_tunnel_nested_tap_select_dmi, bscan_tunnel_nested_tap_select_dmi_num_fields, bscan_tunnel_type, jtag_add_dr_scan(), jtag_add_ir_scan(), select_user4, target::tap, and TAP_IDLE.

Referenced by dtmcontrol_scan_via_bscan(), and select_dmi().

◆ set_debug_reason()

static int set_debug_reason ( struct target *  target,
enum riscv_halt_reason  halt_reason 
)
static

Definition at line 2108 of file riscv.c.

References DBG_REASON_BREAKPOINT, DBG_REASON_DBGRQ, DBG_REASON_SINGLESTEP, DBG_REASON_UNDEFINED, DBG_REASON_WATCHPOINT, target::debug_reason, ERROR_FAIL, ERROR_OK, LOG_DEBUG, RISCV_HALT_BREAKPOINT, RISCV_HALT_ERROR, RISCV_HALT_GROUP, RISCV_HALT_INTERRUPT, RISCV_HALT_SINGLESTEP, RISCV_HALT_TRIGGER, RISCV_HALT_UNKNOWN, and target_name().

Referenced by riscv_openocd_poll().

◆ trigger_from_breakpoint()

static void trigger_from_breakpoint ( struct trigger *  trigger,
const struct breakpoint *  breakpoint 
)
static

Definition at line 521 of file riscv.c.

References breakpoint::address, trigger::address, trigger::execute, breakpoint::length, trigger::length, trigger::mask, trigger::read, breakpoint::unique_id, trigger::unique_id, and trigger::write.

Referenced by riscv_add_breakpoint(), and riscv_remove_breakpoint().

◆ trigger_from_watchpoint()

static void trigger_from_watchpoint ( struct trigger *  trigger,
const struct watchpoint *  watchpoint 
)
static

Definition at line 974 of file riscv.c.

References watchpoint::address, trigger::address, trigger::execute, watchpoint::length, trigger::length, watchpoint::mask, trigger::mask, trigger::read, watchpoint::rw, watchpoint::unique_id, trigger::unique_id, watchpoint::value, trigger::value, WPT_ACCESS, WPT_READ, WPT_WRITE, and trigger::write.

Referenced by riscv_add_watchpoint(), and riscv_remove_watchpoint().

◆ write_by_given_size()

static int write_by_given_size ( struct target *  target,
target_addr_t  address,
uint32_t  size,
uint8_t *  buffer,
uint32_t  access_size 
)
static

Write one memory item of given "size".

Use memory access of given "access_size". Utilize read-modify-write, if needed.

Definition at line 751 of file riscv.c.

References address, buffer, ERROR_FAIL, ERROR_OK, size, target_read_memory(), and target_write_memory().

Referenced by riscv_write_by_any_size().

Variable Documentation

◆ _bscan_tunnel_data_register_select_dmi

struct scan_field _bscan_tunnel_data_register_select_dmi[]
static
Initial value:
= {
{
.num_bits = 3,
.out_value = bscan_zero,
.in_value = NULL,
},
{
.num_bits = 5,
.out_value = ir_dbus,
.in_value = NULL,
},
{
.num_bits = 7,
.out_value = bscan_tunneled_ir_width,
.in_value = NULL,
},
{
.num_bits = 1,
.out_value = bscan_zero,
.in_value = NULL,
}
}
bscan_tunneled_ir_width
static uint8_t bscan_tunneled_ir_width[4]
Definition: riscv.c:141
ir_dbus
static uint8_t ir_dbus[4]
Definition: riscv.c:117
bscan_zero
static const uint8_t bscan_zero[4]
Definition: riscv.c:131
NULL
#define NULL
Definition: usb.h:16

Definition at line 141 of file riscv.c.

◆ _bscan_tunnel_nested_tap_select_dmi

struct scan_field _bscan_tunnel_nested_tap_select_dmi[]
static
Initial value:
= {
{
.num_bits = 1,
.out_value = bscan_zero,
.in_value = NULL,
},
{
.num_bits = 7,
.out_value = bscan_tunneled_ir_width,
.in_value = NULL,
},
{
.num_bits = 0,
.out_value = ir_dbus,
.in_value = NULL,
},
{
.num_bits = 3,
.out_value = bscan_zero,
.in_value = NULL,
}
}

Definition at line 141 of file riscv.c.

◆ bscan_one

const uint8_t bscan_one[4] = {1}
static

Definition at line 132 of file riscv.c.

Referenced by dtmcontrol_scan_via_bscan(), and riscv_add_bscan_tunneled_scan().

◆ bscan_tunnel_data_register_select_dmi

struct scan_field* bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi
static

Definition at line 190 of file riscv.c.

Referenced by riscv_init_target(), and select_dmi_via_bscan().

◆ bscan_tunnel_data_register_select_dmi_num_fields

uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi)
static

Definition at line 191 of file riscv.c.

Referenced by select_dmi_via_bscan().

◆ bscan_tunnel_ir_width

int bscan_tunnel_ir_width

Definition at line 129 of file riscv.c.

Referenced by COMMAND_HANDLER(), dmi_scan(), dtmcontrol_scan(), dtmcontrol_scan_via_bscan(), riscv_batch_alloc(), riscv_batch_run(), riscv_init_target(), and select_dmi().

◆ bscan_tunnel_nested_tap_select_dmi

struct scan_field* bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi
static

Definition at line 187 of file riscv.c.

Referenced by riscv_init_target(), and select_dmi_via_bscan().

◆ bscan_tunnel_nested_tap_select_dmi_num_fields

uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi)
static

Definition at line 188 of file riscv.c.

Referenced by select_dmi_via_bscan().

◆ bscan_tunnel_type

bscan_tunnel_type_t bscan_tunnel_type
static

Definition at line 128 of file riscv.c.

Referenced by COMMAND_HANDLER(), dtmcontrol_scan_via_bscan(), riscv_add_bscan_tunneled_scan(), riscv_init_target(), and select_dmi_via_bscan().

◆ bscan_tunneled_ir_width

uint8_t bscan_tunneled_ir_width[4] = {5}
static

Definition at line 141 of file riscv.c.

Referenced by riscv_init_target().

◆ bscan_zero

const uint8_t bscan_zero[4] = {0}
static

Definition at line 131 of file riscv.c.

Referenced by dtmcontrol_scan_via_bscan(), and riscv_add_bscan_tunneled_scan().

◆ ir_dbus

uint8_t ir_dbus[4] = {DBUS}
static

Definition at line 117 of file riscv.c.

Referenced by COMMAND_HANDLER().

◆ ir_dtmcontrol

uint8_t ir_dtmcontrol[4] = {DTMCONTROL}
static

Definition at line 112 of file riscv.c.

Referenced by COMMAND_HANDLER(), and dtmcontrol_scan_via_bscan().

◆ ir_idcode

uint8_t ir_idcode[4] = {0x1}
static

Definition at line 122 of file riscv.c.

Referenced by COMMAND_HANDLER().

◆ ir_user4

uint8_t ir_user4[4]
static

Definition at line 134 of file riscv.c.

Referenced by riscv_init_target().

◆ 

enum { ... } resume_order

Referenced by COMMAND_HANDLER(), and riscv_resume().

◆ riscv_command_handlers

const struct command_registration riscv_command_handlers[]
static
Initial value:
= {
{
.name = "riscv",
.mode = COMMAND_ANY,
.help = "RISC-V Command Group",
.usage = "",
.chain = riscv_exec_command_handlers
},
{
.name = "arm",
.mode = COMMAND_ANY,
.help = "ARM Command Group",
.usage = "",
.chain = semihosting_common_handlers
},
{
.chain = smp_command_handlers
},
COMMAND_REGISTRATION_DONE
}
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
riscv_exec_command_handlers
static const struct command_registration riscv_exec_command_handlers[]
Definition: riscv.c:2862
semihosting_common_handlers
const struct command_registration semihosting_common_handlers[]
Definition: semihosting_common.c:2119
smp_command_handlers
const struct command_registration smp_command_handlers[]
Definition: smp.c:153
command_registration::name
const char * name
Definition: command.h:235
command_registration::chain
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
Definition: command.h:249

Definition at line 2844 of file riscv.c.

◆ riscv_command_timeout_sec

int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC

Definition at line 203 of file riscv.c.

Referenced by COMMAND_HANDLER(), dmi_op(), dmstatus_read(), full_step(), read_sbcs_nonbusy(), riscv013_clear_abstract_error(), wait_for_authbusy(), wait_for_debugint_clear(), wait_for_idle(), wait_for_state(), and write_memory_bus_v1().

◆ riscv_ebreakm

bool riscv_ebreakm = true

Definition at line 209 of file riscv.c.

Referenced by assert_reset(), COMMAND_HANDLER(), execute_resume(), and riscv013_on_step_or_resume().

◆ riscv_ebreaks

bool riscv_ebreaks = true

Definition at line 210 of file riscv.c.

Referenced by assert_reset(), COMMAND_HANDLER(), execute_resume(), and riscv013_on_step_or_resume().

◆ riscv_ebreaku

bool riscv_ebreaku = true

Definition at line 211 of file riscv.c.

Referenced by assert_reset(), COMMAND_HANDLER(), execute_resume(), and riscv013_on_step_or_resume().

◆ riscv_enable_virt2phys

bool riscv_enable_virt2phys = true
static

Definition at line 208 of file riscv.c.

Referenced by COMMAND_HANDLER(), and riscv_mmu().

◆ riscv_enable_virtual

bool riscv_enable_virtual

Definition at line 213 of file riscv.c.

Referenced by COMMAND_HANDLER(), examine(), modify_privilege(), read_memory_progbuf(), read_memory_progbuf_one(), and write_memory_progbuf().

◆ riscv_exec_command_handlers

const struct command_registration riscv_exec_command_handlers[]
static

Definition at line 2844 of file riscv.c.

◆ riscv_reg_arch_type

struct reg_arch_type riscv_reg_arch_type
static
Initial value:
= {
.get = register_get,
.set = register_set
}
register_set
static int register_set(struct reg *reg, uint8_t *buf)
Definition: riscv.c:3725
register_get
static int register_get(struct reg *reg)
Definition: riscv.c:3695

Definition at line 3725 of file riscv.c.

Referenced by riscv_init_registers().

◆ riscv_reset_timeout_sec

int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC

Definition at line 206 of file riscv.c.

Referenced by COMMAND_HANDLER(), and deassert_reset().

◆ riscv_target

struct target_type riscv_target

Definition at line 3061 of file riscv.c.

◆ select_dbus

struct scan_field select_dbus
Initial value:
= {
.in_value = NULL,
.out_value = ir_dbus
}

Definition at line 117 of file riscv.c.

Referenced by assert_reset(), deassert_reset(), dtmcontrol_scan(), halt(), idcode_scan(), poll_target(), read_memory(), riscv011_resume(), riscv_init_target(), select_dmi(), step(), and write_memory().

◆ select_dtmcontrol

struct scan_field select_dtmcontrol
Initial value:
= {
.in_value = NULL,
.out_value = ir_dtmcontrol
}
ir_dtmcontrol
static uint8_t ir_dtmcontrol[4]
Definition: riscv.c:112

Definition at line 112 of file riscv.c.

Referenced by dtmcontrol_scan(), and riscv_init_target().

◆ select_idcode

struct scan_field select_idcode
Initial value:
= {
.in_value = NULL,
.out_value = ir_idcode
}
ir_idcode
static uint8_t ir_idcode[4]
Definition: riscv.c:122

Definition at line 122 of file riscv.c.

Referenced by idcode_scan(), and riscv_init_target().

◆ select_user4

struct scan_field select_user4
static
Initial value:
= {
.in_value = NULL,
.out_value = ir_user4
}
ir_user4
static uint8_t ir_user4[4]
Definition: riscv.c:134

Definition at line 134 of file riscv.c.

Referenced by dtmcontrol_scan_via_bscan(), riscv_add_bscan_tunneled_scan(), riscv_init_target(), and select_dmi_via_bscan().

◆ sv32

const virt2phys_info_t sv32
static
Initial value:
= {
.name = "Sv32",
.va_bits = 32,
.level = 2,
.pte_shift = 2,
.vpn_shift = {12, 22},
.vpn_mask = {0x3ff, 0x3ff},
.pte_ppn_shift = {10, 20},
.pte_ppn_mask = {0x3ff, 0xfff},
.pa_ppn_shift = {12, 22},
.pa_ppn_mask = {0x3ff, 0xfff},
}

Definition at line 220 of file riscv.c.

Referenced by riscv_address_translate().

◆ sv39

const virt2phys_info_t sv39
static
Initial value:
= {
.name = "Sv39",
.va_bits = 39,
.level = 3,
.pte_shift = 3,
.vpn_shift = {12, 21, 30},
.vpn_mask = {0x1ff, 0x1ff, 0x1ff},
.pte_ppn_shift = {10, 19, 28},
.pte_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
.pa_ppn_shift = {12, 21, 30},
.pa_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
}

Definition at line 233 of file riscv.c.

Referenced by riscv_address_translate().

◆ sv48

const virt2phys_info_t sv48
static
Initial value:
= {
.name = "Sv48",
.va_bits = 48,
.level = 4,
.pte_shift = 3,
.vpn_shift = {12, 21, 30, 39},
.vpn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ff},
.pte_ppn_shift = {10, 19, 28, 37},
.pte_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
.pa_ppn_shift = {12, 21, 30, 39},
.pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
}

Definition at line 246 of file riscv.c.

Referenced by riscv_address_translate().