Include dependency graph for riscv.h:

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Data Structures
struct	range_list_t

struct	reg_name_table

struct	riscv_bscan_tunneled_scan_context_t

struct	riscv_info

struct	riscv_mem_access_args

struct	riscv_private_config

struct	riscv_reg_info_t

struct	riscv_sample_buf

struct	riscv_sample_config_t

struct	virt2phys_info_t

Macros
#define	DEFAULT_COMMAND_TIMEOUT_SEC 5

#define	DTM_DTMCS_VERSION_UNKNOWN ((unsigned int)-1)

#define	PG_MAX_LEVEL 5

#define	RISCV013_DTMCS_ABITS_MAX 32

#define	RISCV013_DTMCS_ABITS_MIN 7

#define	RISCV_BATCH_ALLOC_SIZE 128

#define	RISCV_COMMON_MAGIC 0x52495356U

#define	RISCV_HGATP_MODE(xlen) ((xlen) == 32 ? HGATP32_MODE : HGATP64_MODE)

#define	RISCV_HGATP_PPN(xlen) ((xlen) == 32 ? HGATP32_PPN : HGATP64_PPN)

#define	RISCV_INFO(R) struct riscv_info *R = riscv_info(target);

#define	RISCV_MAX_DMS 100

#define	RISCV_MAX_TRIGGERS 32

#define	RISCV_PGBASE(addr) ((addr) & ~(RISCV_PGSIZE - 1))

#define	RISCV_PGOFFSET(addr) ((addr) & (RISCV_PGSIZE - 1))

#define	RISCV_PGSHIFT 12

#define	RISCV_PGSIZE BIT(RISCV_PGSHIFT)

#define	RISCV_SAMPLE_BUF_TIMESTAMP_AFTER 0x81

#define	RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE 0x80

#define	RISCV_SATP_MODE(xlen) ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)

#define	RISCV_SATP_PPN(xlen) ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)

#define	RISCV_TINFO_VERSION_UNKNOWN (-1)

Typedefs
typedef uint64_t	riscv_addr_t

typedef uint32_t	riscv_insn_t

typedef uint64_t	riscv_reg_t

Enumerations
enum	bscan_tunnel_type_t { BSCAN_TUNNEL_NESTED_TAP , BSCAN_TUNNEL_DATA_REGISTER }

enum	riscv_halt_reason { RISCV_HALT_INTERRUPT , RISCV_HALT_EBREAK , RISCV_HALT_SINGLESTEP , RISCV_HALT_TRIGGER , RISCV_HALT_UNKNOWN , RISCV_HALT_GROUP , RISCV_HALT_CRITICAL_ERROR , RISCV_HALT_ERROR }

enum	riscv_hart_state { RISCV_STATE_NON_EXISTENT , RISCV_STATE_RUNNING , RISCV_STATE_HALTED , RISCV_STATE_UNAVAILABLE }

enum	riscv_isrmasking_mode { RISCV_ISRMASK_OFF , RISCV_ISRMASK_STEPONLY }

enum	riscv_mem_access_method { RISCV_MEM_ACCESS_PROGBUF , RISCV_MEM_ACCESS_SYSBUS , RISCV_MEM_ACCESS_ABSTRACT , RISCV_MEM_ACCESS_MAX_METHODS_NUM }

enum	riscv_priv_mode { RISCV_MODE_M , RISCV_MODE_S , RISCV_MODE_U , RISCV_MODE_VS , RISCV_MODE_VU , N_RISCV_MODE }

enum	riscv_virt2phys_mode { RISCV_VIRT2PHYS_MODE_HW , RISCV_VIRT2PHYS_MODE_SW , RISCV_VIRT2PHYS_MODE_OFF }

enum	yes_no_maybe { YNM_MAYBE , YNM_YES , YNM_NO }

Functions
	COMMAND_HELPER (riscv_print_info_line, const char section, const char key, unsigned int value)

int	dtmcs_scan (struct jtag_tap tap, uint32_t out, uint32_t in_ptr)

static bool	is_riscv (const struct riscv_info *riscv_info)

void	riscv_add_bscan_tunneled_scan (struct jtag_tap tap, const struct scan_field field, riscv_bscan_tunneled_scan_context_t *ctxt)

int	riscv_add_watchpoint (struct target target, struct watchpoint watchpoint)

int	riscv_enumerate_triggers (struct target *target)
	Count triggers, and initialize trigger_count for each hart. More...

int	riscv_execute_progbuf (struct target target, uint32_t cmderr)

void	riscv_fill_dm_nop (const struct target target, uint8_t buf)

void	riscv_fill_dmi_read (const struct target target, uint8_t buf, uint32_t a)

void	riscv_fill_dmi_write (const struct target target, uint8_t buf, uint32_t a, uint32_t d)

int	riscv_get_command_timeout_sec (void)

uint32_t	riscv_get_dmi_address (const struct target *target, uint32_t dm_address)

unsigned int	riscv_get_dmi_address_bits (const struct target *target)

int	riscv_get_hart_state (struct target target, enum riscv_hart_state state)

int	riscv_halt (struct target *target)

static struct riscv_info *	riscv_info (const struct target *target) __attribute__((unused))

static bool	riscv_mem_access_is_read (const struct riscv_mem_access_args args)

static bool	riscv_mem_access_is_valid (const struct riscv_mem_access_args args)

static bool	riscv_mem_access_is_write (const struct riscv_mem_access_args args)

int	riscv_openocd_poll (struct target *target)

int	riscv_openocd_step (struct target *target, bool current, target_addr_t address, bool handle_breakpoints)

static riscv_reg_t	riscv_priv_mode_to_prv (enum riscv_priv_mode mode)

static struct riscv_private_config *	riscv_private_config (const struct target *target)

unsigned int	riscv_progbuf_size (struct target *target)

int	riscv_read_by_any_size (struct target target, target_addr_t address, uint32_t size, uint8_t buffer)
	Read one memory item using any memory access size that will work. More...

riscv_insn_t	riscv_read_progbuf (struct target *target, int index)

int	riscv_remove_watchpoint (struct target target, struct watchpoint watchpoint)

enum semihosting_result	riscv_semihosting (struct target target, int retval)
	Check for and process a semihosting request using the ARM protocol). More...

void	riscv_semihosting_init (struct target *target)
	Initialize RISC-V semihosting. More...

bool	riscv_supports_extension (const struct target *target, char letter)

const char *	riscv_virt2phys_mode_to_str (enum riscv_virt2phys_mode mode)

unsigned int	riscv_vlenb (const struct target *target)

int	riscv_write_by_any_size (struct target target, target_addr_t address, uint32_t size, uint8_t buffer)
	Write one memory item using any memory access size that will work. More...

int	riscv_write_progbuf (struct target *target, unsigned int index, riscv_insn_t insn)

unsigned int	riscv_xlen (const struct target *target)

void	select_dmi_via_bscan (struct jtag_tap *tap)

Variables
uint8_t	bscan_tunnel_ir_width

struct scan_field *	bscan_tunneled_select_dmi

uint32_t	bscan_tunneled_select_dmi_num_fields

struct target_type	riscv011_target

struct target_type	riscv013_target

struct scan_field	select_dbus

struct scan_field	select_dtmcontrol

struct scan_field	select_idcode

Macro Definition Documentation

◆ DEFAULT_COMMAND_TIMEOUT_SEC

#define DEFAULT_COMMAND_TIMEOUT_SEC 5

Definition at line 23 of file riscv.h.

◆ DTM_DTMCS_VERSION_UNKNOWN

#define DTM_DTMCS_VERSION_UNKNOWN ((unsigned int)-1)

Definition at line 124 of file riscv.h.

◆ PG_MAX_LEVEL

#define PG_MAX_LEVEL 5

Definition at line 34 of file riscv.h.

◆ RISCV013_DTMCS_ABITS_MAX

#define RISCV013_DTMCS_ABITS_MAX 32

Definition at line 128 of file riscv.h.

◆ RISCV013_DTMCS_ABITS_MIN

#define RISCV013_DTMCS_ABITS_MIN 7

Definition at line 127 of file riscv.h.

◆ RISCV_BATCH_ALLOC_SIZE

#define RISCV_BATCH_ALLOC_SIZE 128

Definition at line 36 of file riscv.h.

◆ RISCV_COMMON_MAGIC

#define RISCV_COMMON_MAGIC 0x52495356U

Definition at line 18 of file riscv.h.

◆ RISCV_HGATP_MODE

#define RISCV_HGATP_MODE ( xlen ) ((xlen) == 32 ? HGATP32_MODE : HGATP64_MODE)

Definition at line 27 of file riscv.h.

◆ RISCV_HGATP_PPN

#define RISCV_HGATP_PPN ( xlen ) ((xlen) == 32 ? HGATP32_PPN : HGATP64_PPN)

Definition at line 28 of file riscv.h.

◆ RISCV_INFO

#define RISCV_INFO ( R ) struct riscv_info *R = riscv_info(target);

Definition at line 441 of file riscv.h.

◆ RISCV_MAX_DMS

#define RISCV_MAX_DMS 100

Definition at line 21 of file riscv.h.

◆ RISCV_MAX_TRIGGERS

#define RISCV_MAX_TRIGGERS 32

Definition at line 20 of file riscv.h.

◆ RISCV_PGBASE

#define RISCV_PGBASE ( addr ) ((addr) & ~(RISCV_PGSIZE - 1))

Definition at line 31 of file riscv.h.

◆ RISCV_PGOFFSET

#define RISCV_PGOFFSET ( addr ) ((addr) & (RISCV_PGSIZE - 1))

Definition at line 32 of file riscv.h.

◆ RISCV_PGSHIFT

#define RISCV_PGSHIFT 12

Definition at line 29 of file riscv.h.

◆ RISCV_PGSIZE

#define RISCV_PGSIZE BIT(RISCV_PGSHIFT)

Definition at line 30 of file riscv.h.

◆ RISCV_SAMPLE_BUF_TIMESTAMP_AFTER

#define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER 0x81

Definition at line 102 of file riscv.h.

◆ RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE

#define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE 0x80

Definition at line 101 of file riscv.h.

◆ RISCV_SATP_MODE

#define RISCV_SATP_MODE ( xlen ) ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)

Definition at line 25 of file riscv.h.

◆ RISCV_SATP_PPN

#define RISCV_SATP_PPN ( xlen ) ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)

Definition at line 26 of file riscv.h.

◆ RISCV_TINFO_VERSION_UNKNOWN

#define RISCV_TINFO_VERSION_UNKNOWN (-1)

Definition at line 125 of file riscv.h.

Typedef Documentation

◆ riscv_addr_t

typedef uint64_t riscv_addr_t

Definition at line 46 of file riscv.h.

◆ riscv_insn_t

typedef uint32_t riscv_insn_t

Definition at line 45 of file riscv.h.

◆ riscv_reg_t

typedef uint64_t riscv_reg_t

Definition at line 44 of file riscv.h.

Enumeration Type Documentation

◆ bscan_tunnel_type_t

enum bscan_tunnel_type_t

Enumerator
BSCAN_TUNNEL_NESTED_TAP
BSCAN_TUNNEL_DATA_REGISTER

Definition at line 456 of file riscv.h.

◆ riscv_halt_reason

enum riscv_halt_reason

Enumerator
RISCV_HALT_INTERRUPT
RISCV_HALT_EBREAK
RISCV_HALT_SINGLESTEP
RISCV_HALT_TRIGGER
RISCV_HALT_UNKNOWN
RISCV_HALT_GROUP
RISCV_HALT_CRITICAL_ERROR
RISCV_HALT_ERROR

Definition at line 69 of file riscv.h.

◆ riscv_hart_state

enum riscv_hart_state

Enumerator
RISCV_STATE_NON_EXISTENT
RISCV_STATE_RUNNING
RISCV_STATE_HALTED
RISCV_STATE_UNAVAILABLE

Definition at line 87 of file riscv.h.

◆ riscv_isrmasking_mode

enum riscv_isrmasking_mode

Enumerator
RISCV_ISRMASK_OFF
RISCV_ISRMASK_STEPONLY

Definition at line 80 of file riscv.h.

◆ riscv_mem_access_method

enum riscv_mem_access_method

Enumerator
RISCV_MEM_ACCESS_PROGBUF
RISCV_MEM_ACCESS_SYSBUS
RISCV_MEM_ACCESS_ABSTRACT
RISCV_MEM_ACCESS_MAX_METHODS_NUM

Definition at line 54 of file riscv.h.

◆ riscv_priv_mode

enum riscv_priv_mode

Enumerator
RISCV_MODE_M
RISCV_MODE_S
RISCV_MODE_U
RISCV_MODE_VS
RISCV_MODE_VU
N_RISCV_MODE

Definition at line 135 of file riscv.h.

◆ riscv_virt2phys_mode

enum riscv_virt2phys_mode

Enumerator
RISCV_VIRT2PHYS_MODE_HW
RISCV_VIRT2PHYS_MODE_SW
RISCV_VIRT2PHYS_MODE_OFF

Definition at line 61 of file riscv.h.

◆ yes_no_maybe

enum yes_no_maybe

Enumerator
YNM_MAYBE
YNM_YES
YNM_NO

Definition at line 48 of file riscv.h.

Function Documentation

◆ COMMAND_HELPER()

COMMAND_HELPER	(	riscv_print_info_line	,
		const char *	section,
		const char *	key,
		unsigned int	value
	)

Definition at line 5562 of file riscv.c.

References CALL_COMMAND_HANDLER.

◆ dtmcs_scan()

int dtmcs_scan	(	struct jtag_tap *	tap,
		uint32_t	out,
		uint32_t *	in_ptr
	)

Definition at line 423 of file riscv.c.

References bscan_tunnel_ir_width, buf_get_u32(), buf_set_u32(), dtmcs_scan_via_bscan(), ERROR_OK, scan_field::in_value, jtag_add_dr_scan(), jtag_add_ir_scan(), jtag_execute_queue(), jtag_tap_name(), LOG_DEBUG, LOG_ERROR, NULL, scan_field::num_bits, select_dbus, select_dtmcontrol, and TAP_IDLE.

Referenced by examine(), increase_dbus_busy_delay(), increase_dmi_busy_delay(), and riscv_examine().

◆ is_riscv()

static bool is_riscv ( const struct riscv_info * riscv_info )

inlinestatic

Definition at line 443 of file riscv.h.

References riscv_info::common_magic, and RISCV_COMMON_MAGIC.

Referenced by fespi_write().

◆ riscv_add_bscan_tunneled_scan()

void riscv_add_bscan_tunneled_scan	(	struct jtag_tap *	tap,
		const struct scan_field *	field,
		riscv_bscan_tunneled_scan_context_t *	ctxt
	)

Definition at line 6529 of file riscv.c.

References ARRAY_SIZE, bscan_one, BSCAN_TUNNEL_DATA_REGISTER, bscan_tunnel_type, bscan_zero, scan_field::in_value, jtag_add_dr_scan(), jtag_add_ir_scan(), scan_field::num_bits, scan_field::out_value, select_user4, TAP_IDLE, riscv_bscan_tunneled_scan_context_t::tunneled_dr, and riscv_bscan_tunneled_scan_context_t::tunneled_dr_width.

Referenced by riscv_batch_run_from().

◆ riscv_add_watchpoint()

int riscv_add_watchpoint	(	struct target *	target,
		struct watchpoint *	watchpoint
	)

Definition at line 1764 of file riscv.c.

References add_trigger(), ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, find_first_trigger_by_id(), LOG_TARGET_ERROR, watchpoint::mask, trigger_from_watchpoint(), watchpoint::unique_id, WATCHPOINT_IGNORE_DATA_VALUE_MASK, and watchpoint_set().

Referenced by enable_watchpoints(), and strict_step().

◆ riscv_enumerate_triggers()

int riscv_enumerate_triggers ( struct target * target )

Count triggers, and initialize trigger_count for each hart.

trigger_count is initialized even if this function fails to discover something. Disable any hardware triggers that have dmode set. We can't have set them ourselves. Maybe they're left over from some killed debug session.

Definition at line 6444 of file riscv.c.

References ARRAY_SIZE, check_if_trigger_exists(), create_wp_trigger_cache(), CSR_TINFO_VERSION, disable_trigger_if_dmode(), ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_HALTED, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, GDB_REGNO_TDATA1, GDB_REGNO_TINFO, GDB_REGNO_TSELECT, get_field(), get_trigger_types(), LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_INFO, LOG_TARGET_WARNING, NULL, RISCV_INFO, riscv_reg_get(), riscv_reg_set(), RISCV_TINFO_VERSION_UNKNOWN, target::state, and TARGET_HALTED.