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mips32.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2008 by Spencer Oliver *
5  * spen@spen-soft.co.uk *
6  * *
7  * Copyright (C) 2008 by David T.L. Wong *
8  * *
9  * Copyright (C) 2007,2008 Øyvind Harboe *
10  * oyvind.harboe@zylin.com *
11  * *
12  * Copyright (C) 2011 by Drasko DRASKOVIC *
13  * drasko.draskovic@gmail.com *
14  ***************************************************************************/
15 
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19 
20 #include "mips32.h"
21 #include "mips_cpu.h"
22 #include "breakpoints.h"
23 #include "algorithm.h"
24 #include "register.h"
25 
26 static const char *mips_isa_strings[] = {
27  "MIPS32", "MIPS16", "", "MICRO MIPS32",
28 };
29 
30 #define MIPS32_GDB_FP_REG 1
31 
32 /*
33  * GDB registers
34  * based on gdb-7.6.2/gdb/features/mips-{fpu,cp0,cpu,dsp}.xml
35  */
36 static const struct {
37  unsigned int id;
38  const char *name;
39  enum reg_type type;
40  const char *group;
41  const char *feature;
42  int size;
43 } mips32_regs[] = {
44  { 0, "r0", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
45  { 1, "r1", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
46  { 2, "r2", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
47  { 3, "r3", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
48  { 4, "r4", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
49  { 5, "r5", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
50  { 6, "r6", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
51  { 7, "r7", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
52  { 8, "r8", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
53  { 9, "r9", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
54  { 10, "r10", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
55  { 11, "r11", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
56  { 12, "r12", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
57  { 13, "r13", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
58  { 14, "r14", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
59  { 15, "r15", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
60  { 16, "r16", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
61  { 17, "r17", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
62  { 18, "r18", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
63  { 19, "r19", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
64  { 20, "r20", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
65  { 21, "r21", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
66  { 22, "r22", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
67  { 23, "r23", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
68  { 24, "r24", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
69  { 25, "r25", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
70  { 26, "r26", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
71  { 27, "r27", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
72  { 28, "r28", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
73  { 29, "r29", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
74  { 30, "r30", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
75  { 31, "r31", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
76  { 32, "lo", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
77  { 33, "hi", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
78 
79  { MIPS32_REGLIST_FP_INDEX + 0, "f0", REG_TYPE_IEEE_DOUBLE, NULL,
80  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
81  { MIPS32_REGLIST_FP_INDEX + 1, "f1", REG_TYPE_IEEE_DOUBLE, NULL,
82  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
83  { MIPS32_REGLIST_FP_INDEX + 2, "f2", REG_TYPE_IEEE_DOUBLE, NULL,
84  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
85  { MIPS32_REGLIST_FP_INDEX + 3, "f3", REG_TYPE_IEEE_DOUBLE, NULL,
86  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
87  { MIPS32_REGLIST_FP_INDEX + 4, "f4", REG_TYPE_IEEE_DOUBLE, NULL,
88  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
89  { MIPS32_REGLIST_FP_INDEX + 5, "f5", REG_TYPE_IEEE_DOUBLE, NULL,
90  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
91  { MIPS32_REGLIST_FP_INDEX + 6, "f6", REG_TYPE_IEEE_DOUBLE, NULL,
92  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
93  { MIPS32_REGLIST_FP_INDEX + 7, "f7", REG_TYPE_IEEE_DOUBLE, NULL,
94  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
95  { MIPS32_REGLIST_FP_INDEX + 8, "f8", REG_TYPE_IEEE_DOUBLE, NULL,
96  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
97  { MIPS32_REGLIST_FP_INDEX + 9, "f9", REG_TYPE_IEEE_DOUBLE, NULL,
98  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
99  { MIPS32_REGLIST_FP_INDEX + 10, "f10", REG_TYPE_IEEE_DOUBLE, NULL,
100  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
101  { MIPS32_REGLIST_FP_INDEX + 11, "f11", REG_TYPE_IEEE_DOUBLE, NULL,
102  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
103  { MIPS32_REGLIST_FP_INDEX + 12, "f12", REG_TYPE_IEEE_DOUBLE, NULL,
104  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
105  { MIPS32_REGLIST_FP_INDEX + 13, "f13", REG_TYPE_IEEE_DOUBLE, NULL,
106  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
107  { MIPS32_REGLIST_FP_INDEX + 14, "f14", REG_TYPE_IEEE_DOUBLE, NULL,
108  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
109  { MIPS32_REGLIST_FP_INDEX + 15, "f15", REG_TYPE_IEEE_DOUBLE, NULL,
110  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
111  { MIPS32_REGLIST_FP_INDEX + 16, "f16", REG_TYPE_IEEE_DOUBLE, NULL,
112  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
113  { MIPS32_REGLIST_FP_INDEX + 17, "f17", REG_TYPE_IEEE_DOUBLE, NULL,
114  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
115  { MIPS32_REGLIST_FP_INDEX + 18, "f18", REG_TYPE_IEEE_DOUBLE, NULL,
116  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
117  { MIPS32_REGLIST_FP_INDEX + 19, "f19", REG_TYPE_IEEE_DOUBLE, NULL,
118  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
119  { MIPS32_REGLIST_FP_INDEX + 20, "f20", REG_TYPE_IEEE_DOUBLE, NULL,
120  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
121  { MIPS32_REGLIST_FP_INDEX + 21, "f21", REG_TYPE_IEEE_DOUBLE, NULL,
122  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
123  { MIPS32_REGLIST_FP_INDEX + 22, "f22", REG_TYPE_IEEE_DOUBLE, NULL,
124  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
125  { MIPS32_REGLIST_FP_INDEX + 23, "f23", REG_TYPE_IEEE_DOUBLE, NULL,
126  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
127  { MIPS32_REGLIST_FP_INDEX + 24, "f24", REG_TYPE_IEEE_DOUBLE, NULL,
128  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
129  { MIPS32_REGLIST_FP_INDEX + 25, "f25", REG_TYPE_IEEE_DOUBLE, NULL,
130  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
131  { MIPS32_REGLIST_FP_INDEX + 26, "f26", REG_TYPE_IEEE_DOUBLE, NULL,
132  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
133  { MIPS32_REGLIST_FP_INDEX + 27, "f27", REG_TYPE_IEEE_DOUBLE, NULL,
134  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
135  { MIPS32_REGLIST_FP_INDEX + 28, "f28", REG_TYPE_IEEE_DOUBLE, NULL,
136  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
137  { MIPS32_REGLIST_FP_INDEX + 29, "f29", REG_TYPE_IEEE_DOUBLE, NULL,
138  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
139  { MIPS32_REGLIST_FP_INDEX + 30, "f30", REG_TYPE_IEEE_DOUBLE, NULL,
140  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
141  { MIPS32_REGLIST_FP_INDEX + 31, "f31", REG_TYPE_IEEE_DOUBLE, NULL,
142  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
143 
144  { MIPS32_REGLIST_FPC_INDEX + 0, "fcsr", REG_TYPE_INT, "float",
145  "org.gnu.gdb.mips.fpu", 0 },
146  { MIPS32_REGLIST_FPC_INDEX + 1, "fir", REG_TYPE_INT, "float",
147  "org.gnu.gdb.mips.fpu", 0 },
148 
149  { MIPS32_REGLIST_C0_STATUS_INDEX, "status", REG_TYPE_INT, NULL,
150  "org.gnu.gdb.mips.cp0", 0 },
151  { MIPS32_REGLIST_C0_BADVADDR_INDEX, "badvaddr", REG_TYPE_INT, NULL,
152  "org.gnu.gdb.mips.cp0", 0 },
153  { MIPS32_REGLIST_C0_CAUSE_INDEX, "cause", REG_TYPE_INT, NULL,
154  "org.gnu.gdb.mips.cp0", 0 },
155  { MIPS32_REGLIST_C0_PC_INDEX, "pc", REG_TYPE_INT, NULL,
156  "org.gnu.gdb.mips.cpu", 0 },
157  { MIPS32_REGLIST_C0_GUESTCTL1_INDEX, "guestCtl1", REG_TYPE_INT, NULL,
158  "org.gnu.gdb.mips.cp0", 0 },
159 
160  { MIPS32_REGLIST_DSP_INDEX + 0, "hi1", REG_TYPE_INT, NULL,
161  "org.gnu.gdb.mips.dsp", 0 },
162  { MIPS32_REGLIST_DSP_INDEX + 1, "lo1", REG_TYPE_INT, NULL,
163  "org.gnu.gdb.mips.dsp", 0 },
164  { MIPS32_REGLIST_DSP_INDEX + 2, "hi2", REG_TYPE_INT, NULL,
165  "org.gnu.gdb.mips.dsp", 0 },
166  { MIPS32_REGLIST_DSP_INDEX + 3, "lo2", REG_TYPE_INT, NULL,
167  "org.gnu.gdb.mips.dsp", 0 },
168  { MIPS32_REGLIST_DSP_INDEX + 4, "hi3", REG_TYPE_INT, NULL,
169  "org.gnu.gdb.mips.dsp", 0 },
170  { MIPS32_REGLIST_DSP_INDEX + 5, "lo3", REG_TYPE_INT, NULL,
171  "org.gnu.gdb.mips.dsp", 0 },
172 
173  { MIPS32_REGLIST_DSP_DSPCTL_INDEX, "dspctl", REG_TYPE_INT, NULL,
174  "org.gnu.gdb.mips.dsp", 0 },
175 };
176 
177 #define MIPS32_NUM_REGS ARRAY_SIZE(mips32_regs)
178 
179 
180 
181 #define zero 0
182 
183 #define AT 1
184 
185 #define v0 2
186 #define v1 3
187 
188 #define a0 4
189 #define a1 5
190 #define a2 6
191 #define a3 7
192 #define t0 8
193 #define t1 9
194 #define t2 10
195 #define t3 11
196 #define t4 12
197 #define t5 13
198 #define t6 14
199 #define t7 15
200 #define ta0 12 /* alias for $t4 */
201 #define ta1 13 /* alias for $t5 */
202 #define ta2 14 /* alias for $t6 */
203 #define ta3 15 /* alias for $t7 */
204 
205 #define s0 16
206 #define s1 17
207 #define s2 18
208 #define s3 19
209 #define s4 20
210 #define s5 21
211 #define s6 22
212 #define s7 23
213 #define s8 30 /* == fp */
214 
215 #define t8 24
216 #define t9 25
217 #define k0 26
218 #define k1 27
219 
220 #define gp 28
221 
222 #define sp 29
223 #define fp 30
224 #define ra 31
225 
226 
227 static const struct {
228  const char *name;
229 } mips32_dsp_regs[MIPS32NUMDSPREGS] = {
230  { "hi1"},
231  { "lo1"},
232  { "hi2"},
233  { "lo2"},
234  { "hi3"},
235  { "lo3"},
236  { "control"},
237 };
238 
239 static int mips32_get_core_reg(struct reg *reg)
240 {
241  struct mips32_core_reg *mips32_reg = reg->arch_info;
242  struct target *target = mips32_reg->target;
243  struct mips32_common *mips32_target = target_to_mips32(target);
244 
245  if (target->state != TARGET_HALTED)
246  return ERROR_TARGET_NOT_HALTED;
247 
248  return mips32_target->read_core_reg(target, mips32_reg->num);
249 }
250 
251 static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
252 {
253  struct mips32_core_reg *mips32_reg = reg->arch_info;
254  struct target *target = mips32_reg->target;
255  uint64_t value;
256 
257  if (reg->size == 64)
258  value = buf_get_u64(buf, 0, 64);
259  else
260  value = buf_get_u32(buf, 0, 32);
261 
262  if (target->state != TARGET_HALTED)
263  return ERROR_TARGET_NOT_HALTED;
264 
265  if (reg->size == 64)
266  buf_set_u64(reg->value, 0, 64, value);
267  else
268  buf_set_u32(reg->value, 0, 32, value);
269 
270  reg->dirty = true;
271  reg->valid = true;
272 
273  return ERROR_OK;
274 }
275 
283 static void mips32_set_all_fpr_width(struct mips32_common *mips32, bool fp64)
284 {
285  struct reg_cache *cache = mips32->core_cache;
286  struct reg *reg_list = cache->reg_list;
287  int i;
288 
289  for (i = MIPS32_REGLIST_FP_INDEX; i < (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT); i++) {
290  reg_list[i].size = fp64 ? 64 : 32;
291  reg_list[i].reg_data_type->type = fp64 ? REG_TYPE_IEEE_DOUBLE : REG_TYPE_IEEE_SINGLE;
292  }
293 }
294 
304 static void mips32_detect_fpr_mode_change(struct mips32_common *mips32, uint32_t cp0_status)
305 {
306  if (!mips32->fp_imp)
307  return;
308 
309  /* CP0.Status.FR indicates the working mode of floating-point register.
310  * When FP = 0, fpr can contain any 32bit data type,
311  * 64bit data types are stored in even-odd register pairs.
312  * When FP = 1, fpr can contain any data types.*/
313  bool fpu_in_64bit = ((cp0_status & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0);
314 
315  /* CP0.Status.CU1 indicated whether CoProcessor1(which is FPU) is present. */
316  bool fp_enabled = ((cp0_status & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0);
317 
318  if (mips32->fpu_in_64bit != fpu_in_64bit) {
319  mips32->fpu_in_64bit = fpu_in_64bit;
320  mips32_set_all_fpr_width(mips32, fpu_in_64bit);
321  LOG_WARNING("** FP mode changed to %sbit, you must reconnect GDB **", fpu_in_64bit ? "64" : "32");
322  }
323 
324  if (mips32->fpu_enabled != fp_enabled) {
325  mips32->fpu_enabled = fp_enabled;
326  const char *s = fp_enabled ? "enabled" : "disabled";
327  LOG_WARNING("** FP is %s, register update %s **", s, s);
328  }
329 }
330 
331 static int mips32_read_core_reg(struct target *target, unsigned int num)
332 {
333  unsigned int cnum;
334  uint64_t reg_value = 0;
335 
336  /* get pointers to arch-specific information */
337  struct mips32_common *mips32 = target_to_mips32(target);
338 
339  if (num >= MIPS32_NUM_REGS)
340  return ERROR_COMMAND_SYNTAX_ERROR;
341 
342  if (num >= MIPS32_REGLIST_DSP_INDEX) {
343  /* DSP */
344  cnum = num - MIPS32_REGLIST_DSP_INDEX;
345  reg_value = mips32->core_regs.dsp[cnum];
346  buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
347  } else if (num >= MIPS32_REGLIST_C0_INDEX) {
348  /* CP0 */
349  cnum = num - MIPS32_REGLIST_C0_INDEX;
350  reg_value = mips32->core_regs.cp0[cnum];
351  buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
352  if (cnum == MIPS32_REG_C0_STATUS_INDEX)
353  mips32_detect_fpr_mode_change(mips32, reg_value);
354  } else if (num >= MIPS32_REGLIST_FPC_INDEX) {
355  /* FPCR */
356  cnum = num - MIPS32_REGLIST_FPC_INDEX;
357  reg_value = mips32->core_regs.fpcr[cnum];
358  buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
359  } else if (num >= MIPS32_REGLIST_FP_INDEX) {
360  /* FPR */
361  cnum = num - MIPS32_REGLIST_FP_INDEX;
362  reg_value = mips32->core_regs.fpr[cnum];
363  buf_set_u64(mips32->core_cache->reg_list[num].value, 0, 64, reg_value);
364  } else {
365  /* GPR */
366  cnum = num - MIPS32_REGLIST_GP_INDEX;
367  reg_value = mips32->core_regs.gpr[cnum];
368  buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
369  }
370 
371  mips32->core_cache->reg_list[num].valid = true;
372  mips32->core_cache->reg_list[num].dirty = false;
373 
374  LOG_DEBUG("read core reg %i value 0x%" PRIx64, num, reg_value);
375 
376  return ERROR_OK;
377 }
378 
379 static int mips32_write_core_reg(struct target *target, unsigned int num)
380 {
381  unsigned int cnum;
382  uint64_t reg_value;
383 
384  /* get pointers to arch-specific information */
385  struct mips32_common *mips32 = target_to_mips32(target);
386 
387  if (num >= MIPS32_NUM_REGS)
388  return ERROR_COMMAND_SYNTAX_ERROR;
389 
390  if (num >= MIPS32_REGLIST_DSP_INDEX) {
391  /* DSP */
392  cnum = num - MIPS32_REGLIST_DSP_INDEX;
393  reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
394  mips32->core_regs.dsp[cnum] = (uint32_t)reg_value;
395  } else if (num >= MIPS32_REGLIST_C0_INDEX) {
396  /* CP0 */
397  cnum = num - MIPS32_REGLIST_C0_INDEX;
398  reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
399  mips32->core_regs.cp0[cnum] = (uint32_t)reg_value;
400  if (cnum == MIPS32_REG_C0_STATUS_INDEX)
401  mips32_detect_fpr_mode_change(mips32, reg_value);
402  } else if (num >= MIPS32_REGLIST_FPC_INDEX) {
403  /* FPCR */
404  cnum = num - MIPS32_REGLIST_FPC_INDEX;
405  reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
406  mips32->core_regs.fpcr[cnum] = (uint32_t)reg_value;
407  } else if (num >= MIPS32_REGLIST_FP_INDEX) {
408  /* FPR */
409  cnum = num - MIPS32_REGLIST_FP_INDEX;
410  reg_value = buf_get_u64(mips32->core_cache->reg_list[num].value, 0, 64);
411  mips32->core_regs.fpr[cnum] = reg_value;
412  } else {
413  /* GPR */
414  cnum = num - MIPS32_REGLIST_GP_INDEX;
415  reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
416  mips32->core_regs.gpr[cnum] = (uint32_t)reg_value;
417  }
418 
419  LOG_DEBUG("write core reg %i value 0x%" PRIx64, num, reg_value);
420  mips32->core_cache->reg_list[num].valid = true;
421  mips32->core_cache->reg_list[num].dirty = false;
422 
423  return ERROR_OK;
424 }
425 
426 int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
427  int *reg_list_size, enum target_register_class reg_class)
428 {
429  /* get pointers to arch-specific information */
430  struct mips32_common *mips32 = target_to_mips32(target);
431  unsigned int i;
432 
433  /* include floating point registers */
434  *reg_list_size = MIPS32_NUM_REGS;
435  *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
436 
437  for (i = 0; i < MIPS32_NUM_REGS; i++)
438  (*reg_list)[i] = &mips32->core_cache->reg_list[i];
439 
440  return ERROR_OK;
441 }
442 
443 int mips32_save_context(struct target *target)
444 {
445  unsigned int i;
446 
447  /* get pointers to arch-specific information */
448  struct mips32_common *mips32 = target_to_mips32(target);
449 
450  /* read core registers */
451  int retval = mips32_pracc_read_regs(mips32);
452  if (retval != ERROR_OK) {
453  LOG_ERROR("Could not read core registers from target");
454  return retval;
455  }
456 
457  for (i = 0; i < MIPS32_NUM_REGS; i++) {
458  if (!mips32->core_cache->reg_list[i].valid)
459  mips32->read_core_reg(target, i);
460  }
461 
462  return ERROR_OK;
463 }
464 
465 int mips32_restore_context(struct target *target)
466 {
467  unsigned int i;
468 
469  /* get pointers to arch-specific information */
470  struct mips32_common *mips32 = target_to_mips32(target);
471 
472  for (i = 0; i < MIPS32_NUM_REGS; i++) {
473  if (mips32->core_cache->reg_list[i].dirty)
474  mips32->write_core_reg(target, i);
475  }
476 
477  /* write core regs */
478  return mips32_pracc_write_regs(mips32);
479 }
480 
481 int mips32_arch_state(struct target *target)
482 {
483  struct mips32_common *mips32 = target_to_mips32(target);
484 
485  LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32,
486  mips_isa_strings[mips32->isa_mode],
487  debug_reason_name(target),
488  buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32));
489 
490  return ERROR_OK;
491 }
492 
493 static const struct reg_arch_type mips32_reg_type = {
494  .get = mips32_get_core_reg,
495  .set = mips32_set_core_reg,
496 };
497 
498 struct reg_cache *mips32_build_reg_cache(struct target *target)
499 {
500  /* get pointers to arch-specific information */
501  struct mips32_common *mips32 = target_to_mips32(target);
502 
503  int num_regs = MIPS32_NUM_REGS;
504  struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
505  struct reg_cache *cache = malloc(sizeof(struct reg_cache));
506  struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
507  struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
508  struct reg_feature *feature;
509  int i;
510 
511  /* Build the process context cache */
512  cache->name = "mips32 registers";
513  cache->next = NULL;
514  cache->reg_list = reg_list;
515  cache->num_regs = num_regs;
516  (*cache_p) = cache;
517  mips32->core_cache = cache;
518 
519  for (i = 0; i < num_regs; i++) {
520  arch_info[i].num = mips32_regs[i].id;
521  arch_info[i].target = target;
522  arch_info[i].mips32_common = mips32;
523 
524  reg_list[i].name = mips32_regs[i].name;
525  reg_list[i].size = mips32_regs[i].size ? 64 : 32;
526 
527  reg_list[i].value = mips32_regs[i].size ? calloc(1, 8) : calloc(1, 4);
528  reg_list[i].valid = false;
529  reg_list[i].type = &mips32_reg_type;
530  reg_list[i].arch_info = &arch_info[i];
531 
532  reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
533  if (reg_list[i].reg_data_type)
534  reg_list[i].reg_data_type->type = mips32_regs[i].type;
535  else
536  LOG_ERROR("unable to allocate reg type list");
537 
538 
539  reg_list[i].dirty = false;
540 
541  reg_list[i].group = mips32_regs[i].group;
542  reg_list[i].number = i;
543  reg_list[i].exist = true;
544  reg_list[i].caller_save = true; /* gdb defaults to true */
545 
546  feature = calloc(1, sizeof(struct reg_feature));
547  if (feature) {
548  feature->name = mips32_regs[i].feature;
549  reg_list[i].feature = feature;
550  } else
551  LOG_ERROR("unable to allocate feature list");
552  }
553 
554  return cache;
555 }
556 
557 int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
558 {
559  target->arch_info = mips32;
560  mips32->common_magic = MIPS32_COMMON_MAGIC;
561  mips32->fast_data_area = NULL;
562  mips32->isa_imp = MIPS32_ONLY; /* default */
563 
564  /* has breakpoint/watchpoint unit been scanned */
565  mips32->bp_scanned = 0;
566  mips32->data_break_list = NULL;
567 
568  mips32->ejtag_info.tap = tap;
569  mips32->read_core_reg = mips32_read_core_reg;
570  mips32->write_core_reg = mips32_write_core_reg;
571  /* if unknown endianness defaults to little endian, 1 */
572  mips32->ejtag_info.endianness = target->endianness == TARGET_BIG_ENDIAN ? 0 : 1;
573  mips32->ejtag_info.scan_delay = MIPS32_SCAN_DELAY_LEGACY_MODE;
574  mips32->ejtag_info.mode = 0; /* Initial default value */
575  mips32->ejtag_info.isa = 0; /* isa on debug mips32, updated by poll function */
576  mips32->ejtag_info.config_regs = 0; /* no config register read */
577  return ERROR_OK;
578 }
579 
580 /* run to exit point. return error if exit point was not reached. */
581 static int mips32_run_and_wait(struct target *target, target_addr_t entry_point,
582  unsigned int timeout_ms, target_addr_t exit_point, struct mips32_common *mips32)
583 {
584  uint32_t pc;
585  int retval;
586  /* This code relies on the target specific resume() and poll()->debug_entry()
587  * sequence to write register values to the processor and the read them back */
588  retval = target_resume(target, false, entry_point, false, true);
589  if (retval != ERROR_OK)
590  return retval;
591 
592  retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
593  /* If the target fails to halt due to the breakpoint, force a halt */
594  if (retval != ERROR_OK || target->state != TARGET_HALTED) {
595  retval = target_halt(target);
596  if (retval != ERROR_OK)
597  return retval;
598  retval = target_wait_state(target, TARGET_HALTED, 500);
599  if (retval != ERROR_OK)
600  return retval;
601  return ERROR_TARGET_TIMEOUT;
602  }
603 
604  pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32);
605  if (exit_point && (pc != exit_point)) {
606  LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
607  return ERROR_TARGET_TIMEOUT;
608  }
609 
610  return ERROR_OK;
611 }
612 
613 int mips32_run_algorithm(struct target *target, int num_mem_params,
614  struct mem_param *mem_params, int num_reg_params,
615  struct reg_param *reg_params, target_addr_t entry_point,
616  target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
617 {
618  struct mips32_common *mips32 = target_to_mips32(target);
619  struct mips32_algorithm *mips32_algorithm_info = arch_info;
620  enum mips32_isa_mode isa_mode = mips32->isa_mode;
621 
622  uint32_t context[MIPS32_NUM_REGS];
623  int retval = ERROR_OK;
624 
625  LOG_DEBUG("Running algorithm");
626 
627  /* NOTE: mips32_run_algorithm requires that each algorithm uses a software breakpoint
628  * at the exit point */
629 
630  if (mips32->common_magic != MIPS32_COMMON_MAGIC) {
631  LOG_ERROR("current target isn't a MIPS32 target");
632  return ERROR_TARGET_INVALID;
633  }
634 
635  if (target->state != TARGET_HALTED) {
636  LOG_TARGET_ERROR(target, "not halted (run target algo)");
637  return ERROR_TARGET_NOT_HALTED;
638  }
639 
640  /* refresh core register cache */
641  for (unsigned int i = 0; i < MIPS32_NUM_REGS; i++) {
642  if (!mips32->core_cache->reg_list[i].valid)
643  mips32->read_core_reg(target, i);
644  context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
645  }
646 
647  for (int i = 0; i < num_mem_params; i++) {
648  if (mem_params[i].direction == PARAM_IN)
649  continue;
650  retval = target_write_buffer(target, mem_params[i].address,
651  mem_params[i].size, mem_params[i].value);
652  if (retval != ERROR_OK)
653  return retval;
654  }
655 
656  for (int i = 0; i < num_reg_params; i++) {
657  if (reg_params[i].direction == PARAM_IN)
658  continue;
659 
660  struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, false);
661 
662  if (!reg) {
663  LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
664  return ERROR_COMMAND_SYNTAX_ERROR;
665  }
666 
667  if (reg->size != reg_params[i].size) {
668  LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
669  reg_params[i].reg_name);
670  return ERROR_COMMAND_SYNTAX_ERROR;
671  }
672 
673  mips32_set_core_reg(reg, reg_params[i].value);
674  }
675 
676  mips32->isa_mode = mips32_algorithm_info->isa_mode;
677 
678  retval = mips32_run_and_wait(target, entry_point, timeout_ms, exit_point, mips32);
679 
680  if (retval != ERROR_OK)
681  return retval;
682 
683  for (int i = 0; i < num_mem_params; i++) {
684  if (mem_params[i].direction != PARAM_OUT) {
685  retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size,
686  mem_params[i].value);
687  if (retval != ERROR_OK)
688  return retval;
689  }
690  }
691 
692  for (int i = 0; i < num_reg_params; i++) {
693  if (reg_params[i].direction != PARAM_OUT) {
694  struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, false);
695  if (!reg) {
696  LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
697  return ERROR_COMMAND_SYNTAX_ERROR;
698  }
699 
700  if (reg->size != reg_params[i].size) {
701  LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
702  reg_params[i].reg_name);
703  return ERROR_COMMAND_SYNTAX_ERROR;
704  }
705 
706  buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
707  }
708  }
709 
710  /* restore everything we saved before */
711  for (unsigned int i = 0; i < MIPS32_NUM_REGS; i++) {
712  uint32_t regvalue;
713  regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
714  if (regvalue != context[i]) {
715  LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
716  mips32->core_cache->reg_list[i].name, context[i]);
717  buf_set_u32(mips32->core_cache->reg_list[i].value,
718  0, 32, context[i]);
719  mips32->core_cache->reg_list[i].valid = true;
720  mips32->core_cache->reg_list[i].dirty = true;
721  }
722  }
723 
724  mips32->isa_mode = isa_mode;
725 
726  return ERROR_OK;
727 }
728 
729 int mips32_examine(struct target *target)
730 {
731  struct mips32_common *mips32 = target_to_mips32(target);
732 
733  if (!target_was_examined(target)) {
734  /* we will configure later */
735  mips32->bp_scanned = 0;
736  mips32->num_inst_bpoints = 0;
737  mips32->num_data_bpoints = 0;
738  mips32->num_inst_bpoints_avail = 0;
739  mips32->num_data_bpoints_avail = 0;
740  }
741 
742  return ERROR_OK;
743 }
744 
745 static int mips32_configure_ibs(struct target *target)
746 {
747  struct mips32_common *mips32 = target_to_mips32(target);
748  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
749  int retval, i;
750  uint32_t bpinfo;
751 
752  /* get number of inst breakpoints */
753  retval = target_read_u32(target, ejtag_info->ejtag_ibs_addr, &bpinfo);
754  if (retval != ERROR_OK)
755  return retval;
756 
757  mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
758  mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
759  mips32->inst_break_list = calloc(mips32->num_inst_bpoints,
760  sizeof(struct mips32_comparator));
761 
762  for (i = 0; i < mips32->num_inst_bpoints; i++)
763  mips32->inst_break_list[i].reg_address =
764  ejtag_info->ejtag_iba0_addr +
765  (ejtag_info->ejtag_iba_step_size * i);
766 
767  /* clear IBIS reg */
768  return target_write_u32(target, ejtag_info->ejtag_ibs_addr, 0);
769 }
770 
771 static int mips32_configure_dbs(struct target *target)
772 {
773  struct mips32_common *mips32 = target_to_mips32(target);
774  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
775  int retval, i;
776  uint32_t bpinfo;
777 
778  /* get number of data breakpoints */
779  retval = target_read_u32(target, ejtag_info->ejtag_dbs_addr, &bpinfo);
780  if (retval != ERROR_OK)
781  return retval;
782 
783  mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
784  mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
785  mips32->data_break_list = calloc(mips32->num_data_bpoints,
786  sizeof(struct mips32_comparator));
787 
788  for (i = 0; i < mips32->num_data_bpoints; i++)
789  mips32->data_break_list[i].reg_address =
790  ejtag_info->ejtag_dba0_addr +
791  (ejtag_info->ejtag_dba_step_size * i);
792 
793  /* clear DBIS reg */
794  return target_write_u32(target, ejtag_info->ejtag_dbs_addr, 0);
795 }
796 
797 int mips32_configure_break_unit(struct target *target)
798 {
799  /* get pointers to arch-specific information */
800  struct mips32_common *mips32 = target_to_mips32(target);
801  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
802  int retval;
803  uint32_t dcr;
804 
805  if (mips32->bp_scanned)
806  return ERROR_OK;
807 
808  /* get info about breakpoint support */
809  retval = target_read_u32(target, EJTAG_DCR, &dcr);
810  if (retval != ERROR_OK)
811  return retval;
812 
813  /* EJTAG 2.0 defines IB and DB bits in IMP instead of DCR. */
814  if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
815  ejtag_info->debug_caps = dcr & EJTAG_DCR_ENM;
816  if (!(ejtag_info->impcode & EJTAG_V20_IMP_NOIB))
817  ejtag_info->debug_caps |= EJTAG_DCR_IB;
818  if (!(ejtag_info->impcode & EJTAG_V20_IMP_NODB))
819  ejtag_info->debug_caps |= EJTAG_DCR_DB;
820  } else
821  /* keep debug caps for later use */
822  ejtag_info->debug_caps = dcr & (EJTAG_DCR_ENM
823  | EJTAG_DCR_IB | EJTAG_DCR_DB);
824 
825 
826  if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
827  retval = mips32_configure_ibs(target);
828  if (retval != ERROR_OK)
829  return retval;
830  }
831 
832  if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
833  retval = mips32_configure_dbs(target);
834  if (retval != ERROR_OK)
835  return retval;
836  }
837 
838  /* check if target endianness settings matches debug control register */
839  if (((ejtag_info->debug_caps & EJTAG_DCR_ENM)
840  && (target->endianness == TARGET_LITTLE_ENDIAN)) ||
841  (!(ejtag_info->debug_caps & EJTAG_DCR_ENM)
842  && (target->endianness == TARGET_BIG_ENDIAN)))
843  LOG_WARNING("DCR endianness settings does not match target settings");
844 
845  LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
846  mips32->num_data_bpoints);
847 
848  mips32->bp_scanned = 1;
849 
850  return ERROR_OK;
851 }
852 
853 int mips32_enable_interrupts(struct target *target, int enable)
854 {
855  int retval;
856  int update = 0;
857  uint32_t dcr;
858 
859  /* read debug control register */
860  retval = target_read_u32(target, EJTAG_DCR, &dcr);
861  if (retval != ERROR_OK)
862  return retval;
863 
864  if (enable) {
865  if (!(dcr & EJTAG_DCR_INTE)) {
866  /* enable interrupts */
867  dcr |= EJTAG_DCR_INTE;
868  update = 1;
869  }
870  } else {
871  if (dcr & EJTAG_DCR_INTE) {
872  /* disable interrupts */
873  dcr &= ~EJTAG_DCR_INTE;
874  update = 1;
875  }
876  }
877 
878  if (update) {
879  retval = target_write_u32(target, EJTAG_DCR, dcr);
880  if (retval != ERROR_OK)
881  return retval;
882  }
883 
884  return ERROR_OK;
885 }
886 
887 /* read processor identification cp0 register */
888 static int mips32_read_c0_prid(struct target *target)
889 {
890  struct mips32_common *mips32 = target_to_mips32(target);
891  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
892  int retval;
893 
894  retval = mips32_cp0_read(ejtag_info, &mips32->prid, 15, 0);
895  if (retval != ERROR_OK) {
896  LOG_ERROR("processor id not available, failed to read cp0 PRId register");
897  mips32->prid = 0;
898  }
899 
900  return retval;
901 }
902 
913 static const struct cpu_entry *mips32_find_cpu_by_prid(uint32_t prid)
914 {
915  /* AMD/Alchemy CPU uses Company Options instead of Processor ID.
916  * Therefore an extra transform step for prid to map it to an assigned ID,
917  */
918  if ((prid & PRID_COMP_MASK) == PRID_COMP_ALCHEMY) {
919  /* Clears Processor ID field, then put Company Option field to its place */
920  prid = (prid & 0xFFFF00FF) | ((prid & 0xFF000000) >> 16);
921  }
922 
923  /* Mask out Company Option */
924  prid &= 0x00FFFFFF;
925 
926  for (unsigned int i = 0; i < MIPS32_NUM_CPU_ENTRIES; i++) {
927  const struct cpu_entry *entry = &mips32_cpu_entry[i];
928  if ((entry->prid & MIPS32_CORE_MASK) <= prid && prid <= entry->prid)
929  return entry;
930  }
931 
932  /* If nothing matched, then return unknown entry */
933  return &mips32_cpu_entry[MIPS32_NUM_CPU_ENTRIES - 1];
934 }
935 
936 static bool mips32_cpu_is_lexra(struct mips_ejtag *ejtag_info)
937 {
938  return (ejtag_info->prid & PRID_COMP_MASK) == PRID_COMP_LEXRA;
939 }
940 
941 static int mips32_cpu_get_release(struct mips_ejtag *ejtag_info)
942 {
943  return (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
944 }
945 
956 bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info)
957 {
958  return !mips32_cpu_is_lexra(ejtag_info);
959 }
960 
969 bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info)
970 {
971  return mips32_cpu_get_release(ejtag_info) > MIPS32_RELEASE_1;
972 }
973 
988 int mips32_cpu_probe(struct target *target)
989 {
990  struct mips32_common *mips32 = target_to_mips32(target);
991  int retval;
992 
993  if (mips32->prid)
994  return ERROR_OK; /* Already probed once, return early. */
995 
996  retval = mips32_read_c0_prid(target);
997  if (retval != ERROR_OK)
998  return retval;
999 
1000  const struct cpu_entry *entry = mips32_find_cpu_by_prid(mips32->prid);
1001 
1002  switch (mips32->prid & PRID_COMP_MASK) {
1003  case PRID_COMP_INGENIC_E1:
1004  switch (mips32->prid & PRID_IMP_MASK) {
1005  case PRID_IMP_XBURST_REV1:
1006  mips32->cpu_quirks |= EJTAG_QUIRK_PAD_DRET;
1007  break;
1008  default:
1009  break;
1010  }
1011  break;
1012 
1013  /* Determine which CP0 registers are available in the current processor core */
1014  case PRID_COMP_MTI:
1015  switch (entry->prid & PRID_IMP_MASK) {
1016  case PRID_IMP_MAPTIV_UC:
1017  mips32->cp0_mask = MIPS_CP0_MAPTIV_UC;
1018  break;
1019  case PRID_IMP_MAPTIV_UP:
1020  case PRID_IMP_M5150:
1021  mips32->cp0_mask = MIPS_CP0_MAPTIV_UP;
1022  break;
1023  case PRID_IMP_IAPTIV:
1024  case PRID_IMP_IAPTIV_CM:
1025  mips32->cp0_mask = MIPS_CP0_IAPTIV;
1026  break;
1027  default:
1028  /* CP0 mask should be the same as MK4 by default */
1029  mips32->cp0_mask = MIPS_CP0_MK4;
1030  break;
1031  }
1032 
1033  default:
1034  break;
1035  }
1036 
1037  mips32->cpu_info = entry;
1038  LOG_DEBUG("CPU: %s (PRId %08x)", entry->cpu_name, mips32->prid);
1039 
1040  return ERROR_OK;
1041 }
1042 
1043 /* reads dsp implementation info from CP0 Config3 register {DSPP, DSPREV}*/
1044 static void mips32_read_config_dsp(struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
1045 {
1046  uint32_t retval, status_value, dsp_present;
1047  bool dsp_enabled;
1048 
1049  retval = mips32_cp0_read(ejtag_info, &status_value, MIPS32_C0_STATUS, 0);
1050  if (retval != ERROR_OK) {
1051  LOG_ERROR("Failed to read cp0 status register");
1052  return;
1053  }
1054 
1055  dsp_present = ((ejtag_info->config[3] & MIPS32_CONFIG3_DSPP_MASK) >> MIPS32_CONFIG3_DSPP_SHIFT);
1056  dsp_enabled = (status_value & BIT(MIPS32_CP0_STATUS_MX_SHIFT)) != 0;
1057  if (dsp_present) {
1058  mips32->dsp_imp = ((ejtag_info->config[3] & MIPS32_CONFIG3_DSPREV_MASK) >> MIPS32_CONFIG3_DSPREV_SHIFT) + 1;
1059  LOG_USER("DSP implemented: rev %d, %s", mips32->dsp_imp, dsp_enabled ? "enabled" : "disabled");
1060  } else {
1061  LOG_USER("DSP implemented: %s", "no");
1062  }
1063 }
1064 
1065 /* read fpu implementation info from CP0 Config1 register {CU1, FP}*/
1066 static int mips32_read_config_fpu(struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
1067 {
1068  int retval;
1069  uint32_t fp_imp = (ejtag_info->config[1] & MIPS32_CONFIG1_FP_MASK) >> MIPS32_CONFIG1_FP_SHIFT;
1070  char buf[60] = {0};
1071  if (!fp_imp) {
1072  LOG_USER("FPU implemented: %s", "no");
1073  mips32->fp_imp = MIPS32_FP_IMP_NONE;
1074  return ERROR_OK;
1075  }
1076  uint32_t fir_value, status_value;
1077  bool fpu_in_64bit, fp_enabled;
1078 
1079  retval = mips32_cp0_read(ejtag_info, &status_value, MIPS32_C0_STATUS, 0);
1080  if (retval != ERROR_OK) {
1081  LOG_ERROR("Failed to read cp0 status register");
1082  return retval;
1083  }
1084 
1085  fpu_in_64bit = (status_value & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0;
1086  fp_enabled = (status_value & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0;
1087  if (fp_enabled) {
1088  retval = mips32_cp1_control_read(ejtag_info, &fir_value, 0);
1089  if (retval != ERROR_OK) {
1090  LOG_ERROR("Failed to read cp1 FIR register");
1091  return retval;
1092  }
1093 
1094  if ((fir_value >> MIPS32_CP1_FIR_F64_SHIFT) & 0x1)
1095  fp_imp++;
1096  } else {
1097  /* This is the only condition that writes to buf */
1098  snprintf(buf, sizeof(buf), "yes, disabled");
1099  fp_imp = MIPS32_FP_IMP_UNKNOWN;
1100  }
1101 
1102  mips32->fpu_in_64bit = fpu_in_64bit;
1103  mips32->fpu_enabled = fp_enabled;
1104 
1105  mips32_set_all_fpr_width(mips32, fpu_in_64bit);
1106 
1107  /* If fpu is not disabled, print out more information */
1108  if (!buf[0])
1109  snprintf(buf, sizeof(buf), "yes, %sbit (%s, working in %sbit)",
1110  fp_imp == MIPS32_FP_IMP_64 ? "64" : "32",
1111  fp_enabled ? "enabled" : "disabled",
1112  fpu_in_64bit ? "64" : "32");
1113 
1114  LOG_USER("FPU implemented: %s", buf);
1115  mips32->fp_imp = fp_imp;
1116 
1117  return ERROR_OK;
1118 }
1119 
1136 static void mips32_read_config_fdc(struct mips32_common *mips32, struct mips_ejtag *ejtag_info, uint32_t dcr)
1137 {
1138  if (((ejtag_info->config[3] & MIPS32_CONFIG3_CDMM_MASK) != 0) && ((dcr & EJTAG_DCR_FDC) != 0)) {
1139  mips32->fdc = 1;
1140  mips32->semihosting = 1;
1141  } else {
1142  mips32->fdc = 0;
1143  mips32->semihosting = 0;
1144  }
1145 }
1146 
1147 /* read config to config3 cp0 registers and log isa implementation */
1148 int mips32_read_config_regs(struct target *target)
1149 {
1150  struct mips32_common *mips32 = target_to_mips32(target);
1151  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1152  char buf[60] = {0};
1153  int retval;
1154 
1155  if (ejtag_info->config_regs == 0)
1156  for (int i = 0; i != 4; i++) {
1157  retval = mips32_cp0_read(ejtag_info, &ejtag_info->config[i], 16, i);
1158  if (retval != ERROR_OK) {
1159  LOG_ERROR("isa info not available, failed to read cp0 config register: %" PRId32, i);
1160  ejtag_info->config_regs = 0;
1161  return retval;
1162  }
1163  ejtag_info->config_regs = i + 1;
1164  if ((ejtag_info->config[i] & (1 << 31)) == 0)
1165  break; /* no more config registers implemented */
1166  }
1167  else
1168  return ERROR_OK; /* already successfully read */
1169 
1170  LOG_DEBUG("read %"PRIu32" config registers", ejtag_info->config_regs);
1171 
1172  mips32->isa_rel = (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
1173  snprintf(buf, sizeof(buf), ", release %s(AR=%d)",
1174  mips32->isa_rel == MIPS32_RELEASE_1 ? "1"
1175  : mips32->isa_rel == MIPS32_RELEASE_2 ? "2"
1176  : mips32->isa_rel == MIPS32_RELEASE_6 ? "6"
1177  : "unknown", mips32->isa_rel);
1178 
1179  if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
1180  mips32->isa_imp = MIPS32_MIPS16;
1181  LOG_USER("ISA implemented: %s%s", "MIPS32, MIPS16", buf);
1182  } else if (ejtag_info->config_regs >= 4) { /* config3 implemented */
1183  unsigned int isa_imp = (ejtag_info->config[3] & MIPS32_CONFIG3_ISA_MASK) >> MIPS32_CONFIG3_ISA_SHIFT;
1184  if (isa_imp == 1) {
1185  mips32->isa_imp = MMIPS32_ONLY;
1186  LOG_USER("ISA implemented: %s%s", "microMIPS32", buf);
1187 
1188  } else if (isa_imp != 0) {
1189  mips32->isa_imp = MIPS32_MMIPS32;
1190  LOG_USER("ISA implemented: %s%s", "MIPS32, microMIPS32", buf);
1191  }
1192  } else if (mips32->isa_imp == MIPS32_ONLY) {
1193  /* initial default value */
1194  LOG_USER("ISA implemented: %s%s", "MIPS32", buf);
1195  }
1196 
1197  /* Retrieve DSP info */
1198  mips32_read_config_dsp(mips32, ejtag_info);
1199 
1200  /* Retrieve if Float Point CoProcessor Implemented */
1201  retval = mips32_read_config_fpu(mips32, ejtag_info);
1202  if (retval != ERROR_OK) {
1203  LOG_ERROR("fpu info is not available, error while reading cp0 status");
1204  mips32->fp_imp = MIPS32_FP_IMP_NONE;
1205  return retval;
1206  }
1207 
1208  uint32_t dcr;
1209 
1210  retval = target_read_u32(target, EJTAG_DCR, &dcr);
1211  if (retval != ERROR_OK) {
1212  LOG_ERROR("failed to read EJTAG_DCR register");
1213  return retval;
1214  }
1215 
1216  /* Determine if FDC and CDMM are implemented for this core */
1217  mips32_read_config_fdc(mips32, ejtag_info, dcr);
1218 
1219  return ERROR_OK;
1220 }
1221 
1222 int mips32_checksum_memory(struct target *target, target_addr_t address,
1223  uint32_t count, uint32_t *checksum)
1224 {
1225  struct working_area *crc_algorithm;
1226  struct reg_param reg_params[2];
1227  struct mips32_algorithm mips32_info;
1228 
1229  struct mips32_common *mips32 = target_to_mips32(target);
1230  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1231 
1232  /* see contrib/loaders/checksum/mips32.s for src */
1233  uint32_t isa = ejtag_info->isa ? 1 : 0;
1234 
1235  uint32_t mips_crc_code[] = {
1236  MIPS32_ADDIU(isa, 12, 4, 0), /* addiu $t4, $a0, 0 */
1237  MIPS32_ADDIU(isa, 10, 5, 0), /* addiu $t2, $a1, 0 */
1238  MIPS32_ADDIU(isa, 4, 0, 0xFFFF), /* addiu $a0, $zero, 0xffff */
1239  MIPS32_BEQ(isa, 0, 0, 0x10 << isa), /* beq $zero, $zero, ncomp */
1240  MIPS32_ADDIU(isa, 11, 0, 0), /* addiu $t3, $zero, 0 */
1241  /* nbyte: */
1242  MIPS32_LB(isa, 5, 0, 12), /* lb $a1, ($t4) */
1243  MIPS32_ADDI(isa, 12, 12, 1), /* addi $t4, $t4, 1 */
1244  MIPS32_SLL(isa, 5, 5, 24), /* sll $a1, $a1, 24 */
1245  MIPS32_LUI(isa, 2, 0x04c1), /* lui $v0, 0x04c1 */
1246  MIPS32_XOR(isa, 4, 4, 5), /* xor $a0, $a0, $a1 */
1247  MIPS32_ORI(isa, 7, 2, 0x1db7), /* ori $a3, $v0, 0x1db7 */
1248  MIPS32_ADDU(isa, 6, 0, 0), /* addu $a2, $zero, $zero */
1249  /* loop */
1250  MIPS32_SLL(isa, 8, 4, 1), /* sll $t0, $a0, 1 */
1251  MIPS32_ADDIU(isa, 6, 6, 1), /* addiu $a2, $a2, 1 */
1252  MIPS32_SLTI(isa, 4, 4, 0), /* slti $a0, $a0, 0 */
1253  MIPS32_XOR(isa, 9, 8, 7), /* xor $t1, $t0, $a3 */
1254  MIPS32_MOVN(isa, 8, 9, 4), /* movn $t0, $t1, $a0 */
1255  MIPS32_SLTI(isa, 3, 6, 8), /* slti $v1, $a2, 8 */
1256  MIPS32_BNE(isa, 3, 0, NEG16(7 << isa)), /* bne $v1, $zero, loop */
1257  MIPS32_ADDU(isa, 4, 8, 0), /* addu $a0, $t0, $zero */
1258  /* ncomp */
1259  MIPS32_BNE(isa, 10, 11, NEG16(16 << isa)), /* bne $t2, $t3, nbyte */
1260  MIPS32_ADDIU(isa, 11, 11, 1), /* addiu $t3, $t3, 1 */
1261  MIPS32_SDBBP(isa),
1262  };
1263 
1264  /* make sure we have a working area */
1265  if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK)
1266  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1267 
1268  pracc_swap16_array(ejtag_info, mips_crc_code, ARRAY_SIZE(mips_crc_code));
1269 
1270  /* convert mips crc code into a buffer in target endianness */
1271  uint8_t mips_crc_code_8[sizeof(mips_crc_code)];
1272  target_buffer_set_u32_array(target, mips_crc_code_8,
1273  ARRAY_SIZE(mips_crc_code), mips_crc_code);
1274 
1275  int retval = target_write_buffer(target, crc_algorithm->address, sizeof(mips_crc_code), mips_crc_code_8);
1276  if (retval != ERROR_OK)
1277  return retval;
1278 
1279  mips32_info.common_magic = MIPS32_COMMON_MAGIC;
1280  mips32_info.isa_mode = isa ? MIPS32_ISA_MMIPS32 : MIPS32_ISA_MIPS32; /* run isa as in debug mode */
1281 
1282  init_reg_param(&reg_params[0], "r4", 32, PARAM_IN_OUT);
1283  buf_set_u32(reg_params[0].value, 0, 32, address);
1284 
1285  init_reg_param(&reg_params[1], "r5", 32, PARAM_OUT);
1286  buf_set_u32(reg_params[1].value, 0, 32, count);
1287 
1288  unsigned int timeout = 20000 * (1 + (count / (1024 * 1024)));
1289 
1290  retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
1291  crc_algorithm->address + (sizeof(mips_crc_code) - 4), timeout, &mips32_info);
1292 
1293  if (retval == ERROR_OK)
1294  *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1295 
1296  destroy_reg_param(&reg_params[0]);
1297  destroy_reg_param(&reg_params[1]);
1298 
1299  target_free_working_area(target, crc_algorithm);
1300 
1301  return retval;
1302 }
1303 
1305 int mips32_blank_check_memory(struct target *target,
1306  struct target_memory_check_block *blocks, unsigned int num_blocks,
1307  uint8_t erased_value, unsigned int *checked)
1308 {
1309  struct working_area *erase_check_algorithm;
1310  struct reg_param reg_params[3];
1311  struct mips32_algorithm mips32_info;
1312 
1313  struct mips32_common *mips32 = target_to_mips32(target);
1314  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1315 
1316  if (erased_value != 0xff) {
1317  LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for MIPS32",
1318  erased_value);
1319  return ERROR_FAIL;
1320  }
1321  uint32_t isa = ejtag_info->isa ? 1 : 0;
1322  uint32_t erase_check_code[] = {
1323  /* nbyte: */
1324  MIPS32_LB(isa, 8, 0, 4), /* lb $t0, ($a0) */
1325  MIPS32_AND(isa, 6, 6, 8), /* and $a2, $a2, $t0 */
1326  MIPS32_ADDIU(isa, 5, 5, NEG16(1)), /* addiu $a1, $a1, -1 */
1327  MIPS32_BNE(isa, 5, 0, NEG16(4 << isa)), /* bne $a1, $zero, nbyte */
1328  MIPS32_ADDIU(isa, 4, 4, 1), /* addiu $a0, $a0, 1 */
1329  MIPS32_SDBBP(isa) /* sdbbp */
1330  };
1331 
1332  /* make sure we have a working area */
1333  if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
1334  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1335 
1336  pracc_swap16_array(ejtag_info, erase_check_code, ARRAY_SIZE(erase_check_code));
1337 
1338  /* convert erase check code into a buffer in target endianness */
1339  uint8_t erase_check_code_8[sizeof(erase_check_code)];
1340  target_buffer_set_u32_array(target, erase_check_code_8,
1341  ARRAY_SIZE(erase_check_code), erase_check_code);
1342 
1343  int retval = target_write_buffer(target, erase_check_algorithm->address,
1344  sizeof(erase_check_code), erase_check_code_8);
1345  if (retval != ERROR_OK)
1346  goto cleanup;
1347 
1348  mips32_info.common_magic = MIPS32_COMMON_MAGIC;
1349  mips32_info.isa_mode = isa ? MIPS32_ISA_MMIPS32 : MIPS32_ISA_MIPS32;
1350 
1351  init_reg_param(&reg_params[0], "r4", 32, PARAM_OUT);
1352  buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address);
1353 
1354  init_reg_param(&reg_params[1], "r5", 32, PARAM_OUT);
1355  buf_set_u32(reg_params[1].value, 0, 32, blocks[0].size);
1356 
1357  init_reg_param(&reg_params[2], "r6", 32, PARAM_IN_OUT);
1358  buf_set_u32(reg_params[2].value, 0, 32, erased_value);
1359 
1360  retval = target_run_algorithm(target, 0, NULL, 3, reg_params, erase_check_algorithm->address,
1361  erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &mips32_info);
1362 
1363  if (retval == ERROR_OK) {
1364  blocks[0].result = buf_get_u32(reg_params[2].value, 0, 32);
1365  *checked = 1; /* only one block has been checked */
1366  }
1367 
1368  destroy_reg_param(&reg_params[0]);
1369  destroy_reg_param(&reg_params[1]);
1370  destroy_reg_param(&reg_params[2]);
1371 
1372 cleanup:
1373  target_free_working_area(target, erase_check_algorithm);
1374 
1375  return retval;
1376 }
1377 
1378 static int mips32_verify_pointer(struct command_invocation *cmd,
1379  struct mips32_common *mips32)
1380 {
1381  if (mips32->common_magic != MIPS32_COMMON_MAGIC) {
1382  command_print(cmd, "target is not an MIPS32");
1383  return ERROR_TARGET_INVALID;
1384  }
1385  return ERROR_OK;
1386 }
1387 
1397 static int mips32_read_config_mmu(struct mips_ejtag *ejtag_info)
1398 {
1399  uint32_t config4, tlb_entries = 0, ways = 0, sets = 0;
1400  uint32_t config0 = ejtag_info->config[0];
1401  uint32_t config1 = ejtag_info->config[1];
1402  uint32_t config3 = ejtag_info->config[3];
1403  uint32_t mmu_type = (config0 >> 7) & 7;
1404  uint32_t vz_present = (config3 & BIT(23));
1405 
1406  int retval = mips32_cp0_read(ejtag_info, &config4, 16, 4);
1407  if (retval != ERROR_OK)
1408  return retval;
1409 
1410  /* mmu type = 1: VTLB only (Note: Does not account for Config4.ExtVTLB)
1411  * mmu type = 3: root RPU/Fixed (Note: Only valid with VZ ASE)
1412  * mmu type = 4: VTLB and FTLB
1413  */
1414  if ((mmu_type == 1 || mmu_type == 4) || (mmu_type == 3 && vz_present)) {
1415  tlb_entries = (uint32_t)(((config1 >> 25) & 0x3f) + 1);
1416  if (mmu_type == 4) {
1417  /* Release 6 definition for Config4[0:15] (MD01251, page 243) */
1418  /* The FTLB ways field is defined as [2, 3, 4, 5, 6, 7, 8, ...0 (reserved)] */
1419  int index = ((config4 >> 4) & 0xf);
1420  ways = index > 6 ? 0 : index + 2;
1421 
1422  /* The FTLB sets field is defined as [1, 2, 4, 8, ..., 16384, 32768] (powers of 2) */
1423  index = (config4 & 0xf);
1424  sets = 1 << index;
1425  tlb_entries = tlb_entries + (ways * sets);
1426  }
1427  }
1428  LOG_USER("TLB Entries: %d (%d ways, %d sets per way)", tlb_entries, ways, sets);
1429 
1430  return ERROR_OK;
1431 }
1432 
1444 static const struct mips32_cp0 *mips32_cp0_find_register_by_name(uint32_t cp0_mask, const char *reg_name)
1445 {
1446  if (reg_name)
1447  for (unsigned int i = 0; i < MIPS32NUMCP0REGS; i++) {
1448  if ((mips32_cp0_regs[i].core & cp0_mask) == 0)
1449  continue;
1450 
1451  if (strcmp(mips32_cp0_regs[i].name, reg_name) == 0)
1452  return &mips32_cp0_regs[i];
1453  }
1454  return NULL;
1455 }
1456 
1468 static int mips32_cp0_get_all_regs(struct command_invocation *cmd, struct mips_ejtag *ejtag_info, uint32_t cp0_mask)
1469 {
1470  uint32_t value;
1471 
1472  for (unsigned int i = 0; i < MIPS32NUMCP0REGS; i++) {
1473  /* Register name not valid for this core */
1474  if ((mips32_cp0_regs[i].core & cp0_mask) == 0)
1475  continue;
1476 
1477  int retval = mips32_cp0_read(ejtag_info, &value, mips32_cp0_regs[i].reg, mips32_cp0_regs[i].sel);
1478  if (retval != ERROR_OK) {
1479  command_print(CMD, "Error: couldn't access reg %s", mips32_cp0_regs[i].name);
1480  return retval;
1481  }
1482 
1483  command_print(CMD, "%*s: 0x%8.8" PRIx32, 14, mips32_cp0_regs[i].name, value);
1484  }
1485  return ERROR_OK;
1486 }
1487 
1499 static int mips32_cp0_get_reg_by_name(struct command_invocation *cmd, struct mips_ejtag *ejtag_info, uint32_t cp0_mask)
1500 {
1501  const struct mips32_cp0 *cp0_regs = mips32_cp0_find_register_by_name(cp0_mask, CMD_ARGV[0]);
1502  if (!cp0_regs) {
1503  command_print(CMD, "Error: Register '%s' not found", CMD_ARGV[0]);
1504  return ERROR_COMMAND_ARGUMENT_INVALID;
1505  }
1506 
1507  uint32_t value;
1508  int retval = mips32_cp0_read(ejtag_info, &value, cp0_regs->reg, cp0_regs->sel);
1509  if (retval != ERROR_OK) {
1510  command_print(CMD, "Error: Encounter an Error while reading cp0 reg %d sel %d",
1511  cp0_regs->reg, cp0_regs->sel);
1512  return retval;
1513  }
1514 
1515  command_print(CMD, "0x%8.8" PRIx32, value);
1516  return ERROR_OK;
1517 }
1518 
1529 static int mips32_cp0_get_reg_by_number(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
1530 {
1531  uint32_t cp0_reg, cp0_sel, value;
1532  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1533  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1534 
1535  int retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1536  if (retval != ERROR_OK) {
1537  command_print(CMD,
1538  "Error: couldn't access reg %" PRIu32,
1539  cp0_reg);
1540  return retval;
1541  }
1542 
1543  command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1544  cp0_reg, cp0_sel, value);
1545  return ERROR_OK;
1546 }
1547 
1559 static int mips32_cp0_set_reg_by_name(struct command_invocation *cmd,
1560  struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
1561 {
1562  const struct mips32_cp0 *cp0_regs = mips32_cp0_find_register_by_name(mips32->cp0_mask, CMD_ARGV[0]);
1563  if (!cp0_regs) {
1564  command_print(CMD, "Error: Register '%s' not found", CMD_ARGV[0]);
1565  return ERROR_COMMAND_ARGUMENT_INVALID;
1566  }
1567 
1568 
1569  uint32_t value;
1570  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1571 
1572  if (cp0_regs->reg == MIPS32_C0_STATUS && cp0_regs->sel == 0) {
1573  /* Update cached Status register if user is writing to Status */
1574  mips32->core_regs.cp0[MIPS32_REG_C0_STATUS_INDEX] = value;
1575  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_STATUS_INDEX].dirty = 1;
1576  } else if (cp0_regs->reg == MIPS32_C0_CAUSE && cp0_regs->sel == 0) {
1577  /* Update register cache with new value if its Cause */
1578  mips32->core_regs.cp0[MIPS32_REG_C0_CAUSE_INDEX] = value;
1579  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_CAUSE_INDEX].dirty = 1;
1580  } else if (cp0_regs->reg == MIPS32_C0_DEPC && cp0_regs->sel == 0) {
1581  /* Update cached PC if its DEPC */
1582  mips32->core_regs.cp0[MIPS32_REG_C0_PC_INDEX] = value;
1583  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = 1;
1584  } else if (cp0_regs->reg == MIPS32_C0_GUESTCTL1 && cp0_regs->sel == 4) {
1585  /* Update cached guestCtl1 */
1586  mips32->core_regs.cp0[MIPS32_REG_C0_GUESTCTL1_INDEX] = value;
1587  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_GUESTCTL1_INDEX].dirty = 1;
1588  }
1589 
1590  int retval = mips32_cp0_write(ejtag_info, value,
1591  cp0_regs->reg,
1592  cp0_regs->sel);
1593  if (retval != ERROR_OK) {
1594  command_print(CMD, "Error: Encounter an Error while writing to cp0 reg %d, sel %d",
1595  cp0_regs->reg, cp0_regs->sel);
1596  return retval;
1597  }
1598 
1599  command_print(CMD, "cp0 reg %s (%u, select %u: %8.8" PRIx32 ")",
1600  CMD_ARGV[0], cp0_regs->reg, cp0_regs->sel, value);
1601  return ERROR_OK;
1602 }
1603 
1615 static int mips32_cp0_set_reg_by_number(struct command_invocation *cmd,
1616  struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
1617 {
1618  uint32_t cp0_reg, cp0_sel, value;
1619  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1620  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1621  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1622 
1623  if (cp0_reg == MIPS32_C0_STATUS && cp0_sel == 0) {
1624  /* Update cached status register if user is writing to Status register */
1625  mips32->core_regs.cp0[MIPS32_REG_C0_STATUS_INDEX] = value;
1626  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_STATUS_INDEX].dirty = 1;
1627  } else if (cp0_reg == MIPS32_C0_CAUSE && cp0_sel == 0) {
1628  /* Update register cache with new value if its Cause register */
1629  mips32->core_regs.cp0[MIPS32_REG_C0_CAUSE_INDEX] = value;
1630  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_CAUSE_INDEX].dirty = 1;
1631  } else if (cp0_reg == MIPS32_C0_DEPC && cp0_sel == 0) {
1632  /* Update cached PC if its DEPC */
1633  mips32->core_regs.cp0[MIPS32_REG_C0_PC_INDEX] = value;
1634  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = 1;
1635  } else if (cp0_reg == MIPS32_C0_GUESTCTL1 && cp0_sel == 4) {
1636  /* Update cached guestCtl1, too */
1637  mips32->core_regs.cp0[MIPS32_REG_C0_GUESTCTL1_INDEX] = value;
1638  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_GUESTCTL1_INDEX].dirty = 1;
1639  }
1640 
1641  int retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1642  if (retval != ERROR_OK) {
1643  command_print(CMD,
1644  "Error: couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
1645  cp0_reg, cp0_sel);
1646  return retval;
1647  }
1648 
1649  command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1650  cp0_reg, cp0_sel, value);
1651  return ERROR_OK;
1652 }
1653 
1664 COMMAND_HANDLER(mips32_handle_cp0_command)
1665 {
1666  int retval, tmp;
1667  struct target *target = get_current_target(CMD_CTX);
1668  struct mips32_common *mips32 = target_to_mips32(target);
1669  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1670 
1671 
1672  retval = mips32_verify_pointer(CMD, mips32);
1673  if (retval != ERROR_OK)
1674  return retval;
1675 
1676  if (target->state != TARGET_HALTED) {
1677  command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME);
1678  return ERROR_TARGET_NOT_HALTED;
1679  }
1680 
1681  switch (CMD_ARGC) {
1682  case 0: /* No arg => print out all cp0 regs */
1683  retval = mips32_cp0_get_all_regs(CMD, ejtag_info, mips32->cp0_mask);
1684  break;
1685  case 1: /* 1 arg => get cp0 #reg/#sel value by name */
1686  retval = mips32_cp0_get_reg_by_name(CMD, ejtag_info, mips32->cp0_mask);
1687  break;
1688  case 2: /* 2 args => get cp0 reg/sel value or set value by name */
1689  tmp = *CMD_ARGV[0];
1690  if (isdigit(tmp)) /* starts from number then args are #reg and #sel */
1691  retval = mips32_cp0_get_reg_by_number(CMD, ejtag_info);
1692  else /* or set value by register name */
1693  retval = mips32_cp0_set_reg_by_name(CMD, mips32, ejtag_info);
1694  break;
1695  case 3: /* 3 args => set cp0 reg/sel value*/
1696  retval = mips32_cp0_set_reg_by_number(CMD, mips32, ejtag_info);
1697  break;
1698  default: /* Other argc => err */
1699  retval = ERROR_COMMAND_SYNTAX_ERROR;
1700  break;
1701  }
1702 
1703  return retval;
1704 }
1705 
1716 static void mips32_dsp_enable(struct pracc_queue_info *ctx, int isa)
1717 {
1718  /* Save Status Register */
1719  /* move status to $9 (t1) 2*/
1720  pracc_add(ctx, 0, MIPS32_MFC0(isa, 9, 12, 0));
1721 
1722  /* Read it again in order to modify it */
1723  /* move status to $0 (t0) 3*/
1724  pracc_add(ctx, 0, MIPS32_MFC0(isa, 8, 12, 0));
1725 
1726  /* Enable access to DSP registers by setting MX bit in status register */
1727  /* $15 = MIPS32_PRACC_STACK 4/5/6*/
1728  pracc_add(ctx, 0, MIPS32_LUI(isa, 15, UPPER16(MIPS32_DSP_ENABLE)));
1729  pracc_add(ctx, 0, MIPS32_ORI(isa, 15, 15, LOWER16(MIPS32_DSP_ENABLE)));
1730  pracc_add(ctx, 0, MIPS32_ISA_OR(8, 8, 15));
1731  /* Enable DSP - update status registers 7*/
1732  pracc_add(ctx, 0, MIPS32_MTC0(isa, 8, 12, 0));
1733 }
1734 
1745 static void mips32_dsp_restore(struct pracc_queue_info *ctx, int isa)
1746 {
1747  pracc_add(ctx, 0, MIPS32_MTC0(isa, 9, 12, 0)); /* Restore status registers to previous setting */
1748  pracc_add(ctx, 0, MIPS32_NOP); /* nop */
1749 }
1750 
1765 static int mips32_pracc_read_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t reg)
1766 {
1767  int isa = 0;
1768 
1769  struct pracc_queue_info ctx = {
1770  .max_code = 48,
1771  .ejtag_info = ejtag_info
1772  };
1773 
1774  uint32_t dsp_read_code[] = {
1775  MIPS32_DSP_MFHI(t0, 1), /* mfhi t0,$ac1 - OPCODE - 0x00204010 */
1776  MIPS32_DSP_MFLO(t0, 1), /* mflo t0,$ac1 - OPCODE - 0x00204012 */
1777  MIPS32_DSP_MFHI(t0, 2), /* mfhi t0,$ac2 - OPCODE - 0x00404010 */
1778  MIPS32_DSP_MFLO(t0, 2), /* mflo t0,$ac2 - OPCODE - 0x00404012 */
1779  MIPS32_DSP_MFHI(t0, 3), /* mfhi t0,$ac3 - OPCODE - 0x00604010*/
1780  MIPS32_DSP_MFLO(t0, 3), /* mflo t0,$ac3 - OPCODE - 0x00604012 */
1781  MIPS32_DSP_RDDSP(t0, 0x3F), /* rddsp t0, 0x3f (DSPCtl) - OPCODE - 0x7c3f44b8 */
1782  };
1783 
1784  /* Check status register to determine if dsp register access is enabled */
1785  /* Get status register so it can be restored later */
1786 
1787  ctx.pracc_list = NULL;
1788 
1789  /* Init context queue */
1790  pracc_queue_init(&ctx);
1791 
1792  if (ctx.retval != ERROR_OK)
1793  goto exit;
1794 
1795  /* Enables DSP whether its already enabled or not */
1796  mips32_dsp_enable(&ctx, isa);
1797 
1798  /* move AC or Control to $8 (t0) 8*/
1799  pracc_add(&ctx, 0, dsp_read_code[reg]);
1800  /* Restore status registers to previous setting */
1801  mips32_dsp_restore(&ctx, isa);
1802 
1803  /* $15 = MIPS32_PRACC_BASE_ADDR 1*/
1804  pracc_add(&ctx, 0, MIPS32_LUI(isa, 15, PRACC_UPPER_BASE_ADDR));
1805  /* store $8 to pracc_out 10*/
1806  pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, MIPS32_SW(isa, 8, PRACC_OUT_OFFSET, 15));
1807  /* move COP0 DeSave to $15 11*/
1808  pracc_add(&ctx, 0, MIPS32_MFC0(isa, 15, 31, 0));
1809  /* restore upper 16 of $8 12*/
1810  pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8)));
1811  /* restore lower 16 of $8 13*/
1812  pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(ejtag_info->reg8)));
1813  /* restore upper 16 of $9 14*/
1814  pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9)));
1815  pracc_add(&ctx, 0, MIPS32_SYNC(isa));
1816  /* jump to start 18*/
1817  pracc_add(&ctx, 0, MIPS32_B(isa, NEG16(ctx.code_count + 1)));
1818  /* restore lower 16 of $9 15*/
1819  pracc_add(&ctx, 0, MIPS32_ORI(isa, 9, 9, LOWER16(ejtag_info->reg9)));
1820 
1821  ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, val, 1);
1822 exit:
1823  pracc_queue_free(&ctx);
1824  return ctx.retval;
1825 }
1826 
1840 static int mips32_pracc_write_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t reg)
1841 {
1842  int isa = 0;
1843 
1844  struct pracc_queue_info ctx = {
1845  .max_code = 48,
1846  .ejtag_info = ejtag_info
1847  };
1848 
1849  uint32_t dsp_write_code[] = {
1850  MIPS32_DSP_MTHI(t0, 1), /* mthi t0, $ac1 - OPCODE - 0x01000811 */
1851  MIPS32_DSP_MTLO(t0, 1), /* mtlo t0, $ac1 - OPCODE - 0x01000813 */
1852  MIPS32_DSP_MTHI(t0, 2), /* mthi t0, $ac2 - OPCODE - 0x01001011 */
1853  MIPS32_DSP_MTLO(t0, 2), /* mtlo t0, $ac2 - OPCODE - 0x01001013 */
1854  MIPS32_DSP_MTHI(t0, 3), /* mthi t0, $ac3 - OPCODE - 0x01001811 */
1855  MIPS32_DSP_MTLO(t0, 3), /* mtlo t0, $ac3 - OPCODE - 0x01001813 */
1856  MIPS32_DSP_WRDSP(t0, 0x1F), /* wrdsp t0, 0x1f (DSPCtl) - OPCODE - 0x7d00fcf8*/
1857  };
1858 
1859  /* Init context queue */
1860  pracc_queue_init(&ctx);
1861  if (ctx.retval != ERROR_OK)
1862  goto exit;
1863 
1864  /* Enables DSP whether its already enabled or not */
1865  mips32_dsp_enable(&ctx, isa);
1866 
1867  /* Load val to $8 (t0) */
1868  pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(val)));
1869  pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(val)));
1870 
1871  /* move AC or Control to $8 (t0) */
1872  pracc_add(&ctx, 0, dsp_write_code[reg]);
1873 
1874  /* nop, delay in order to ensure write */
1875  pracc_add(&ctx, 0, MIPS32_NOP);
1876  /* Restore status registers to previous setting */
1877  mips32_dsp_restore(&ctx, isa);
1878 
1879  /* move COP0 DeSave to $15 */
1880  pracc_add(&ctx, 0, MIPS32_MFC0(isa, 15, 31, 0));
1881 
1882  /* restore $8 */
1883  pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8)));
1884  pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(ejtag_info->reg8)));
1885 
1886  /* restore upper 16 of $9 */
1887  pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9)));
1888 
1889  /* jump to start */
1890  pracc_add(&ctx, 0, MIPS32_B(isa, NEG16(ctx.code_count + 1)));
1891  /* restore lower 16 of $9 */
1892  pracc_add(&ctx, 0, MIPS32_ORI(isa, 9, 9, LOWER16(ejtag_info->reg9)));
1893 
1894  ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1);
1895 exit:
1896  pracc_queue_free(&ctx);
1897  return ctx.retval;
1898 }
1899 
1909 COMMAND_HANDLER(mips32_handle_cpuinfo_command)
1910 {
1911  int retval;
1912  struct target *target = get_current_target(CMD_CTX);
1913  struct mips32_common *mips32 = target_to_mips32(target);
1914  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1915 
1916  uint32_t prid = mips32->prid; /* cp0 PRID - 15, 0 */
1917  uint32_t config0 = ejtag_info->config[0]; /* cp0 config - 16, 0 */
1918  uint32_t config1 = ejtag_info->config[1]; /* cp0 config - 16, 1 */
1919  uint32_t config3 = ejtag_info->config[3]; /* cp0 config - 16, 3 */
1920 
1921  /* Following configs are not read during probe */
1922  uint32_t config5; /* cp0 config - 16, 5 */
1923 
1924  /* No args for now */
1925  if (CMD_ARGC != 0)
1926  return ERROR_COMMAND_SYNTAX_ERROR;
1927 
1928  if (target->state != TARGET_HALTED) {
1929  command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
1930  return ERROR_TARGET_NOT_HALTED;
1931  }
1932 
1933  retval = mips32_cp0_read(ejtag_info, &config5, 16, 5);
1934  if (retval != ERROR_OK)
1935  return retval;
1936 
1937  /* Determine Core info */
1938  const struct cpu_entry *entry = mips32->cpu_info;
1939  /* Display Core Type info */
1940  command_print(CMD, "CPU Core: %s", entry->cpu_name);
1941 
1942  /* Display Core Vendor ID if it's unknown */
1943  if (entry == &mips32_cpu_entry[MIPS32_NUM_CPU_ENTRIES - 1])
1944  command_print(CMD, "Vendor: Unknown CPU vendor code %x.", ((prid & 0x00ffff00) >> 16));
1945  else
1946  command_print(CMD, "Vendor: %s", entry->vendor);
1947 
1948  /* If MIPS release 2 or above, then get exception base info */
1949  enum mips32_isa_rel ar = mips32->isa_rel;
1950  if (ar > MIPS32_RELEASE_1) { /* release 2 and above */
1951  uint32_t ebase;
1952  retval = mips32_cp0_read(ejtag_info, &ebase, 15, 1);
1953  if (retval != ERROR_OK)
1954  return retval;
1955 
1956  command_print(CMD, "Current CPU ID: %d", (ebase & 0x1ff));
1957  } else {
1958  command_print(CMD, "Current CPU ID: 0");
1959  }
1960 
1961  char *instr;
1962  switch ((config3 & MIPS32_CONFIG3_ISA_MASK) >> MIPS32_CONFIG3_ISA_SHIFT) {
1963  case 0:
1964  instr = "MIPS32";
1965  break;
1966  case 1:
1967  instr = "microMIPS";
1968  break;
1969  case 2:
1970  instr = "MIPS32 (at reset) and microMIPS";
1971  break;
1972  case 3:
1973  default:
1974  instr = "microMIPS (at reset) and MIPS32";
1975  break;
1976  }
1977 
1978  /* Display Instruction Set Info */
1979  command_print(CMD, "Instr set: %s", instr);
1980  command_print(CMD, "Instr rel: %s",
1981  ar == MIPS32_RELEASE_1 ? "1"
1982  : ar == MIPS32_RELEASE_2 ? "2"
1983  : ar == MIPS32_RELEASE_6 ? "6"
1984  : "unknown");
1985  command_print(CMD, "PRId: %x", prid);
1986  /* Some of MIPS CPU Revisions(for M74K) can be seen on MD00541, page 26 */
1987  uint32_t rev = prid & 0x000000ff;
1988  command_print(CMD, "RTL Rev: %d.%d.%d", (rev & 0xE0), (rev & 0x1C), (rev & 0x3));
1989 
1990  command_print(CMD, "Max Number of Instr Breakpoints: %d", mips32->num_inst_bpoints);
1991  command_print(CMD, "Max Number of Data Breakpoints: %d", mips32->num_data_bpoints);
1992 
1993  /* MMU Support */
1994  uint32_t mmu_type = (config0 >> 7) & 7; /* MMU Type Info */
1995  char *mmu;
1996  switch (mmu_type) {
1997  case MIPS32_MMU_TLB:
1998  mmu = "TLB";
1999  break;
2000  case MIPS32_MMU_BAT:
2001  mmu = "BAT";
2002  break;
2003  case MIPS32_MMU_FIXED:
2004  mmu = "FIXED";
2005  break;
2006  case MIPS32_MMU_DUAL_VTLB_FTLB:
2007  mmu = "DUAL VAR/FIXED";
2008  break;
2009  default:
2010  mmu = "Unknown";
2011  }
2012  command_print(CMD, "MMU Type: %s", mmu);
2013 
2014  retval = mips32_read_config_mmu(ejtag_info);
2015  if (retval != ERROR_OK)
2016  return retval;
2017 
2018  /* Definitions of I/D Cache Sizes are available on MD01251, page 224~226 */
2019  int index;
2020  uint32_t ways, sets, bpl;
2021 
2022  /* Determine Instr Cache Size */
2023  /* Ways mapping = [1, 2, 3, 4, 5, 6, 7, 8] */
2024  ways = ((config1 >> MIPS32_CFG1_IASHIFT) & 7);
2025 
2026  /* Sets per way = [64, 128, 256, 512, 1024, 2048, 4096, 32] */
2027  index = ((config1 >> MIPS32_CFG1_ISSHIFT) & 7);
2028  sets = index == 7 ? 32 : 32 << (index + 1);
2029 
2030  /* Bytes per line = [0, 4, 8, 16, 32, 64, 128, Reserved] */
2031  index = ((config1 >> MIPS32_CFG1_ILSHIFT) & 7);
2032  bpl = index == 0 ? 0 : 4 << (index - 1);
2033  command_print(CMD, "Instr Cache: %d (%d ways, %d lines, %d byte per line)", ways * sets * bpl, ways, sets, bpl);
2034 
2035  /* Determine data cache size, same as above */
2036  ways = ((config1 >> MIPS32_CFG1_DASHIFT) & 7);
2037 
2038  index = ((config1 >> MIPS32_CFG1_DSSHIFT) & 7);
2039  sets = index == 7 ? 32 : 32 << (index + 1);
2040 
2041  index = ((config1 >> MIPS32_CFG1_DLSHIFT) & 7);
2042  bpl = index == 0 ? 0 : 4 << (index - 1);
2043  command_print(CMD, " Data Cache: %d (%d ways, %d lines, %d byte per line)", ways * sets * bpl, ways, sets, bpl);
2044 
2045  /* does the core hava FPU*/
2046  mips32_read_config_fpu(mips32, ejtag_info);
2047 
2048  /* does the core support a DSP */
2049  mips32_read_config_dsp(mips32, ejtag_info);
2050 
2051  /* VZ module */
2052  uint32_t vzase = (config3 & BIT(23));
2053  if (vzase)
2054  command_print(CMD, "VZ implemented: yes");
2055  else
2056  command_print(CMD, "VZ implemented: no");
2057 
2058  /* multithreading */
2059  uint32_t mtase = (config3 & BIT(2));
2060  if (mtase) {
2061  command_print(CMD, "MT implemented: yes");
2062 
2063  /* Get VPE and Thread info */
2064  uint32_t tcbind;
2065  uint32_t mvpconf0;
2066 
2067  /* Read tcbind register */
2068  retval = mips32_cp0_read(ejtag_info, &tcbind, 2, 2);
2069  if (retval != ERROR_OK)
2070  return retval;
2071 
2072  command_print(CMD, " | Current VPE: %d", (tcbind & 0xf));
2073  command_print(CMD, " | Current TC: %d", ((tcbind >> 21) & 0xff));
2074 
2075  /* Read mvpconf0 register */
2076  retval = mips32_cp0_read(ejtag_info, &mvpconf0, 0, 2);
2077  if (retval != ERROR_OK)
2078  return retval;
2079 
2080  command_print(CMD, " | Total TC: %d", (mvpconf0 & 0xf) + 1);
2081  command_print(CMD, " | Total VPE: %d", ((mvpconf0 >> 10) & 0xf) + 1);
2082  } else {
2083  command_print(CMD, "MT implemented: no");
2084  }
2085 
2086  /* MIPS SIMD Architecture (MSA) */
2087  uint32_t msa = (config3 & BIT(28));
2088  command_print(CMD, "MSA implemented: %s", msa ? "yes" : "no");
2089 
2090  /* Move To/From High COP0 (MTHC0/MFHC0) instructions are implemented.
2091  * Implicates current ISA release >= 5.*/
2092  uint32_t mvh = (config5 & BIT(5));
2093  command_print(CMD, "MVH implemented: %s", mvh ? "yes" : "no");
2094 
2095  /* Common Device Memory Map implemented? */
2096  uint32_t cdmm = (config3 & BIT(3));
2097  command_print(CMD, "CDMM implemented: %s", cdmm ? "yes" : "no");
2098 
2099  return ERROR_OK;
2100 }
2101 
2111 static int mips32_dsp_find_register_by_name(const char *reg_name)
2112 {
2113  if (reg_name)
2114  for (int i = 0; i < MIPS32NUMDSPREGS; i++) {
2115  if (strcmp(mips32_dsp_regs[i].name, reg_name) == 0)
2116  return i;
2117  }
2118  return MIPS32NUMDSPREGS;
2119 }
2120 
2131 static int mips32_dsp_get_all_regs(struct command_invocation *cmd, struct mips32_common *mips32)
2132 {
2133  uint32_t value = 0;
2134  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
2135  for (int i = 0; i < MIPS32NUMDSPREGS; i++) {
2136  int retval = mips32_pracc_read_dsp_reg(ejtag_info, &value, i);
2137  if (retval != ERROR_OK) {
2138  command_print(CMD, "couldn't access reg %s", mips32_dsp_regs[i].name);
2139  return retval;
2140  }
2141  mips32->core_regs.dsp[i] = value;
2142  mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + i].dirty = 1;
2143  command_print(CMD, "%*s: 0x%8.8x", 7, mips32_dsp_regs[i].name, value);
2144  }
2145  return ERROR_OK;
2146 }
2147 
2159 static int mips32_dsp_get_register(struct command_invocation *cmd, struct mips32_common *mips32)
2160 {
2161  uint32_t value = 0;
2162  int index = mips32_dsp_find_register_by_name(CMD_ARGV[0]);
2163  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
2164  if (index == MIPS32NUMDSPREGS) {
2165  command_print(CMD, "ERROR: register '%s' not found", CMD_ARGV[0]);
2166  return ERROR_COMMAND_SYNTAX_ERROR;
2167  }
2168 
2169  int retval = mips32_pracc_read_dsp_reg(ejtag_info, &value, index);
2170  if (retval != ERROR_OK) {
2171  command_print(CMD, "ERROR: Could not access dsp register %s", CMD_ARGV[0]);
2172  return retval;
2173  }
2174 
2175  command_print(CMD, "0x%8.8x", value);
2176 
2177  if (mips32->core_regs.dsp[index] != value) {
2178  mips32->core_regs.dsp[index] = value;
2179  mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty = 1;
2180  }
2181 
2182  return retval;
2183 }
2184 
2197 static int mips32_dsp_set_register(struct command_invocation *cmd, struct mips32_common *mips32)
2198 {
2199  uint32_t value;
2200  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
2201  int index = mips32_dsp_find_register_by_name(CMD_ARGV[0]);
2202  if (index == MIPS32NUMDSPREGS) {
2203  command_print(CMD, "ERROR: register '%s' not found", CMD_ARGV[0]);
2204  return ERROR_COMMAND_SYNTAX_ERROR;
2205  }
2206 
2207  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2208 
2209  int retval = mips32_pracc_write_dsp_reg(ejtag_info, value, index);
2210  if (retval != ERROR_OK) {
2211  command_print(CMD, "Error: could not write to dsp register %s", CMD_ARGV[0]);
2212  return retval;
2213  }
2214 
2215  mips32->core_regs.dsp[index] = value;
2216  mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty = 1;
2217 
2218  return retval;
2219 }
2220 
2229 COMMAND_HANDLER(mips32_handle_dsp_command)
2230 {
2231  int retval, tmp;
2232  struct target *target = get_current_target(CMD_CTX);
2233  struct mips32_common *mips32 = target_to_mips32(target);
2234 
2235  retval = mips32_verify_pointer(CMD, mips32);
2236  if (retval != ERROR_OK)
2237  return retval;
2238 
2239  if (target->state != TARGET_HALTED) {
2240  command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2241  return ERROR_OK;
2242  }
2243 
2244  /* Check for too many command args */
2245  if (CMD_ARGC >= 3)
2246  return ERROR_COMMAND_SYNTAX_ERROR;
2247 
2248  /* Check if DSP access supported or not */
2249  if (!mips32->dsp_imp) {
2250  /* Issue Error Message */
2251  command_print(CMD, "DSP not implemented by this processor");
2252  return ERROR_OK;
2253  }
2254 
2255  switch (CMD_ARGC) {
2256  case 0:
2257  retval = mips32_dsp_get_all_regs(CMD, mips32);
2258  break;
2259  case 1:
2260  retval = mips32_dsp_get_register(CMD, mips32);
2261  break;
2262  case 2:
2263  tmp = *CMD_ARGV[0];
2264  if (isdigit(tmp)) {
2265  command_print(CMD, "Error: invalid dsp command format");
2266  retval = ERROR_COMMAND_ARGUMENT_INVALID;
2267  } else {
2268  retval = mips32_dsp_set_register(CMD, mips32);
2269  }
2270  break;
2271  default:
2272  command_print(CMD, "Error: invalid argument format, required 0-2, given %d", CMD_ARGC);
2273  retval = ERROR_COMMAND_ARGUMENT_INVALID;
2274  break;
2275  }
2276  return retval;
2277 }
2278 
2287 COMMAND_HANDLER(mips32_handle_ejtag_reg_command)
2288 {
2289  struct target *target = get_current_target(CMD_CTX);
2290  struct mips32_common *mips32 = target_to_mips32(target);
2291  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
2292 
2293  uint32_t ejtag_ctrl;
2294  uint32_t dcr;
2295  int retval;
2296 
2297  retval = mips_ejtag_get_idcode(ejtag_info);
2298  if (retval != ERROR_OK)
2299  command_print(CMD, "Error: Encounter an Error while getting idcode");
2300  else
2301  command_print(CMD, " idcode: 0x%8.8" PRIx32, ejtag_info->idcode);
2302 
2303  retval = mips_ejtag_get_impcode(ejtag_info);
2304  if (retval != ERROR_OK)
2305  command_print(CMD, "Error: Encounter an Error while getting impcode");
2306  else
2307  command_print(CMD, " impcode: 0x%8.8" PRIx32, ejtag_info->impcode);
2308 
2309  mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
2310  ejtag_ctrl = ejtag_info->ejtag_ctrl;
2311  retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
2312  if (retval != ERROR_OK)
2313  command_print(CMD, "Error: Encounter an Error while executing drscan reading EJTAG Control register");
2314  else
2315  command_print(CMD, "ejtag control: 0x%8.8" PRIx32, ejtag_ctrl);
2316 
2317  ejtag_main_print_imp(ejtag_info);
2318 
2319  /* Display current DCR */
2320  retval = target_read_u32(target, EJTAG_DCR, &dcr);
2321  if (retval != ERROR_OK)
2322  command_print(CMD, "Error: Encounter an Error while reading Debug Control Register");
2323  else
2324  command_print(CMD, " DCR: 0x%8.8" PRIx32, dcr);
2325 
2326  for (unsigned int i = 0; i < EJTAG_DCR_ENTRIES; i++) {
2327  if (dcr & BIT(dcr_features[i].bit))
2328  command_print(CMD, "%s supported", dcr_features[i].name);
2329  }
2330 
2331  return ERROR_OK;
2332 }
2333 
2342 COMMAND_HANDLER(mips32_handle_scan_delay_command)
2343 {
2344  struct target *target = get_current_target(CMD_CTX);
2345  struct mips32_common *mips32 = target_to_mips32(target);
2346  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
2347 
2348  if (CMD_ARGC == 1)
2349  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
2350  else if (CMD_ARGC > 1)
2351  return ERROR_COMMAND_SYNTAX_ERROR;
2352 
2353  command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
2354  if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
2355  ejtag_info->mode = 0;
2356  command_print(CMD, "running in legacy mode");
2357  } else {
2358  ejtag_info->mode = 1;
2359  command_print(CMD, "running in fast queued mode");
2360  }
2361 
2362  return ERROR_OK;
2363 }
2364 
2365 static const struct command_registration mips32_exec_command_handlers[] = {
2366  {
2367  .name = "cp0",
2368  .handler = mips32_handle_cp0_command,
2369  .mode = COMMAND_EXEC,
2370  .usage = "[[reg_name|regnum select] [value]]",
2371  .help = "display/modify cp0 register",
2372  },
2373  {
2374  .name = "cpuinfo",
2375  .handler = mips32_handle_cpuinfo_command,
2376  .mode = COMMAND_EXEC,
2377  .help = "display CPU information",
2378  .usage = "",
2379  },
2380  {
2381  .name = "dsp",
2382  .handler = mips32_handle_dsp_command,
2383  .mode = COMMAND_EXEC,
2384  .help = "display or set DSP register; "
2385  "with no arguments, displays all registers and their values",
2386  .usage = "[[register_name] [value]]",
2387  },
2388  {
2389  .name = "scan_delay",
2390  .handler = mips32_handle_scan_delay_command,
2391  .mode = COMMAND_ANY,
2392  .help = "display/set scan delay in nano seconds",
2393  .usage = "[value]",
2394  },
2395  {
2396  .name = "ejtag_reg",
2397  .handler = mips32_handle_ejtag_reg_command,
2398  .mode = COMMAND_ANY,
2399  .help = "read ejtag registers",
2400  .usage = "",
2401  },
2402  COMMAND_REGISTRATION_DONE
2403 };
2404 
2405 const struct command_registration mips32_command_handlers[] = {
2406  {
2407  .name = "mips32",
2408  .mode = COMMAND_ANY,
2409  .help = "mips32 command group",
2410  .usage = "",
2411  .chain = mips32_exec_command_handlers,
2412  },
2413  COMMAND_REGISTRATION_DONE
2414 };
init_reg_param
void init_reg_param(struct reg_param *param, const char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
destroy_reg_param
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:38
PARAM_OUT
@ PARAM_OUT
Definition: algorithm.h:16
PARAM_IN
@ PARAM_IN
Definition: algorithm.h:15
PARAM_IN_OUT
@ PARAM_IN_OUT
Definition: algorithm.h:17
buf_get_u32
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:104
buf_set_u32
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
buf_get_u64
static uint64_t buf_get_u64(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 64-bit word.
Definition: binarybuffer.h:134
buf_set_u64
static void buf_set_u64(uint8_t *_buffer, unsigned int first, unsigned int num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:65
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:389
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:146
CMD_NAME
#define CMD_NAME
Use this macro to access the name of the command being handled, rather than accessing the variable di...
Definition: command.h:171
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:161
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:405
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:156
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:445
CMD_CTX
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:151
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:256
ERROR_COMMAND_ARGUMENT_INVALID
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:407
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
address
uint32_t address
Starting address. Sector aligned.
Definition: dw-spi-helper.h:0
direction
static uint16_t direction
Definition: ftdi.c:157
LOG_USER
#define LOG_USER(expr ...)
Definition: log.h:150
LOG_WARNING
#define LOG_WARNING(expr ...)
Definition: log.h:144
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:188
LOG_TARGET_ERROR
#define LOG_TARGET_ERROR(target, fmt_str,...)
Definition: log.h:176
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:147
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:124
ERROR_OK
#define ERROR_OK
Definition: log.h:182
mips32_build_reg_cache
struct reg_cache * mips32_build_reg_cache(struct target *target)
Definition: mips32.c:498
mips32_cpu_support_sync
bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info)
mips32_cpu_support_sync - Checks CPU supports ordering
Definition: mips32.c:956
mips32_read_config_mmu
static int mips32_read_config_mmu(struct mips_ejtag *ejtag_info)
mips32_read_config_mmu - Reads MMU configuration and logs relevant information.
Definition: mips32.c:1397
mips32_command_handlers
const struct command_registration mips32_command_handlers[]
Definition: mips32.c:2405
mips32_blank_check_memory
int mips32_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, unsigned int num_blocks, uint8_t erased_value, unsigned int *checked)
Checks whether a memory region is erased.
Definition: mips32.c:1305
mips32_read_config_regs
int mips32_read_config_regs(struct target *target)
Definition: mips32.c:1148
mips32_dsp_regs
static const struct @116 mips32_dsp_regs[MIPS32NUMDSPREGS]
mips32_checksum_memory
int mips32_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Definition: mips32.c:1222
mips32_set_core_reg
static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
Definition: mips32.c:251
mips32_read_config_dsp
static void mips32_read_config_dsp(struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
Definition: mips32.c:1044
mips32_pracc_read_dsp_reg
static int mips32_pracc_read_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t reg)
mips32_pracc_read_dsp_reg - Read a value from a MIPS32 DSP register
Definition: mips32.c:1765
t0
#define t0
Definition: mips32.c:192
mips32_dsp_restore
static void mips32_dsp_restore(struct pracc_queue_info *ctx, int isa)
mips32_dsp_restore - Restore DSP status registers to the previous setting
Definition: mips32.c:1745
mips32_cp0_get_reg_by_number
static int mips32_cp0_get_reg_by_number(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
mips32_cp0_get_reg_by_number - Read and print a CP0 register's value by number.
Definition: mips32.c:1529
size
int size
Definition: mips32.c:42
mips32_cp0_get_all_regs
static int mips32_cp0_get_all_regs(struct command_invocation *cmd, struct mips_ejtag *ejtag_info, uint32_t cp0_mask)
mips32_cp0_get_all_regs - Print all CP0 registers and their values.
Definition: mips32.c:1468
mips32_dsp_get_register
static int mips32_dsp_get_register(struct command_invocation *cmd, struct mips32_common *mips32)
mips32_dsp_get_register - Get the value of a MIPS32 DSP register
Definition: mips32.c:2159
mips32_configure_break_unit
int mips32_configure_break_unit(struct target *target)
Definition: mips32.c:797
mips32_get_core_reg
static int mips32_get_core_reg(struct reg *reg)
Definition: mips32.c:239
mips32_arch_state
int mips32_arch_state(struct target *target)
Definition: mips32.c:481
COMMAND_HANDLER
COMMAND_HANDLER(mips32_handle_cp0_command)
mips32_handle_cp0_command - Handle commands related to CP0 registers.
Definition: mips32.c:1664
group
const char * group
Definition: mips32.c:40
mips32_cp0_set_reg_by_number
static int mips32_cp0_set_reg_by_number(struct command_invocation *cmd, struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
mips32_cp0_set_reg_by_number - Write to a CP0 register identified by number.
Definition: mips32.c:1615
mips32_cpu_probe
int mips32_cpu_probe(struct target *target)
mips32_cpu_probe - Detects processor type and applies necessary quirks.
Definition: mips32.c:988
mips32_run_algorithm
int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Definition: mips32.c:613
MIPS32_NUM_REGS
#define MIPS32_NUM_REGS
Definition: mips32.c:177
mips32_read_config_fpu
static int mips32_read_config_fpu(struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
Definition: mips32.c:1066
MIPS32_GDB_FP_REG
#define MIPS32_GDB_FP_REG
Definition: mips32.c:30
mips32_dsp_get_all_regs
static int mips32_dsp_get_all_regs(struct command_invocation *cmd, struct mips32_common *mips32)
mips32_dsp_get_all_regs - Get values of all MIPS32 DSP registers
Definition: mips32.c:2131
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static int mips32_configure_ibs(struct target *target)
Definition: mips32.c:745
mips32_examine
int mips32_examine(struct target *target)
Definition: mips32.c:729
mips32_read_config_fdc
static void mips32_read_config_fdc(struct mips32_common *mips32, struct mips_ejtag *ejtag_info, uint32_t dcr)
mips32_read_config_fdc - Read Fast Debug Channel configuration
Definition: mips32.c:1136
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int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
Definition: mips32.c:557
mips32_reg_type
static const struct reg_arch_type mips32_reg_type
Definition: mips32.c:493
mips32_configure_dbs
static int mips32_configure_dbs(struct target *target)
Definition: mips32.c:771
name
const char * name
Definition: mips32.c:38
mips32_cpu_support_hazard_barrier
bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info)
mips32_cpu_support_hazard_barrier - Checks CPU supports hazard barrier
Definition: mips32.c:969
mips32_pracc_write_dsp_reg
static int mips32_pracc_write_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t reg)
mips32_pracc_write_dsp_reg - Write a value to a MIPS32 DSP register
Definition: mips32.c:1840
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static int mips32_read_c0_prid(struct target *target)
Definition: mips32.c:888
mips32_dsp_enable
static void mips32_dsp_enable(struct pracc_queue_info *ctx, int isa)
mips32_dsp_enable - Enable access to DSP registers
Definition: mips32.c:1716
mips32_cp0_find_register_by_name
static const struct mips32_cp0 * mips32_cp0_find_register_by_name(uint32_t cp0_mask, const char *reg_name)
mips32_cp0_find_register_by_name - Find CP0 register by its name.
Definition: mips32.c:1444
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static int mips32_write_core_reg(struct target *target, unsigned int num)
Definition: mips32.c:379
mips32_set_all_fpr_width
static void mips32_set_all_fpr_width(struct mips32_common *mips32, bool fp64)
mips32_set_all_fpr_width - Set the width of all floating-point registers
Definition: mips32.c:283
type
enum reg_type type
Definition: mips32.c:39
mips32_read_core_reg
static int mips32_read_core_reg(struct target *target, unsigned int num)
Definition: mips32.c:331
mips32_run_and_wait
static int mips32_run_and_wait(struct target *target, target_addr_t entry_point, unsigned int timeout_ms, target_addr_t exit_point, struct mips32_common *mips32)
Definition: mips32.c:581
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int mips32_save_context(struct target *target)
Definition: mips32.c:443
id
unsigned int id
Definition: mips32.c:37
mips32_dsp_set_register
static int mips32_dsp_set_register(struct command_invocation *cmd, struct mips32_common *mips32)
mips32_dsp_set_register - Set the value of a MIPS32 DSP register
Definition: mips32.c:2197
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int mips32_enable_interrupts(struct target *target, int enable)
Definition: mips32.c:853
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static const char * mips_isa_strings[]
Definition: mips32.c:26
mips32_find_cpu_by_prid
static const struct cpu_entry * mips32_find_cpu_by_prid(uint32_t prid)
mips32_find_cpu_by_prid - Find CPU information by processor ID.
Definition: mips32.c:913
mips32_detect_fpr_mode_change
static void mips32_detect_fpr_mode_change(struct mips32_common *mips32, uint32_t cp0_status)
mips32_detect_fpr_mode_change - Detect changes in floating-point register mode
Definition: mips32.c:304
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static int mips32_cp0_set_reg_by_name(struct command_invocation *cmd, struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
mips32_cp0_set_reg_by_name - Write to a CP0 register identified by name.
Definition: mips32.c:1559
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static int mips32_dsp_find_register_by_name(const char *reg_name)
mips32_dsp_find_register_by_name - Find DSP register index by name
Definition: mips32.c:2111
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static bool mips32_cpu_is_lexra(struct mips_ejtag *ejtag_info)
Definition: mips32.c:936
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int mips32_restore_context(struct target *target)
Definition: mips32.c:465
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static int mips32_verify_pointer(struct command_invocation *cmd, struct mips32_common *mips32)
Definition: mips32.c:1378
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static const struct @115 mips32_regs[]
mips32_cp0_get_reg_by_name
static int mips32_cp0_get_reg_by_name(struct command_invocation *cmd, struct mips_ejtag *ejtag_info, uint32_t cp0_mask)
mips32_cp0_get_reg_by_name - Read and print a CP0 register's value by name.
Definition: mips32.c:1499
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int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: mips32.c:426
feature
const char * feature
Definition: mips32.c:41
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static int mips32_cpu_get_release(struct mips_ejtag *ejtag_info)
Definition: mips32.c:941
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static const struct command_registration mips32_exec_command_handlers[]
Definition: mips32.c:2365
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#define MIPS32_CONFIG3_DSPP_MASK
Definition: mips32.h:59
MIPS32_CONFIG3_DSPREV_SHIFT
#define MIPS32_CONFIG3_DSPREV_SHIFT
Definition: mips32.h:61
MIPS32_CONFIG3_DSPP_SHIFT
#define MIPS32_CONFIG3_DSPP_SHIFT
Definition: mips32.h:58
MIPS32_NOP
#define MIPS32_NOP
Definition: mips32.h:719
MIPS32_C0_CAUSE
#define MIPS32_C0_CAUSE
Definition: mips32.h:860
MIPS32_SCAN_DELAY_LEGACY_MODE
#define MIPS32_SCAN_DELAY_LEGACY_MODE
Definition: mips32.h:70
MIPS32_REGLIST_DSP_DSPCTL_INDEX
#define MIPS32_REGLIST_DSP_DSPCTL_INDEX
Definition: mips32.h:245
MIPS32_CORE_MASK
#define MIPS32_CORE_MASK
Definition: mips32.h:282
MIPS32_ISA_OR
#define MIPS32_ISA_OR(dst, src, val)
Definition: mips32.h:561
MIPS32_CONFIG3_DSPREV_MASK
#define MIPS32_CONFIG3_DSPREV_MASK
Definition: mips32.h:62
MIPS32_REGLIST_FP_INDEX
#define MIPS32_REGLIST_FP_INDEX
Definition: mips32.h:228
MIPS32_CONFIG3_CDMM_MASK
#define MIPS32_CONFIG3_CDMM_MASK
Definition: mips32.h:56
MIPS32_ADDI
#define MIPS32_ADDI(isa, tar, src, val)
Definition: mips32.h:720
MIPS32_SYNC
#define MIPS32_SYNC(isa)
Definition: mips32.h:772
MIPS32_REG_C0_PC_INDEX
#define MIPS32_REG_C0_PC_INDEX
Definition: mips32.h:242
MIPS32_CONFIG3_ISA_MASK
#define MIPS32_CONFIG3_ISA_MASK
Definition: mips32.h:65
MIPS32_REGLIST_C0_STATUS_INDEX
#define MIPS32_REGLIST_C0_STATUS_INDEX
Definition: mips32.h:233
MIPS32_DSP_MTLO
#define MIPS32_DSP_MTLO(reg, ac)
Definition: mips32.h:799
target_to_mips32
static struct mips32_common * target_to_mips32(struct target *target)
Definition: mips32.h:444
MIPS32_XOR
#define MIPS32_XOR(isa, reg, val1, val2)
Definition: mips32.h:773
EJTAG_QUIRK_PAD_DRET
#define EJTAG_QUIRK_PAD_DRET
Definition: mips32.h:209
MIPS32_DSP_ENABLE
#define MIPS32_DSP_ENABLE
Definition: mips32.h:787
MIPS32_COMMON_MAGIC
#define MIPS32_COMMON_MAGIC
Definition: mips32.h:21
MIPS32_NUM_CPU_ENTRIES
#define MIPS32_NUM_CPU_ENTRIES
Definition: mips32.h:362
MIPS32_CFG1_ILSHIFT
#define MIPS32_CFG1_ILSHIFT
Definition: mips32.h:814
MIPS32_SDBBP
#define MIPS32_SDBBP(isa)
Definition: mips32.h:780
MIPS_CP0_MK4
#define MIPS_CP0_MK4
Definition: mips32.h:75
MIPS32_FP_IMP_64
@ MIPS32_FP_IMP_64
Definition: mips32.h:367
MIPS32_FP_IMP_NONE
@ MIPS32_FP_IMP_NONE
Definition: mips32.h:365
MIPS32_FP_IMP_UNKNOWN
@ MIPS32_FP_IMP_UNKNOWN
Definition: mips32.h:368
MIPS32_CFG1_DASHIFT
#define MIPS32_CFG1_DASHIFT
Definition: mips32.h:822
MIPS32_LB
#define MIPS32_LB(isa, reg, off, base)
Definition: mips32.h:736
MIPS32_CP0_STATUS_CU1_SHIFT
#define MIPS32_CP0_STATUS_CU1_SHIFT
Definition: mips32.h:83
MIPS32_REG_C0_GUESTCTL1_INDEX
#define MIPS32_REG_C0_GUESTCTL1_INDEX
Definition: mips32.h:243
MIPS32_REGLIST_C0_CAUSE_INDEX
#define MIPS32_REGLIST_C0_CAUSE_INDEX
Definition: mips32.h:235
MIPS32_CONFIG0_AR_SHIFT
#define MIPS32_CONFIG0_AR_SHIFT
Definition: mips32.h:46
MIPS32_CONFIG1_FP_SHIFT
#define MIPS32_CONFIG1_FP_SHIFT
Definition: mips32.h:49
MIPS32_BNE
#define MIPS32_BNE(isa, src, tar, off)
Definition: mips32.h:729
MIPS32_REG_C0_CAUSE_INDEX
#define MIPS32_REG_C0_CAUSE_INDEX
Definition: mips32.h:241
MIPS32_REG_FP_COUNT
#define MIPS32_REG_FP_COUNT
Definition: mips32.h:222
MIPS_CP0_IAPTIV
#define MIPS_CP0_IAPTIV
Definition: mips32.h:78
MIPS32_BEQ
#define MIPS32_BEQ(isa, src, tar, off)
Definition: mips32.h:727
MIPS32_CP1_FIR_F64_SHIFT
#define MIPS32_CP1_FIR_F64_SHIFT
Definition: mips32.h:86
MIPS32_C0_DEPC
#define MIPS32_C0_DEPC
Definition: mips32.h:874
MIPS_CP0_MAPTIV_UP
#define MIPS_CP0_MAPTIV_UP
Definition: mips32.h:77
MIPS32_REGLIST_DSP_INDEX
#define MIPS32_REGLIST_DSP_INDEX
Definition: mips32.h:231
MIPS32_REGLIST_C0_GUESTCTL1_INDEX
#define MIPS32_REGLIST_C0_GUESTCTL1_INDEX
Definition: mips32.h:237
MIPS32_CONFIG3_ISA_SHIFT
#define MIPS32_CONFIG3_ISA_SHIFT
Definition: mips32.h:64
MIPS32_SW
#define MIPS32_SW(isa, reg, off, base)
Definition: mips32.h:760
MIPS32_MOVN
#define MIPS32_MOVN(isa, dst, src, tar)
Definition: mips32.h:755
MIPS32_REGLIST_C0_PC_INDEX
#define MIPS32_REGLIST_C0_PC_INDEX
Definition: mips32.h:236
MIPS32_C0_STATUS
#define MIPS32_C0_STATUS
Definition: mips32.h:855
MIPS32_REGLIST_FPC_INDEX
#define MIPS32_REGLIST_FPC_INDEX
Definition: mips32.h:229
MIPS32NUMDSPREGS
#define MIPS32NUMDSPREGS
Definition: mips32.h:72
MIPS32_MMU_TLB
#define MIPS32_MMU_TLB
Definition: mips32.h:895
MIPS32_CFG1_ISSHIFT
#define MIPS32_CFG1_ISSHIFT
Definition: mips32.h:812
MIPS32_REGLIST_GP_INDEX
#define MIPS32_REGLIST_GP_INDEX
Definition: mips32.h:227
MIPS32_ADDU
#define MIPS32_ADDU(isa, dst, src, tar)
Definition: mips32.h:722
MMIPS32_ONLY
@ MMIPS32_ONLY
Definition: mips32.h:257
MIPS32_MMIPS32
@ MIPS32_MMIPS32
Definition: mips32.h:259
MIPS32_MIPS16
@ MIPS32_MIPS16
Definition: mips32.h:258
MIPS32_ONLY
@ MIPS32_ONLY
Definition: mips32.h:256
MIPS32_CFG1_DSSHIFT
#define MIPS32_CFG1_DSSHIFT
Definition: mips32.h:818
MIPS32_REG_C0_STATUS_INDEX
#define MIPS32_REG_C0_STATUS_INDEX
Definition: mips32.h:239
MIPS32_MTC0
#define MIPS32_MTC0(isa, gpr, cpr, sel)
Definition: mips32.h:744
MIPS32_ADDIU
#define MIPS32_ADDIU(isa, tar, src, val)
Definition: mips32.h:721
MIPS32_LUI
#define MIPS32_LUI(isa, reg, val)
Definition: mips32.h:741
MIPS_CP0_MAPTIV_UC
#define MIPS_CP0_MAPTIV_UC
Definition: mips32.h:76
MIPS32_C0_GUESTCTL1
#define MIPS32_C0_GUESTCTL1
Definition: mips32.h:853
MIPS32_MMU_DUAL_VTLB_FTLB
#define MIPS32_MMU_DUAL_VTLB_FTLB
Definition: mips32.h:898
MIPS32_CONFIG0_AR_MASK
#define MIPS32_CONFIG0_AR_MASK
Definition: mips32.h:47
MIPS32_CFG1_DLSHIFT
#define MIPS32_CFG1_DLSHIFT
Definition: mips32.h:820
MIPS32_MMU_FIXED
#define MIPS32_MMU_FIXED
Definition: mips32.h:897
MIPS32_AND
#define MIPS32_AND(isa, dst, src, tar)
Definition: mips32.h:723
MIPS32_DSP_MFHI
#define MIPS32_DSP_MFHI(reg, ac)
Definition: mips32.h:797
MIPS32_REGLIST_C0_BADVADDR_INDEX
#define MIPS32_REGLIST_C0_BADVADDR_INDEX
Definition: mips32.h:234
MIPS32_DSP_MTHI
#define MIPS32_DSP_MTHI(reg, ac)
Definition: mips32.h:800
mips32_isa_mode
mips32_isa_mode
Definition: mips32.h:249
MIPS32_ISA_MMIPS32
@ MIPS32_ISA_MMIPS32
Definition: mips32.h:252
MIPS32_ISA_MIPS32
@ MIPS32_ISA_MIPS32
Definition: mips32.h:250
MIPS32_DSP_MFLO
#define MIPS32_DSP_MFLO(reg, ac)
Definition: mips32.h:798
MIPS32_ORI
#define MIPS32_ORI(isa, tar, src, val)
Definition: mips32.h:756
MIPS32_SLL
#define MIPS32_SLL(isa, dst, src, sa)
Definition: mips32.h:764
MIPS32_MFC0
#define MIPS32_MFC0(isa, gpr, cpr, sel)
Definition: mips32.h:743
MIPS32_CP0_STATUS_MX_SHIFT
#define MIPS32_CP0_STATUS_MX_SHIFT
Definition: mips32.h:81
MIPS32_CFG1_IASHIFT
#define MIPS32_CFG1_IASHIFT
Definition: mips32.h:816
mips32_isa_rel
mips32_isa_rel
Definition: mips32.h:267
MIPS32_RELEASE_1
@ MIPS32_RELEASE_1
Definition: mips32.h:268
MIPS32_RELEASE_6
@ MIPS32_RELEASE_6
Definition: mips32.h:270
MIPS32_RELEASE_2
@ MIPS32_RELEASE_2
Definition: mips32.h:269
MIPS32_REGLIST_C0_INDEX
#define MIPS32_REGLIST_C0_INDEX
Definition: mips32.h:230
mips32_cp0_regs
static const struct mips32_cp0 mips32_cp0_regs[]
mips32_cpu_entry
static const struct cpu_entry mips32_cpu_entry[]
MIPS32_B
#define MIPS32_B(isa, off)
Definition: mips32.h:726
MIPS32_MMU_BAT
#define MIPS32_MMU_BAT
Definition: mips32.h:896
MIPS32_SLTI
#define MIPS32_SLTI(isa, tar, src, val)
Definition: mips32.h:767
MIPS32_CONFIG1_FP_MASK
#define MIPS32_CONFIG1_FP_MASK
Definition: mips32.h:50
MIPS32_CP0_STATUS_FR_SHIFT
#define MIPS32_CP0_STATUS_FR_SHIFT
Definition: mips32.h:82
MIPS32_DSP_WRDSP
#define MIPS32_DSP_WRDSP(rs, mask)
Definition: mips32.h:802
MIPS32NUMCP0REGS
#define MIPS32NUMCP0REGS
Definition: mips32.h:206
MIPS32_DSP_RDDSP
#define MIPS32_DSP_RDDSP(rt, mask)
Definition: mips32.h:801
pracc_queue_free
void pracc_queue_free(struct pracc_queue_info *ctx)
Definition: mips32_pracc.c:339
mips32_pracc_write_regs
int mips32_pracc_write_regs(struct mips32_common *mips32)
Definition: mips32_pracc.c:873
mips32_pracc_queue_exec
int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *buf, bool check_last)
Definition: mips32_pracc.c:344
mips32_pracc_read_regs
int mips32_pracc_read_regs(struct mips32_common *mips32)
Definition: mips32_pracc.c:1087
pracc_queue_init
void pracc_queue_init(struct pracc_queue_info *ctx)
Definition: mips32_pracc.c:297
mips32_cp0_read
int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel)
mips32_cp0_read
Definition: mips32_pracc.c:552
pracc_add
void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr)
Definition: mips32_pracc.c:307
mips32_cp1_control_read
int mips32_cp1_control_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp1_c_reg)
mips32_cp1_control_read
Definition: mips32_pracc.c:591
mips32_cp0_write
int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
mips32_cp0_write
Definition: mips32_pracc.c:573
PRACC_UPPER_BASE_ADDR
#define PRACC_UPPER_BASE_ADDR
Definition: mips32_pracc.h:25
PRACC_OUT_OFFSET
#define PRACC_OUT_OFFSET
Definition: mips32_pracc.h:28
LOWER16
#define LOWER16(addr)
Definition: mips32_pracc.h:32
pracc_swap16_array
static void pracc_swap16_array(struct mips_ejtag *ejtag_info, uint32_t *buf, int count)
Definition: mips32_pracc.h:121
UPPER16
#define UPPER16(addr)
Definition: mips32_pracc.h:31
MIPS32_PRACC_PARAM_OUT
#define MIPS32_PRACC_PARAM_OUT
Definition: mips32_pracc.h:23
NEG16
#define NEG16(v)
Definition: mips32_pracc.h:33
mips_cpu.h
PRID_IMP_MASK
#define PRID_IMP_MASK
Definition: mips_cpu.h:28
PRID_COMP_MASK
#define PRID_COMP_MASK
Definition: mips_cpu.h:13
PRID_COMP_LEXRA
#define PRID_COMP_LEXRA
Definition: mips_cpu.h:19
PRID_COMP_MTI
#define PRID_COMP_MTI
Definition: mips_cpu.h:16
PRID_IMP_MAPTIV_UP
#define PRID_IMP_MAPTIV_UP
Definition: mips_cpu.h:31
PRID_COMP_ALCHEMY
#define PRID_COMP_ALCHEMY
Definition: mips_cpu.h:18
PRID_IMP_M5150
#define PRID_IMP_M5150
Definition: mips_cpu.h:34
PRID_IMP_IAPTIV_CM
#define PRID_IMP_IAPTIV_CM
Definition: mips_cpu.h:32
PRID_COMP_INGENIC_E1
#define PRID_COMP_INGENIC_E1
Definition: mips_cpu.h:21
PRID_IMP_XBURST_REV1
#define PRID_IMP_XBURST_REV1
Definition: mips_cpu.h:36
PRID_IMP_IAPTIV
#define PRID_IMP_IAPTIV
Definition: mips_cpu.h:33
PRID_IMP_MAPTIV_UC
#define PRID_IMP_MAPTIV_UC
Definition: mips_cpu.h:30
mips_ejtag_get_idcode
int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:42
mips_ejtag_set_instr
void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr)
Definition: mips_ejtag.c:22
mips_ejtag_get_impcode
int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:50
mips_ejtag_drscan_32
int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
Definition: mips_ejtag.c:130
ejtag_main_print_imp
void ejtag_main_print_imp(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:335
EJTAG_DCR_ENTRIES
#define EJTAG_DCR_ENTRIES
Definition: mips_ejtag.h:203
EJTAG_V20_IMP_NODB
#define EJTAG_V20_IMP_NODB
Definition: mips_ejtag.h:117
EJTAG_VERSION_20
#define EJTAG_VERSION_20
Definition: mips_ejtag.h:168
EJTAG_INST_CONTROL
#define EJTAG_INST_CONTROL
Definition: mips_ejtag.h:20
EJTAG_V20_IMP_NOIB
#define EJTAG_V20_IMP_NOIB
Definition: mips_ejtag.h:118
EJTAG_DCR_FDC
#define EJTAG_DCR_FDC
Definition: mips_ejtag.h:127
EJTAG_DCR_IB
#define EJTAG_DCR_IB
Definition: mips_ejtag.h:129
EJTAG_DCR_DB
#define EJTAG_DCR_DB
Definition: mips_ejtag.h:128
EJTAG_DCR_ENM
#define EJTAG_DCR_ENM
Definition: mips_ejtag.h:126
EJTAG_IMP_MIPS16
#define EJTAG_IMP_MIPS16
Definition: mips_ejtag.h:112
dcr_features
static const struct dcr_feature dcr_features[]
EJTAG_DCR
#define EJTAG_DCR
Definition: mips_ejtag.h:125
EJTAG_DCR_INTE
#define EJTAG_DCR_INTE
Definition: mips_ejtag.h:130
bit
static uint32_t bit(uint32_t value, unsigned int b)
Definition: opcodes.h:39
register_get_by_name
struct reg * register_get_by_name(struct reg_cache *first, const char *name, bool search_all)
Definition: register.c:50
register_get_last_cache_p
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
Definition: register.c:72
reg_type
reg_type
Definition: register.h:19
REG_TYPE_INT
@ REG_TYPE_INT
Definition: register.h:21
REG_TYPE_IEEE_DOUBLE
@ REG_TYPE_IEEE_DOUBLE
Definition: register.h:37
REG_TYPE_IEEE_SINGLE
@ REG_TYPE_IEEE_SINGLE
Definition: register.h:36
target
struct target * target
Definition: rtt/rtt.c:26
BIT
#define BIT(nr)
Definition: stm32l4x.h:18
command_invocation
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
command_registration
Definition: command.h:238
command_registration::name
const char * name
Definition: command.h:239
cpu_entry
Definition: mips32.h:293
cpu_entry::vendor
const char * vendor
Definition: mips32.h:296
cpu_entry::cpu_name
const char * cpu_name
Definition: mips32.h:297
cpu_entry::prid
uint32_t prid
Definition: mips32.h:294
jtag_tap
Definition: jtag.h:101
mem_param
Definition: algorithm.h:20
mips32_algorithm
Definition: mips32.h:455
mips32_algorithm::isa_mode
enum mips32_isa_mode isa_mode
Definition: mips32.h:457
mips32_algorithm::common_magic
unsigned int common_magic
Definition: mips32.h:456
mips32_common
Definition: mips32.h:391
mips32_common::bp_scanned
int bp_scanned
Definition: mips32.h:430
mips32_common::dsp_imp
enum mips32_dsp_imp dsp_imp
Definition: mips32.h:404
mips32_common::fp_imp
enum mips32_fp_imp fp_imp
Definition: mips32.h:403
mips32_common::write_core_reg
int(* write_core_reg)(struct target *target, unsigned int num)
Definition: mips32.h:440
mips32_common::semihosting
int semihosting
Definition: mips32.h:407
mips32_common::common_magic
unsigned int common_magic
Definition: mips32.h:392
mips32_common::cpu_quirks
uint32_t cpu_quirks
Definition: mips32.h:425
mips32_common::num_data_bpoints
int num_data_bpoints
Definition: mips32.h:432
mips32_common::fpu_in_64bit
bool fpu_in_64bit
Definition: mips32.h:418
mips32_common::data_break_list
struct mips32_comparator * data_break_list
Definition: mips32.h:436
mips32_common::inst_break_list
struct mips32_comparator * inst_break_list
Definition: mips32.h:435
mips32_common::ejtag_info
struct mips_ejtag ejtag_info
Definition: mips32.h:396
mips32_common::fast_data_area
struct working_area * fast_data_area
Definition: mips32.h:428
mips32_common::core_regs
struct mips32_core_regs core_regs
Definition: mips32.h:398
mips32_common::num_data_bpoints_avail
int num_data_bpoints_avail
Definition: mips32.h:434
mips32_common::num_inst_bpoints
int num_inst_bpoints
Definition: mips32.h:431
mips32_common::prid
uint32_t prid
Definition: mips32.h:421
mips32_common::fpu_enabled
bool fpu_enabled
Definition: mips32.h:416
mips32_common::cp0_mask
uint32_t cp0_mask
Definition: mips32.h:413
mips32_common::read_core_reg
int(* read_core_reg)(struct target *target, unsigned int num)
Definition: mips32.h:439
mips32_common::isa_imp
enum mips32_isa_imp isa_imp
Definition: mips32.h:401
mips32_common::isa_mode
enum mips32_isa_mode isa_mode
Definition: mips32.h:400
mips32_common::isa_rel
enum mips32_isa_rel isa_rel
Definition: mips32.h:402
mips32_common::fdc
int fdc
Definition: mips32.h:406
mips32_common::core_cache
struct reg_cache * core_cache
Definition: mips32.h:395
mips32_common::num_inst_bpoints_avail
int num_inst_bpoints_avail
Definition: mips32.h:433
mips32_common::cpu_info
const struct cpu_entry * cpu_info
Definition: mips32.h:423
mips32_comparator
Definition: mips32.h:377
mips32_comparator::reg_address
uint32_t reg_address
Definition: mips32.h:380
mips32_core_reg
Definition: mips32.h:449
mips32_core_reg::target
struct target * target
Definition: mips32.h:451
mips32_core_reg::mips32_common
struct mips32_common * mips32_common
Definition: mips32.h:452
mips32_core_reg::num
uint32_t num
Definition: mips32.h:450
mips32_core_regs::fpr
uint64_t fpr[MIPS32_REG_FP_COUNT]
Definition: mips32.h:385
mips32_core_regs::gpr
uint32_t gpr[MIPS32_REG_GP_COUNT]
Definition: mips32.h:384
mips32_core_regs::cp0
uint32_t cp0[MIPS32_REG_C0_COUNT]
Definition: mips32.h:387
mips32_core_regs::dsp
uint32_t dsp[MIPS32_REG_DSP_COUNT]
Definition: mips32.h:388
mips32_core_regs::fpcr
uint32_t fpcr[MIPS32_REG_FPC_COUNT]
Definition: mips32.h:386
mips32_cp0
Definition: mips32.h:88
mips32_cp0::sel
unsigned int sel
Definition: mips32.h:90
mips32_cp0::reg
unsigned int reg
Definition: mips32.h:89
mips32_cp0::core
const unsigned int core
Definition: mips32.h:92
mips_ejtag
Definition: mips_ejtag.h:205
mips_ejtag::prid
uint32_t prid
Definition: mips_ejtag.h:209
mips_ejtag::ejtag_ctrl
uint32_t ejtag_ctrl
Definition: mips_ejtag.h:210
mips_ejtag::scan_delay
unsigned int scan_delay
Definition: mips_ejtag.h:217
mips_ejtag::idcode
uint32_t idcode
Definition: mips_ejtag.h:208
mips_ejtag::reg9
uint32_t reg9
Definition: mips_ejtag.h:216
mips_ejtag::config
uint32_t config[4]
Definition: mips_ejtag.h:213
mips_ejtag::ejtag_version
unsigned int ejtag_version
Definition: mips_ejtag.h:221
mips_ejtag::impcode
uint32_t impcode
Definition: mips_ejtag.h:207
mips_ejtag::ejtag_iba0_addr
uint32_t ejtag_iba0_addr
Definition: mips_ejtag.h:229
mips_ejtag::ejtag_iba_step_size
uint32_t ejtag_iba_step_size
Definition: mips_ejtag.h:241
mips_ejtag::endianness
uint32_t endianness
Definition: mips_ejtag.h:223
mips_ejtag::tap
struct jtag_tap * tap
Definition: mips_ejtag.h:206
mips_ejtag::ejtag_dba_step_size
uint32_t ejtag_dba_step_size
Definition: mips_ejtag.h:242
mips_ejtag::reg8
uint32_t reg8
Definition: mips_ejtag.h:215
mips_ejtag::ejtag_ibs_addr
uint32_t ejtag_ibs_addr
Definition: mips_ejtag.h:228
mips_ejtag::config_regs
uint32_t config_regs
Definition: mips_ejtag.h:212
mips_ejtag::ejtag_dbs_addr
uint32_t ejtag_dbs_addr
Definition: mips_ejtag.h:234
mips_ejtag::mode
int mode
Definition: mips_ejtag.h:218
mips_ejtag::ejtag_dba0_addr
uint32_t ejtag_dba0_addr
Definition: mips_ejtag.h:235
mips_ejtag::debug_caps
uint32_t debug_caps
Definition: mips_ejtag.h:227
mips_ejtag::isa
uint32_t isa
Definition: mips_ejtag.h:222
pracc_queue_info
Definition: mips32_pracc.h:46
pracc_queue_info::code_count
int code_count
Definition: mips32_pracc.h:50
pracc_queue_info::pracc_list
struct pa_list * pracc_list
Definition: mips32_pracc.h:53
pracc_queue_info::retval
int retval
Definition: mips32_pracc.h:49
pracc_queue_info::max_code
int max_code
Definition: mips32_pracc.h:52
pracc_queue_info::isa
unsigned int isa
Definition: mips32_pracc.h:48
pracc_queue_info::ejtag_info
struct mips_ejtag * ejtag_info
Definition: mips32_pracc.h:47
reg_arch_type
Definition: register.h:151
reg_arch_type::get
int(* get)(struct reg *reg)
Definition: register.h:152
reg_cache
Definition: register.h:144
reg_cache::name
const char * name
Definition: register.h:145
reg_cache::num_regs
unsigned int num_regs
Definition: register.h:148
reg_cache::reg_list
struct reg * reg_list
Definition: register.h:147
reg_cache::next
struct reg_cache * next
Definition: register.h:146
reg_data_type
Definition: register.h:99
reg_data_type::type
enum reg_type type
Definition: register.h:100
reg_feature
Definition: register.h:41
reg_param
Definition: algorithm.h:27
reg_param::size
uint32_t size
Definition: algorithm.h:29
reg_param::reg_name
const char * reg_name
Definition: algorithm.h:28
reg
Definition: register.h:111
reg::caller_save
bool caller_save
Definition: register.h:119
reg::valid
bool valid
Definition: register.h:126
reg::exist
bool exist
Definition: register.h:128
reg::size
uint32_t size
Definition: register.h:132
reg::group
const char * group
Definition: register.h:138
reg::value
uint8_t * value
Definition: register.h:122
reg::feature
struct reg_feature * feature
Definition: register.h:117
reg::reg_data_type
struct reg_data_type * reg_data_type
Definition: register.h:135
reg::number
uint32_t number
Definition: register.h:115
reg::arch_info
void * arch_info
Definition: register.h:140
reg::dirty
bool dirty
Definition: register.h:124
reg::type
const struct reg_arch_type * type
Definition: register.h:141
reg::name
const char * name
Definition: register.h:113
target_memory_check_block
Definition: target.h:346
target_memory_check_block::result
uint32_t result
Definition: target.h:349
target
Definition: target.h:119
target::state
enum target_state state
Definition: target.h:167
target::endianness
enum target_endianness endianness
Definition: target.h:165
target::reg_cache
struct reg_cache * reg_cache
Definition: target.h:168
target::arch_info
void * arch_info
Definition: target.h:174
timeout
Definition: psoc6.c:83
working_area
Definition: target.h:88
working_area::address
target_addr_t address
Definition: target.h:89
target_halt
int target_halt(struct target *target)
Definition: target.c:517
target_write_buffer
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2369
target_read_buffer
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Definition: target.c:2434
target_run_algorithm
int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Downloads a target-specific native code algorithm to the target, and executes it.
Definition: target.c:786
target_alloc_working_area
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2090
target_write_u32
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2635
target_free_working_area
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2148
target_resume
int target_resume(struct target *target, bool current, target_addr_t address, bool handle_breakpoints, bool debug_execution)
Make the target (re)start executing using its saved execution context (possibly with some modificatio...
Definition: target.c:566
target_read_u32
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2561
debug_reason_name
const char * debug_reason_name(const struct target *t)
Definition: target.c:257
target_wait_state
int target_wait_state(struct target *target, enum target_state state, unsigned int ms)
Definition: target.c:3167
get_current_target
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:468
target_buffer_set_u32_array
void target_buffer_set_u32_array(struct target *target, uint8_t *buffer, uint32_t count, const uint32_t *srcbuf)
Definition: target.c:427
target_register_class
target_register_class
Definition: target.h:113
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:817
target_was_examined
static bool target_was_examined(const struct target *target)
Definition: target.h:443
ERROR_TARGET_INVALID
#define ERROR_TARGET_INVALID
Definition: target.h:814
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:58
TARGET_BIG_ENDIAN
@ TARGET_BIG_ENDIAN
Definition: target.h:85
TARGET_LITTLE_ENDIAN
@ TARGET_LITTLE_ENDIAN
Definition: target.h:85
ERROR_TARGET_TIMEOUT
#define ERROR_TARGET_TIMEOUT
Definition: target.h:816
ERROR_TARGET_RESOURCE_NOT_AVAILABLE
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:821
ARRAY_SIZE
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
target_addr_t
uint64_t target_addr_t
Definition: types.h:279
NULL
#define NULL
Definition: usb.h:16
cmd
uint8_t cmd
Definition: vdebug.c:1
count
uint8_t count[4]
Definition: vdebug.c:22