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aarch64.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2015 by David Ung *
5  * *
6  ***************************************************************************/
7 
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11 
12 #include "breakpoints.h"
13 #include "aarch64.h"
14 #include "register.h"
15 #include "target_request.h"
16 #include "target_type.h"
17 #include "armv8_opcodes.h"
18 #include "armv8_cache.h"
19 #include "arm_coresight.h"
20 #include "arm_semihosting.h"
21 #include "jtag/interface.h"
22 #include "smp.h"
23 #include <helper/nvp.h>
24 #include <helper/time_support.h>
25 
26 enum restart_mode {
27  RESTART_LAZY,
28  RESTART_SYNC,
29 };
30 
31 enum halt_mode {
32  HALT_LAZY,
33  HALT_SYNC,
34 };
35 
36 struct aarch64_private_config {
37  struct adiv5_private_config adiv5_config;
38  struct arm_cti *cti;
39 };
40 
41 static int aarch64_poll_smp(struct target *target, bool smp,
42  bool postpone_event);
43 static int aarch64_debug_entry(struct target *target);
44 static int aarch64_restore_context(struct target *target, bool bpwp);
45 static int aarch64_set_breakpoint(struct target *target,
46  struct breakpoint *breakpoint, uint8_t matchmode);
47 static int aarch64_set_context_breakpoint(struct target *target,
48  struct breakpoint *breakpoint, uint8_t matchmode);
49 static int aarch64_set_hybrid_breakpoint(struct target *target,
50  struct breakpoint *breakpoint);
51 static int aarch64_unset_breakpoint(struct target *target,
52  struct breakpoint *breakpoint);
53 static int aarch64_mmu(struct target *target, bool *enabled);
54 static int aarch64_virt2phys(struct target *target,
55  target_addr_t virt, target_addr_t *phys);
56 static int aarch64_read_cpu_memory(struct target *target,
57  uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer);
58 
59 static int aarch64_restore_system_control_reg(struct target *target)
60 {
61  enum arm_mode target_mode = ARM_MODE_ANY;
62  int retval = ERROR_OK;
63  uint32_t instr;
64 
65  struct aarch64_common *aarch64 = target_to_aarch64(target);
66  struct armv8_common *armv8 = target_to_armv8(target);
67 
68  if (aarch64->system_control_reg != aarch64->system_control_reg_curr) {
69  aarch64->system_control_reg_curr = aarch64->system_control_reg;
70  /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_v8->cp15_control_reg); */
71 
72  switch (armv8->arm.core_mode) {
73  case ARMV8_64_EL0T:
74  target_mode = ARMV8_64_EL1H;
75  /* fall through */
76  case ARMV8_64_EL1T:
77  case ARMV8_64_EL1H:
78  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL1, 0);
79  break;
80  case ARMV8_64_EL2T:
81  case ARMV8_64_EL2H:
82  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL2, 0);
83  break;
84  case ARMV8_64_EL3H:
85  case ARMV8_64_EL3T:
86  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0);
87  break;
88 
89  case ARM_MODE_SVC:
90  case ARM_MODE_ABT:
91  case ARM_MODE_FIQ:
92  case ARM_MODE_IRQ:
93  case ARM_MODE_HYP:
94  case ARM_MODE_UND:
95  case ARM_MODE_SYS:
96  case ARM_MODE_MON:
97  instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
98  break;
99 
100  default:
101  LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)",
102  armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
103  return ERROR_FAIL;
104  }
105 
106  if (target_mode != ARM_MODE_ANY)
107  armv8_dpm_modeswitch(&armv8->dpm, target_mode);
108 
109  retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg);
110  if (retval != ERROR_OK)
111  return retval;
112 
113  if (target_mode != ARM_MODE_ANY)
114  armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
115  }
116 
117  return retval;
118 }
119 
120 /* modify system_control_reg in order to enable or disable mmu for :
121  * - virt2phys address conversion
122  * - read or write memory in phys or virt address */
123 static int aarch64_mmu_modify(struct target *target, int enable)
124 {
125  struct aarch64_common *aarch64 = target_to_aarch64(target);
126  struct armv8_common *armv8 = &aarch64->armv8_common;
127  int retval = ERROR_OK;
128  enum arm_mode target_mode = ARM_MODE_ANY;
129  uint32_t instr = 0;
130 
131  if (enable) {
132  /* if mmu enabled at target stop and mmu not enable */
133  if (!(aarch64->system_control_reg & 0x1U)) {
134  LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
135  return ERROR_FAIL;
136  }
137  if (!(aarch64->system_control_reg_curr & 0x1U))
138  aarch64->system_control_reg_curr |= 0x1U;
139  } else {
140  if (aarch64->system_control_reg_curr & 0x4U) {
141  /* data cache is active */
142  aarch64->system_control_reg_curr &= ~0x4U;
143  /* flush data cache armv8 function to be called */
144  if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache)
145  armv8->armv8_mmu.armv8_cache.flush_all_data_cache(target);
146  }
147  if ((aarch64->system_control_reg_curr & 0x1U)) {
148  aarch64->system_control_reg_curr &= ~0x1U;
149  }
150  }
151 
152  switch (armv8->arm.core_mode) {
153  case ARMV8_64_EL0T:
154  target_mode = ARMV8_64_EL1H;
155  /* fall through */
156  case ARMV8_64_EL1T:
157  case ARMV8_64_EL1H:
158  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL1, 0);
159  break;
160  case ARMV8_64_EL2T:
161  case ARMV8_64_EL2H:
162  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL2, 0);
163  break;
164  case ARMV8_64_EL3H:
165  case ARMV8_64_EL3T:
166  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0);
167  break;
168 
169  case ARM_MODE_SVC:
170  case ARM_MODE_ABT:
171  case ARM_MODE_FIQ:
172  case ARM_MODE_IRQ:
173  case ARM_MODE_HYP:
174  case ARM_MODE_UND:
175  case ARM_MODE_SYS:
176  case ARM_MODE_MON:
177  instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
178  break;
179 
180  default:
181  LOG_DEBUG("unknown cpu state 0x%x", armv8->arm.core_mode);
182  break;
183  }
184  if (target_mode != ARM_MODE_ANY)
185  armv8_dpm_modeswitch(&armv8->dpm, target_mode);
186 
187  retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr,
188  aarch64->system_control_reg_curr);
189 
190  if (target_mode != ARM_MODE_ANY)
191  armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
192 
193  return retval;
194 }
195 
196 static int aarch64_read_prsr(struct target *target, uint32_t *prsr)
197 {
198  struct armv8_common *armv8 = target_to_armv8(target);
199  int retval;
200 
201  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
202  armv8->debug_base + CPUV8_DBG_PRSR, prsr);
203  if (retval != ERROR_OK)
204  return retval;
205 
206  armv8->sticky_reset |= *prsr & PRSR_SR;
207  return ERROR_OK;
208 }
209 
210 /*
211  * Basic debug access, very low level assumes state is saved
212  */
213 static int aarch64_init_debug_access(struct target *target)
214 {
215  struct armv8_common *armv8 = target_to_armv8(target);
216  int retval;
217  uint32_t dummy;
218  uint32_t lsr;
219 
220  LOG_DEBUG("%s", target_name(target));
221 
222  /* while the LAR shouldn't even be visible on the external debugger
223  * interface, this unlock is needed on at least NXP's LX2160A
224  */
225  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
226  armv8->debug_base + ARM_CS_LAR, ARM_CS_LAR_UNLOCK_KEY);
227  if (retval != ERROR_OK) {
228  LOG_WARNING("debug unit unlock write failed - register may not be implemented");
229  } else {
230  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
231  armv8->debug_base + ARM_CS_LSR, &lsr);
232  if (retval != ERROR_OK)
233  LOG_WARNING("debug unit unlock write OK but status read failed.");
234  else if ((lsr & (ARM_CS_LSR_SLI | ARM_CS_LSR_SLK))
235  == (ARM_CS_LSR_SLI | ARM_CS_LSR_SLK))
236  /* try to continue anyway, at least read accesses still work */
237  LOG_WARNING("debug unit locked, may cause further failures.");
238  }
239 
240  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
241  armv8->debug_base + CPUV8_DBG_OSLAR, 0);
242  if (retval != ERROR_OK) {
243  LOG_DEBUG("Examine %s failed", "oslock");
244  return retval;
245  }
246 
247  /* Clear Sticky Power Down status Bit in PRSR to enable access to
248  the registers in the Core Power Domain */
249  retval = aarch64_read_prsr(target, &dummy);
250  if (retval != ERROR_OK)
251  return retval;
252 
253  /*
254  * Static CTI configuration:
255  * Channel 0 -> trigger outputs HALT request to PE
256  * Channel 1 -> trigger outputs Resume request to PE
257  * Gate all channel trigger events from entering the CTM
258  */
259 
260  /* Enable CTI */
261  retval = arm_cti_enable(armv8->cti, true);
262  /* By default, gate all channel events to and from the CTM */
263  if (retval == ERROR_OK)
264  retval = arm_cti_write_reg(armv8->cti, CTI_GATE, 0);
265  /* output halt requests to PE on channel 0 event */
266  if (retval == ERROR_OK)
267  retval = arm_cti_write_reg(armv8->cti, CTI_OUTEN0, CTI_CHNL(0));
268  /* output restart requests to PE on channel 1 event */
269  if (retval == ERROR_OK)
270  retval = arm_cti_write_reg(armv8->cti, CTI_OUTEN1, CTI_CHNL(1));
271  if (retval != ERROR_OK)
272  return retval;
273 
274  /* Resync breakpoint registers */
275 
276  return ERROR_OK;
277 }
278 
279 /* Write to memory mapped registers directly with no cache or mmu handling */
280 static int aarch64_dap_write_memap_register_u32(struct target *target,
281  target_addr_t address,
282  uint32_t value)
283 {
284  struct armv8_common *armv8 = target_to_armv8(target);
285 
286  return mem_ap_write_atomic_u32(armv8->debug_ap, address, value);
287 }
288 
289 static int aarch64_dpm_setup(struct aarch64_common *a8, uint64_t debug)
290 {
291  struct arm_dpm *dpm = &a8->armv8_common.dpm;
292  int retval;
293 
294  dpm->arm = &a8->armv8_common.arm;
295  dpm->didr = debug;
296 
297  retval = armv8_dpm_setup(dpm);
298  if (retval == ERROR_OK)
299  retval = armv8_dpm_initialize(dpm);
300 
301  return retval;
302 }
303 
304 static int aarch64_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
305 {
306  struct armv8_common *armv8 = target_to_armv8(target);
307  return armv8_set_dbgreg_bits(armv8, CPUV8_DBG_DSCR, bit_mask, value);
308 }
309 
310 static int aarch64_check_state_one(struct target *target,
311  uint32_t mask, uint32_t val, int *p_result, uint32_t *p_prsr)
312 {
313  uint32_t prsr;
314  int retval;
315 
316  retval = aarch64_read_prsr(target, &prsr);
317  if (retval != ERROR_OK)
318  return retval;
319 
320  if (p_prsr)
321  *p_prsr = prsr;
322 
323  if (p_result)
324  *p_result = (prsr & mask) == (val & mask);
325 
326  return ERROR_OK;
327 }
328 
329 static int aarch64_wait_halt_one(struct target *target)
330 {
331  int retval = ERROR_OK;
332  uint32_t prsr;
333 
334  int64_t then = timeval_ms();
335  for (;;) {
336  int halted;
337 
338  retval = aarch64_check_state_one(target, PRSR_HALT, PRSR_HALT, &halted, &prsr);
339  if (retval != ERROR_OK || halted)
340  break;
341 
342  if (timeval_ms() > then + 1000) {
343  retval = ERROR_TARGET_TIMEOUT;
344  LOG_DEBUG("target %s timeout, prsr=0x%08"PRIx32, target_name(target), prsr);
345  break;
346  }
347  }
348  return retval;
349 }
350 
351 static int aarch64_prepare_halt_smp(struct target *target, bool exc_target, struct target **p_first)
352 {
353  int retval = ERROR_OK;
354  struct target_list *head;
355  struct target *first = NULL;
356 
357  LOG_DEBUG("target %s exc %i", target_name(target), exc_target);
358 
359  foreach_smp_target(head, target->smp_targets) {
360  struct target *curr = head->target;
361  struct armv8_common *armv8 = target_to_armv8(curr);
362 
363  if (exc_target && curr == target)
364  continue;
365  if (!target_was_examined(curr))
366  continue;
367  if (curr->state != TARGET_RUNNING)
368  continue;
369 
370  /* HACK: mark this target as prepared for halting */
371  curr->debug_reason = DBG_REASON_DBGRQ;
372 
373  /* open the gate for channel 0 to let HALT requests pass to the CTM */
374  retval = arm_cti_ungate_channel(armv8->cti, 0);
375  if (retval == ERROR_OK)
376  retval = aarch64_set_dscr_bits(curr, DSCR_HDE, DSCR_HDE);
377  if (retval != ERROR_OK)
378  break;
379 
380  LOG_DEBUG("target %s prepared", target_name(curr));
381 
382  if (!first)
383  first = curr;
384  }
385 
386  if (p_first) {
387  if (exc_target && first)
388  *p_first = first;
389  else
390  *p_first = target;
391  }
392 
393  return retval;
394 }
395 
396 static int aarch64_halt_one(struct target *target, enum halt_mode mode)
397 {
398  int retval = ERROR_OK;
399  struct armv8_common *armv8 = target_to_armv8(target);
400 
401  LOG_DEBUG("%s", target_name(target));
402 
403  /* allow Halting Debug Mode */
404  retval = aarch64_set_dscr_bits(target, DSCR_HDE, DSCR_HDE);
405  if (retval != ERROR_OK)
406  return retval;
407 
408  /* trigger an event on channel 0, this outputs a halt request to the PE */
409  retval = arm_cti_pulse_channel(armv8->cti, 0);
410  if (retval != ERROR_OK)
411  return retval;
412 
413  if (mode == HALT_SYNC) {
414  retval = aarch64_wait_halt_one(target);
415  if (retval != ERROR_OK) {
416  if (retval == ERROR_TARGET_TIMEOUT)
417  LOG_ERROR("Timeout waiting for target %s halt", target_name(target));
418  return retval;
419  }
420  }
421 
422  return ERROR_OK;
423 }
424 
425 static int aarch64_halt_smp(struct target *target, bool exc_target)
426 {
427  struct target *next = target;
428  int retval;
429 
430  /* prepare halt on all PEs of the group */
431  retval = aarch64_prepare_halt_smp(target, exc_target, &next);
432 
433  if (exc_target && next == target)
434  return retval;
435 
436  /* halt the target PE */
437  if (retval == ERROR_OK)
438  retval = aarch64_halt_one(next, HALT_LAZY);
439 
440  if (retval != ERROR_OK)
441  return retval;
442 
443  /* wait for all PEs to halt */
444  int64_t then = timeval_ms();
445  for (;;) {
446  bool all_halted = true;
447  struct target_list *head;
448  struct target *curr;
449 
450  foreach_smp_target(head, target->smp_targets) {
451  int halted;
452 
453  curr = head->target;
454 
455  if (!target_was_examined(curr))
456  continue;
457 
458  retval = aarch64_check_state_one(curr, PRSR_HALT, PRSR_HALT, &halted, NULL);
459  if (retval != ERROR_OK || !halted) {
460  all_halted = false;
461  break;
462  }
463  }
464 
465  if (all_halted)
466  break;
467 
468  if (timeval_ms() > then + 1000) {
469  retval = ERROR_TARGET_TIMEOUT;
470  break;
471  }
472 
473  /*
474  * HACK: on Hi6220 there are 8 cores organized in 2 clusters
475  * and it looks like the CTI's are not connected by a common
476  * trigger matrix. It seems that we need to halt one core in each
477  * cluster explicitly. So if we find that a core has not halted
478  * yet, we trigger an explicit halt for the second cluster.
479  */
480  retval = aarch64_halt_one(curr, HALT_LAZY);
481  if (retval != ERROR_OK)
482  break;
483  }
484 
485  return retval;
486 }
487 
488 static int aarch64_update_halt_gdb(struct target *target, enum target_debug_reason debug_reason)
489 {
490  struct target_list *head;
491  struct target *curr;
492 
493  if (debug_reason == DBG_REASON_NOTHALTED) {
494  LOG_DEBUG("Halting remaining targets in SMP group");
495  aarch64_halt_smp(target, true);
496  }
497 
498  /* poll all targets in the group */
499  foreach_smp_target(head, target->smp_targets) {
500  curr = head->target;
501  /* skip calling context */
502  if (curr == target)
503  continue;
504  if (!target_was_examined(curr))
505  continue;
506  /* skip targets that were already halted */
507  if (curr->state == TARGET_HALTED)
508  continue;
509 
510  const bool smp = false;
511  const bool postpone_event = true;
512  aarch64_poll_smp(curr, smp, postpone_event);
513  }
514 
515  return ERROR_OK;
516 }
517 
518 enum postponed_halt_events_op {
519  POSTPONED_HALT_EVENT_CLEAR,
520  POSTPONED_HALT_EVENT_EMIT
521 };
522 
523 static void aarch64_smp_postponed_halt_events(struct list_head *smp_targets,
524  enum postponed_halt_events_op op)
525 {
526  struct target_list *head;
527  foreach_smp_target(head, smp_targets) {
528  struct target *t = head->target;
529  if (!t->smp_halt_event_postponed)
530  continue;
531 
532  if (op == POSTPONED_HALT_EVENT_EMIT) {
533  LOG_TARGET_DEBUG(t, "sending postponed target event 'halted'");
534  target_call_event_callbacks(t, TARGET_EVENT_HALTED);
535  }
536  t->smp_halt_event_postponed = false;
537  }
538 }
539 
540 /*
541  * Aarch64 Run control
542  */
543 
544 static int aarch64_poll_smp(struct target *target, bool smp,
545  bool postpone_event)
546 {
547  struct armv8_common *armv8 = target_to_armv8(target);
548  enum target_state prev_target_state;
549  int retval = ERROR_OK;
550  uint32_t prsr;
551 
552  retval = aarch64_read_prsr(target, &prsr);
553  if (retval != ERROR_OK)
554  return retval;
555 
556  if (armv8->sticky_reset) {
557  armv8->sticky_reset = false;
558  if (target->state != TARGET_RESET) {
559  target->state = TARGET_RESET;
560  LOG_TARGET_INFO(target, "external reset detected");
561  if (armv8->arm.core_cache) {
562  register_cache_invalidate(armv8->arm.core_cache);
563  register_cache_invalidate(armv8->arm.core_cache->next);
564  }
565  }
566  }
567 
568  if (prsr & PRSR_HALT) {
569  prev_target_state = target->state;
570  if (prev_target_state != TARGET_HALTED) {
571  enum target_debug_reason debug_reason = target->debug_reason;
572 
573  /* We have a halting debug event */
574  target->state = TARGET_HALTED;
575  LOG_DEBUG("Target %s halted", target_name(target));
576  retval = aarch64_debug_entry(target);
577  if (retval != ERROR_OK)
578  return retval;
579 
580  if (smp)
581  aarch64_update_halt_gdb(target, debug_reason);
582 
583  if (arm_semihosting(target, &retval) != 0) {
584  if (smp)
585  aarch64_smp_postponed_halt_events(target->smp_targets,
586  POSTPONED_HALT_EVENT_CLEAR);
587 
588  return retval;
589  }
590 
591  switch (prev_target_state) {
592  case TARGET_RUNNING:
593  case TARGET_UNKNOWN:
594  case TARGET_RESET:
595  if (postpone_event)
596  target->smp_halt_event_postponed = true;
597  else
598  target_call_event_callbacks(target, TARGET_EVENT_HALTED);
599  break;
600  case TARGET_DEBUG_RUNNING:
601  target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
602  break;
603  default:
604  break;
605  }
606 
607  if (smp)
608  aarch64_smp_postponed_halt_events(target->smp_targets,
609  POSTPONED_HALT_EVENT_EMIT);
610  }
611  } else if (prsr & PRSR_RESET) {
612  target->state = TARGET_RESET;
613  } else {
614  target->state = TARGET_RUNNING;
615  }
616 
617  return retval;
618 }
619 
620 static int aarch64_poll(struct target *target)
621 {
622  const bool postpone_event = false;
623  return aarch64_poll_smp(target, target->smp != 0, postpone_event);
624 }
625 
626 static int aarch64_halt(struct target *target)
627 {
628  struct armv8_common *armv8 = target_to_armv8(target);
629  armv8->last_run_control_op = ARMV8_RUNCONTROL_HALT;
630 
631  if (target->smp)
632  return aarch64_halt_smp(target, false);
633 
634  return aarch64_halt_one(target, HALT_SYNC);
635 }
636 
637 static int aarch64_restore_one(struct target *target, bool current,
638  uint64_t *address, bool handle_breakpoints, bool debug_execution)
639 {
640  struct armv8_common *armv8 = target_to_armv8(target);
641  struct arm *arm = &armv8->arm;
642  int retval;
643  uint64_t resume_pc;
644 
645  LOG_DEBUG("%s", target_name(target));
646 
647  if (!debug_execution)
648  target_free_all_working_areas(target);
649 
650  /* current = true: continue on current pc, otherwise continue at <address> */
651  resume_pc = buf_get_u64(arm->pc->value, 0, 64);
652  if (!current)
653  resume_pc = *address;
654  else
655  *address = resume_pc;
656 
657  /* Make sure that the Armv7 gdb thumb fixups does not
658  * kill the return address
659  */
660  switch (arm->core_state) {
661  case ARM_STATE_ARM:
662  resume_pc &= 0xFFFFFFFC;
663  break;
664  case ARM_STATE_AARCH64:
665  resume_pc &= 0xFFFFFFFFFFFFFFFCULL;
666  break;
667  case ARM_STATE_THUMB:
668  case ARM_STATE_THUMB_EE:
669  /* When the return address is loaded into PC
670  * bit 0 must be 1 to stay in Thumb state
671  */
672  resume_pc |= 0x1;
673  break;
674  case ARM_STATE_JAZELLE:
675  LOG_ERROR("How do I resume into Jazelle state??");
676  return ERROR_FAIL;
677  }
678  LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc);
679  buf_set_u64(arm->pc->value, 0, 64, resume_pc);
680  arm->pc->dirty = true;
681  arm->pc->valid = true;
682 
683  /* called it now before restoring context because it uses cpu
684  * register r0 for restoring system control register */
685  retval = aarch64_restore_system_control_reg(target);
686  if (retval == ERROR_OK)
687  retval = aarch64_restore_context(target, handle_breakpoints);
688 
689  return retval;
690 }
691 
697 static int aarch64_prepare_restart_one(struct target *target)
698 {
699  struct armv8_common *armv8 = target_to_armv8(target);
700  int retval;
701  uint32_t dscr;
702  uint32_t tmp;
703 
704  LOG_DEBUG("%s", target_name(target));
705 
706  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
707  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
708  if (retval != ERROR_OK)
709  return retval;
710 
711  if ((dscr & DSCR_ITE) == 0)
712  LOG_ERROR("DSCR.ITE must be set before leaving debug!");
713  if ((dscr & DSCR_ERR) != 0)
714  LOG_ERROR("DSCR.ERR must be cleared before leaving debug!");
715 
716  /* acknowledge a pending CTI halt event */
717  retval = arm_cti_ack_events(armv8->cti, CTI_TRIG(HALT));
718  /*
719  * open the CTI gate for channel 1 so that the restart events
720  * get passed along to all PEs. Also close gate for channel 0
721  * to isolate the PE from halt events.
722  */
723  if (retval == ERROR_OK)
724  retval = arm_cti_ungate_channel(armv8->cti, 1);
725  if (retval == ERROR_OK)
726  retval = arm_cti_gate_channel(armv8->cti, 0);
727 
728  /* make sure that DSCR.HDE is set */
729  if (retval == ERROR_OK) {
730  dscr |= DSCR_HDE;
731  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
732  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
733  }
734 
735  if (retval == ERROR_OK) {
736  /* clear sticky bits in PRSR, SDR is now 0 */
737  retval = aarch64_read_prsr(target, &tmp);
738  }
739 
740  return retval;
741 }
742 
743 static int aarch64_do_restart_one(struct target *target, enum restart_mode mode)
744 {
745  struct armv8_common *armv8 = target_to_armv8(target);
746  int retval;
747 
748  LOG_DEBUG("%s", target_name(target));
749 
750  /* trigger an event on channel 1, generates a restart request to the PE */
751  retval = arm_cti_pulse_channel(armv8->cti, 1);
752  if (retval != ERROR_OK)
753  return retval;
754 
755  if (mode == RESTART_SYNC) {
756  int64_t then = timeval_ms();
757  for (;;) {
758  uint32_t prsr;
759  int resumed;
760  /*
761  * If PRSR.SDR is set now, the target did restart, even
762  * if it's now already halted again (e.g. due to breakpoint).
763  * Some systems do not reliably latch SDR for this CTI resume,
764  * so also accept PRSR.HALT clearing as proof of resume.
765  */
766  retval = aarch64_check_state_one(target,
767  PRSR_SDR, PRSR_SDR, &resumed, &prsr);
768  if (retval != ERROR_OK || resumed || !(prsr & PRSR_HALT))
769  break;
770 
771  if (timeval_ms() > then + 1000) {
772  LOG_ERROR("%s: Timeout waiting for resume"PRIx32, target_name(target));
773  retval = ERROR_TARGET_TIMEOUT;
774  break;
775  }
776  }
777  }
778 
779  if (retval != ERROR_OK)
780  return retval;
781 
782  target->debug_reason = DBG_REASON_NOTHALTED;
783  target->state = TARGET_RUNNING;
784 
785  return ERROR_OK;
786 }
787 
788 static int aarch64_restart_one(struct target *target, enum restart_mode mode)
789 {
790  int retval;
791 
792  LOG_DEBUG("%s", target_name(target));
793 
794  retval = aarch64_prepare_restart_one(target);
795  if (retval == ERROR_OK)
796  retval = aarch64_do_restart_one(target, mode);
797 
798  return retval;
799 }
800 
801 /*
802  * prepare all but the current target for restart
803  */
804 static int aarch64_prep_restart_smp(struct target *target,
805  bool handle_breakpoints, struct target **p_first)
806 {
807  int retval = ERROR_OK;
808  struct target_list *head;
809  struct target *first = NULL;
810  uint64_t address;
811 
812  foreach_smp_target(head, target->smp_targets) {
813  struct target *curr = head->target;
814 
815  /* skip calling target */
816  if (curr == target)
817  continue;
818  if (!target_was_examined(curr))
819  continue;
820  if (curr->state != TARGET_HALTED)
821  continue;
822 
823  /* resume at current address, not in step mode */
824  retval = aarch64_restore_one(curr, true, &address, handle_breakpoints,
825  false);
826  if (retval == ERROR_OK)
827  retval = aarch64_prepare_restart_one(curr);
828  if (retval != ERROR_OK) {
829  LOG_ERROR("failed to restore target %s", target_name(curr));
830  break;
831  }
832  /* remember the first valid target in the group */
833  if (!first)
834  first = curr;
835  }
836 
837  if (p_first)
838  *p_first = first;
839 
840  return retval;
841 }
842 
843 
844 static int aarch64_step_restart_smp(struct target *target)
845 {
846  int retval = ERROR_OK;
847  struct target_list *head;
848  struct target *first = NULL;
849 
850  LOG_DEBUG("%s", target_name(target));
851 
852  retval = aarch64_prep_restart_smp(target, false, &first);
853  if (retval != ERROR_OK)
854  return retval;
855 
856  if (first)
857  retval = aarch64_do_restart_one(first, RESTART_LAZY);
858  if (retval != ERROR_OK) {
859  LOG_DEBUG("error restarting target %s", target_name(first));
860  return retval;
861  }
862 
863  int64_t then = timeval_ms();
864  for (;;) {
865  struct target *curr = target;
866  bool all_resumed = true;
867 
868  foreach_smp_target(head, target->smp_targets) {
869  uint32_t prsr;
870  int resumed;
871 
872  curr = head->target;
873 
874  if (curr == target)
875  continue;
876 
877  if (!target_was_examined(curr))
878  continue;
879 
880  retval = aarch64_check_state_one(curr,
881  PRSR_SDR, PRSR_SDR, &resumed, &prsr);
882  if (retval != ERROR_OK || (!resumed && (prsr & PRSR_HALT))) {
883  all_resumed = false;
884  break;
885  }
886 
887  if (curr->state != TARGET_RUNNING) {
888  curr->state = TARGET_RUNNING;
889  curr->debug_reason = DBG_REASON_NOTHALTED;
890  target_call_event_callbacks(curr, TARGET_EVENT_RESUMED);
891  }
892  }
893 
894  if (all_resumed)
895  break;
896 
897  if (timeval_ms() > then + 1000) {
898  LOG_ERROR("%s: timeout waiting for target resume", __func__);
899  retval = ERROR_TARGET_TIMEOUT;
900  break;
901  }
902  /*
903  * HACK: on Hi6220 there are 8 cores organized in 2 clusters
904  * and it looks like the CTI's are not connected by a common
905  * trigger matrix. It seems that we need to halt one core in each
906  * cluster explicitly. So if we find that a core has not halted
907  * yet, we trigger an explicit resume for the second cluster.
908  */
909  retval = aarch64_do_restart_one(curr, RESTART_LAZY);
910  if (retval != ERROR_OK)
911  break;
912  }
913 
914  return retval;
915 }
916 
917 static int aarch64_resume(struct target *target, bool current,
918  target_addr_t address, bool handle_breakpoints, bool debug_execution)
919 {
920  int retval = 0;
921  uint64_t addr = address;
922 
923  struct armv8_common *armv8 = target_to_armv8(target);
924  armv8->last_run_control_op = ARMV8_RUNCONTROL_RESUME;
925 
926  if (target->state != TARGET_HALTED) {
927  LOG_TARGET_ERROR(target, "not halted");
928  return ERROR_TARGET_NOT_HALTED;
929  }
930 
931  /*
932  * If this target is part of a SMP group, prepare the others
933  * targets for resuming. This involves restoring the complete
934  * target register context and setting up CTI gates to accept
935  * resume events from the trigger matrix.
936  */
937  if (target->smp) {
938  retval = aarch64_prep_restart_smp(target, handle_breakpoints, NULL);
939  if (retval != ERROR_OK)
940  return retval;
941  }
942 
943  /* all targets prepared, restore and restart the current target */
944  retval = aarch64_restore_one(target, current, &addr, handle_breakpoints,
945  debug_execution);
946  if (retval == ERROR_OK)
947  retval = aarch64_restart_one(target, RESTART_SYNC);
948  if (retval != ERROR_OK)
949  return retval;
950 
951  if (target->smp) {
952  int64_t then = timeval_ms();
953  for (;;) {
954  struct target *curr = target;
955  struct target_list *head;
956  bool all_resumed = true;
957 
958  foreach_smp_target(head, target->smp_targets) {
959  uint32_t prsr;
960  int resumed;
961 
962  curr = head->target;
963  if (curr == target)
964  continue;
965  if (!target_was_examined(curr))
966  continue;
967 
968  retval = aarch64_check_state_one(curr,
969  PRSR_SDR, PRSR_SDR, &resumed, &prsr);
970  if (retval != ERROR_OK || (!resumed && (prsr & PRSR_HALT))) {
971  all_resumed = false;
972  break;
973  }
974 
975  if (curr->state != TARGET_RUNNING) {
976  struct armv8_common *curr_armv8 = target_to_armv8(curr);
977  curr_armv8->last_run_control_op = ARMV8_RUNCONTROL_RESUME;
978  curr->state = TARGET_RUNNING;
979  curr->debug_reason = DBG_REASON_NOTHALTED;
980  target_call_event_callbacks(curr, TARGET_EVENT_RESUMED);
981  }
982  }
983 
984  if (all_resumed)
985  break;
986 
987  if (timeval_ms() > then + 1000) {
988  LOG_ERROR("%s: timeout waiting for target %s to resume", __func__, target_name(curr));
989  retval = ERROR_TARGET_TIMEOUT;
990  break;
991  }
992 
993  /*
994  * HACK: on Hi6220 there are 8 cores organized in 2 clusters
995  * and it looks like the CTI's are not connected by a common
996  * trigger matrix. It seems that we need to halt one core in each
997  * cluster explicitly. So if we find that a core has not halted
998  * yet, we trigger an explicit resume for the second cluster.
999  */
1000  retval = aarch64_do_restart_one(curr, RESTART_LAZY);
1001  if (retval != ERROR_OK)
1002  break;
1003  }
1004  }
1005 
1006  if (retval != ERROR_OK)
1007  return retval;
1008 
1009  target->debug_reason = DBG_REASON_NOTHALTED;
1010 
1011  if (!debug_execution) {
1012  target->state = TARGET_RUNNING;
1013  target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1014  LOG_DEBUG("target resumed at 0x%" PRIx64, addr);
1015  } else {
1016  target->state = TARGET_DEBUG_RUNNING;
1017  target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1018  LOG_DEBUG("target debug resumed at 0x%" PRIx64, addr);
1019  }
1020 
1021  return ERROR_OK;
1022 }
1023 
1024 static int aarch64_debug_entry(struct target *target)
1025 {
1026  int retval = ERROR_OK;
1027  struct armv8_common *armv8 = target_to_armv8(target);
1028  struct arm_dpm *dpm = &armv8->dpm;
1029  enum arm_state core_state;
1030  uint32_t dscr;
1031 
1032  /* make sure to clear all sticky errors */
1033  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1034  armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
1035  if (retval == ERROR_OK)
1036  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1037  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
1038  if (retval == ERROR_OK)
1039  retval = arm_cti_ack_events(armv8->cti, CTI_TRIG(HALT));
1040 
1041  if (retval != ERROR_OK)
1042  return retval;
1043 
1044  LOG_DEBUG("%s dscr = 0x%08" PRIx32, target_name(target), dscr);
1045 
1046  dpm->dscr = dscr;
1047  core_state = armv8_dpm_get_core_state(dpm);
1048  armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64);
1049  armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64);
1050 
1051  /* close the CTI gate for all events */
1052  if (retval == ERROR_OK)
1053  retval = arm_cti_write_reg(armv8->cti, CTI_GATE, 0);
1054  /* discard async exceptions */
1055  if (retval == ERROR_OK)
1056  retval = dpm->instr_cpsr_sync(dpm);
1057  if (retval != ERROR_OK)
1058  return retval;
1059 
1060  /* Examine debug reason */
1061  armv8_dpm_report_dscr(dpm, dscr);
1062 
1063  /* save the memory address that triggered the watchpoint */
1064  if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1065  uint32_t tmp;
1066 
1067  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1068  armv8->debug_base + CPUV8_DBG_EDWAR0, &tmp);
1069  if (retval != ERROR_OK)
1070  return retval;
1071  target_addr_t edwar = tmp;
1072 
1073  /* EDWAR[63:32] has unknown content in aarch32 state */
1074  if (core_state == ARM_STATE_AARCH64) {
1075  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1076  armv8->debug_base + CPUV8_DBG_EDWAR1, &tmp);
1077  if (retval != ERROR_OK)
1078  return retval;
1079  edwar |= ((target_addr_t)tmp) << 32;
1080  }
1081 
1082  armv8->dpm.wp_addr = edwar;
1083  }
1084 
1085  retval = armv8_dpm_read_current_registers(&armv8->dpm);
1086 
1087  if (retval == ERROR_OK && armv8->post_debug_entry)
1088  retval = armv8->post_debug_entry(target);
1089 
1090  return retval;
1091 }
1092 
1093 static int aarch64_post_debug_entry(struct target *target)
1094 {
1095  struct aarch64_common *aarch64 = target_to_aarch64(target);
1096  struct armv8_common *armv8 = &aarch64->armv8_common;
1097  int retval;
1098  enum arm_mode target_mode = ARM_MODE_ANY;
1099  uint32_t instr;
1100 
1101  switch (armv8->arm.core_mode) {
1102  case ARMV8_64_EL0T:
1103  target_mode = ARMV8_64_EL1H;
1104  /* fall through */
1105  case ARMV8_64_EL1T:
1106  case ARMV8_64_EL1H:
1107  instr = ARMV8_MRS(SYSTEM_SCTLR_EL1, 0);
1108  break;
1109  case ARMV8_64_EL2T:
1110  case ARMV8_64_EL2H:
1111  instr = ARMV8_MRS(SYSTEM_SCTLR_EL2, 0);
1112  break;
1113  case ARMV8_64_EL3H:
1114  case ARMV8_64_EL3T:
1115  instr = ARMV8_MRS(SYSTEM_SCTLR_EL3, 0);
1116  break;
1117 
1118  case ARM_MODE_SVC:
1119  case ARM_MODE_ABT:
1120  case ARM_MODE_FIQ:
1121  case ARM_MODE_IRQ:
1122  case ARM_MODE_HYP:
1123  case ARM_MODE_UND:
1124  case ARM_MODE_SYS:
1125  case ARM_MODE_MON:
1126  instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
1127  break;
1128 
1129  default:
1130  LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)",
1131  armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
1132  return ERROR_FAIL;
1133  }
1134 
1135  if (target_mode != ARM_MODE_ANY)
1136  armv8_dpm_modeswitch(&armv8->dpm, target_mode);
1137 
1138  retval = armv8->dpm.instr_read_data_r0_64(&armv8->dpm, instr, &aarch64->system_control_reg);
1139  if (retval != ERROR_OK)
1140  return retval;
1141 
1142  if (target_mode != ARM_MODE_ANY)
1143  armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
1144 
1145  LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg);
1146  aarch64->system_control_reg_curr = aarch64->system_control_reg;
1147 
1148  if (!armv8->armv8_mmu.armv8_cache.info_valid) {
1149  armv8_identify_cache(armv8);
1150  armv8_read_mpidr(armv8);
1151  }
1152  if (armv8->is_armv8r) {
1153  armv8->armv8_mmu.mmu_enabled = false;
1154  } else {
1155  armv8->armv8_mmu.mmu_enabled = aarch64->system_control_reg & 0x1U;
1156  }
1157  armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
1158  aarch64->system_control_reg & 0x4U;
1159  armv8->armv8_mmu.armv8_cache.i_cache_enabled =
1160  aarch64->system_control_reg & 0x1000U;
1161  return ERROR_OK;
1162 }
1163 
1164 /*
1165  * single-step a target
1166  */
1167 static int aarch64_step(struct target *target, bool current, target_addr_t address,
1168  bool handle_breakpoints)
1169 {
1170  struct armv8_common *armv8 = target_to_armv8(target);
1171  struct aarch64_common *aarch64 = target_to_aarch64(target);
1172  int saved_retval = ERROR_OK;
1173  int poll_retval;
1174  int retval;
1175  uint32_t edecr;
1176 
1177  armv8->last_run_control_op = ARMV8_RUNCONTROL_STEP;
1178 
1179  if (target->state != TARGET_HALTED) {
1180  LOG_TARGET_ERROR(target, "not halted");
1181  return ERROR_TARGET_NOT_HALTED;
1182  }
1183 
1184  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1185  armv8->debug_base + CPUV8_DBG_EDECR, &edecr);
1186  /* make sure EDECR.SS is not set when restoring the register */
1187 
1188  if (retval == ERROR_OK) {
1189  edecr &= ~0x4;
1190  /* set EDECR.SS to enter hardware step mode */
1191  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1192  armv8->debug_base + CPUV8_DBG_EDECR, (edecr|0x4));
1193  }
1194  /* disable interrupts while stepping */
1195  if (retval == ERROR_OK && aarch64->isrmasking_mode == AARCH64_ISRMASK_ON)
1196  retval = aarch64_set_dscr_bits(target, 0x3 << 22, 0x3 << 22);
1197  /* bail out if stepping setup has failed */
1198  if (retval != ERROR_OK)
1199  return retval;
1200 
1201  if (target->smp && current) {
1202  /*
1203  * isolate current target so that it doesn't get resumed
1204  * together with the others
1205  */
1206  retval = arm_cti_gate_channel(armv8->cti, 1);
1207  /* resume all other targets in the group */
1208  if (retval == ERROR_OK)
1209  retval = aarch64_step_restart_smp(target);
1210  if (retval != ERROR_OK) {
1211  LOG_ERROR("Failed to restart non-stepping targets in SMP group");
1212  return retval;
1213  }
1214  LOG_DEBUG("Restarted all non-stepping targets in SMP group");
1215  }
1216 
1217  /* all other targets running, restore and restart the current target */
1218  retval = aarch64_restore_one(target, current, &address, false, false);
1219  if (retval == ERROR_OK)
1220  retval = aarch64_restart_one(target, RESTART_LAZY);
1221 
1222  if (retval != ERROR_OK)
1223  return retval;
1224 
1225  LOG_DEBUG("target step-resumed at 0x%" PRIx64, address);
1226  if (!handle_breakpoints)
1227  target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1228 
1229  int64_t then = timeval_ms();
1230  for (;;) {
1231  int stepped;
1232  uint32_t prsr;
1233 
1234  retval = aarch64_check_state_one(target,
1235  PRSR_SDR|PRSR_HALT, PRSR_SDR|PRSR_HALT, &stepped, &prsr);
1236  if (retval != ERROR_OK || stepped)
1237  break;
1238 
1239  if (timeval_ms() > then + 100) {
1240  LOG_ERROR("timeout waiting for target %s halt after step",
1241  target_name(target));
1242  retval = ERROR_TARGET_TIMEOUT;
1243  break;
1244  }
1245  }
1246 
1247  /*
1248  * At least on one SoC (Renesas R8A7795) stepping over a WFI instruction
1249  * causes a timeout. The core takes the step but doesn't complete it and so
1250  * debug state is never entered. However, you can manually halt the core
1251  * as an external debug even is also a WFI wakeup event.
1252  */
1253  if (retval == ERROR_TARGET_TIMEOUT)
1254  saved_retval = aarch64_halt_one(target, HALT_SYNC);
1255 
1256  poll_retval = aarch64_poll(target);
1257 
1258  /* restore EDECR */
1259  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1260  armv8->debug_base + CPUV8_DBG_EDECR, edecr);
1261  if (retval != ERROR_OK)
1262  return retval;
1263 
1264  /* restore interrupts */
1265  if (aarch64->isrmasking_mode == AARCH64_ISRMASK_ON) {
1266  retval = aarch64_set_dscr_bits(target, 0x3 << 22, 0);
1267  if (retval != ERROR_OK)
1268  return ERROR_OK;
1269  }
1270 
1271  if (saved_retval != ERROR_OK)
1272  return saved_retval;
1273 
1274  if (poll_retval != ERROR_OK)
1275  return poll_retval;
1276 
1277  return ERROR_OK;
1278 }
1279 
1280 static int aarch64_restore_context(struct target *target, bool bpwp)
1281 {
1282  struct armv8_common *armv8 = target_to_armv8(target);
1283  struct arm *arm = &armv8->arm;
1284 
1285  int retval;
1286 
1287  LOG_DEBUG("%s", target_name(target));
1288 
1289  if (armv8->pre_restore_context)
1290  armv8->pre_restore_context(target);
1291 
1292  retval = armv8_dpm_write_dirty_registers(&armv8->dpm, bpwp);
1293  if (retval == ERROR_OK) {
1294  /* registers are now invalid */
1295  register_cache_invalidate(arm->core_cache);
1296  register_cache_invalidate(arm->core_cache->next);
1297  }
1298 
1299  return retval;
1300 }
1301 
1302 /*
1303  * Cortex-A8 Breakpoint and watchpoint functions
1304  */
1305 
1306 /* Setup hardware Breakpoint Register Pair */
1307 static int aarch64_set_breakpoint(struct target *target,
1308  struct breakpoint *breakpoint, uint8_t matchmode)
1309 {
1310  int retval;
1311  int brp_i = 0;
1312  uint32_t control;
1313  uint8_t byte_addr_select = 0x0F;
1314  struct aarch64_common *aarch64 = target_to_aarch64(target);
1315  struct armv8_common *armv8 = &aarch64->armv8_common;
1316  struct aarch64_brp *brp_list = aarch64->brp_list;
1317 
1318  if (breakpoint->is_set) {
1319  LOG_WARNING("breakpoint already set");
1320  return ERROR_OK;
1321  }
1322 
1323  if (breakpoint->type == BKPT_HARD) {
1324  int64_t bpt_value;
1325  while (brp_list[brp_i].used && (brp_i < aarch64->brp_num))
1326  brp_i++;
1327  if (brp_i >= aarch64->brp_num) {
1328  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1329  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1330  }
1331  breakpoint_hw_set(breakpoint, brp_i);
1332  if (breakpoint->length == 2)
1333  byte_addr_select = (3 << (breakpoint->address & 0x02));
1334  control = ((matchmode & 0x7) << 20)
1335  | (1 << 13)
1336  | (byte_addr_select << 5)
1337  | (3 << 1) | 1;
1338  brp_list[brp_i].used = 1;
1339  brp_list[brp_i].value = breakpoint->address & 0xFFFFFFFFFFFFFFFCULL;
1340  brp_list[brp_i].control = control;
1341  bpt_value = brp_list[brp_i].value;
1342 
1343  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1344  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1345  (uint32_t)(bpt_value & 0xFFFFFFFF));
1346  if (retval != ERROR_OK)
1347  return retval;
1348  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1349  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
1350  (uint32_t)(bpt_value >> 32));
1351  if (retval != ERROR_OK)
1352  return retval;
1353 
1354  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1355  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1356  brp_list[brp_i].control);
1357  if (retval != ERROR_OK)
1358  return retval;
1359  LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1360  brp_list[brp_i].control,
1361  brp_list[brp_i].value);
1362 
1363  } else if (breakpoint->type == BKPT_SOFT) {
1364  uint32_t opcode;
1365  uint8_t code[4];
1366 
1367  if (armv8_dpm_get_core_state(&armv8->dpm) == ARM_STATE_AARCH64) {
1368  opcode = ARMV8_HLT(11);
1369 
1370  if (breakpoint->length != 4)
1371  LOG_ERROR("bug: breakpoint length should be 4 in AArch64 mode");
1372  } else {
1381  opcode = (breakpoint->length == 4) ? ARMV8_HLT_A1(11) :
1382  (uint32_t) (ARMV8_HLT_T1(11) | ARMV8_HLT_T1(11) << 16);
1383 
1384  if (breakpoint->length == 3)
1385  breakpoint->length = 4;
1386  }
1387 
1388  buf_set_u32(code, 0, 32, opcode);
1389 
1390  retval = target_read_memory(target,
1391  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1392  breakpoint->length, 1,
1393  breakpoint->orig_instr);
1394  if (retval != ERROR_OK)
1395  return retval;
1396 
1397  armv8_cache_d_inner_flush_virt(armv8,
1398  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1399  breakpoint->length);
1400 
1401  retval = target_write_memory(target,
1402  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1403  breakpoint->length, 1, code);
1404  if (retval != ERROR_OK)
1405  return retval;
1406 
1407  armv8_cache_d_inner_flush_virt(armv8,
1408  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1409  breakpoint->length);
1410 
1411  armv8_cache_i_inner_inval_virt(armv8,
1412  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1413  breakpoint->length);
1414 
1415  breakpoint->is_set = true;
1416  }
1417 
1418  /* Ensure that halting debug mode is enable */
1419  retval = aarch64_set_dscr_bits(target, DSCR_HDE, DSCR_HDE);
1420  if (retval != ERROR_OK) {
1421  LOG_DEBUG("Failed to set DSCR.HDE");
1422  return retval;
1423  }
1424 
1425  return ERROR_OK;
1426 }
1427 
1428 static int aarch64_set_context_breakpoint(struct target *target,
1429  struct breakpoint *breakpoint, uint8_t matchmode)
1430 {
1431  int retval = ERROR_FAIL;
1432  int brp_i = 0;
1433  uint32_t control;
1434  uint8_t byte_addr_select = 0x0F;
1435  struct aarch64_common *aarch64 = target_to_aarch64(target);
1436  struct armv8_common *armv8 = &aarch64->armv8_common;
1437  struct aarch64_brp *brp_list = aarch64->brp_list;
1438 
1439  if (breakpoint->is_set) {
1440  LOG_WARNING("breakpoint already set");
1441  return retval;
1442  }
1443  /*check available context BRPs*/
1444  while ((brp_list[brp_i].used ||
1445  (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < aarch64->brp_num))
1446  brp_i++;
1447 
1448  if (brp_i >= aarch64->brp_num) {
1449  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1450  return ERROR_FAIL;
1451  }
1452 
1453  breakpoint_hw_set(breakpoint, brp_i);
1454  control = ((matchmode & 0x7) << 20)
1455  | (1 << 13)
1456  | (byte_addr_select << 5)
1457  | (3 << 1) | 1;
1458  brp_list[brp_i].used = 1;
1459  brp_list[brp_i].value = (breakpoint->asid);
1460  brp_list[brp_i].control = control;
1461  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1462  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1463  brp_list[brp_i].value);
1464  if (retval != ERROR_OK)
1465  return retval;
1466  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1467  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1468  brp_list[brp_i].control);
1469  if (retval != ERROR_OK)
1470  return retval;
1471  LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1472  brp_list[brp_i].control,
1473  brp_list[brp_i].value);
1474  return ERROR_OK;
1475 
1476 }
1477 
1478 static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
1479 {
1480  int retval = ERROR_FAIL;
1481  int brp_1 = 0; /* holds the contextID pair */
1482  int brp_2 = 0; /* holds the IVA pair */
1483  uint32_t control_ctx, control_iva;
1484  uint8_t ctx_byte_addr_select = 0x0F;
1485  uint8_t iva_byte_addr_select = 0x0F;
1486  uint8_t ctx_machmode = 0x03;
1487  uint8_t iva_machmode = 0x01;
1488  struct aarch64_common *aarch64 = target_to_aarch64(target);
1489  struct armv8_common *armv8 = &aarch64->armv8_common;
1490  struct aarch64_brp *brp_list = aarch64->brp_list;
1491 
1492  if (breakpoint->is_set) {
1493  LOG_WARNING("breakpoint already set");
1494  return retval;
1495  }
1496  /*check available context BRPs*/
1497  while ((brp_list[brp_1].used ||
1498  (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < aarch64->brp_num))
1499  brp_1++;
1500 
1501  LOG_DEBUG("brp(CTX) found num: %d", brp_1);
1502  if (brp_1 >= aarch64->brp_num) {
1503  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1504  return ERROR_FAIL;
1505  }
1506 
1507  while ((brp_list[brp_2].used ||
1508  (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < aarch64->brp_num))
1509  brp_2++;
1510 
1511  LOG_DEBUG("brp(IVA) found num: %d", brp_2);
1512  if (brp_2 >= aarch64->brp_num) {
1513  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1514  return ERROR_FAIL;
1515  }
1516 
1517  breakpoint_hw_set(breakpoint, brp_1);
1518  breakpoint->linked_brp = brp_2;
1519  control_ctx = ((ctx_machmode & 0x7) << 20)
1520  | (brp_2 << 16)
1521  | (0 << 14)
1522  | (ctx_byte_addr_select << 5)
1523  | (3 << 1) | 1;
1524  brp_list[brp_1].used = 1;
1525  brp_list[brp_1].value = (breakpoint->asid);
1526  brp_list[brp_1].control = control_ctx;
1527  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1528  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_1].brpn,
1529  brp_list[brp_1].value);
1530  if (retval != ERROR_OK)
1531  return retval;
1532  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1533  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_1].brpn,
1534  brp_list[brp_1].control);
1535  if (retval != ERROR_OK)
1536  return retval;
1537 
1538  control_iva = ((iva_machmode & 0x7) << 20)
1539  | (brp_1 << 16)
1540  | (1 << 13)
1541  | (iva_byte_addr_select << 5)
1542  | (3 << 1) | 1;
1543  brp_list[brp_2].used = 1;
1544  brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFCULL;
1545  brp_list[brp_2].control = control_iva;
1546  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1547  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].brpn,
1548  brp_list[brp_2].value & 0xFFFFFFFF);
1549  if (retval != ERROR_OK)
1550  return retval;
1551  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1552  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_2].brpn,
1553  brp_list[brp_2].value >> 32);
1554  if (retval != ERROR_OK)
1555  return retval;
1556  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1557  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_2].brpn,
1558  brp_list[brp_2].control);
1559  if (retval != ERROR_OK)
1560  return retval;
1561 
1562  return ERROR_OK;
1563 }
1564 
1565 static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1566 {
1567  int retval;
1568  struct aarch64_common *aarch64 = target_to_aarch64(target);
1569  struct armv8_common *armv8 = &aarch64->armv8_common;
1570  struct aarch64_brp *brp_list = aarch64->brp_list;
1571 
1572  if (!breakpoint->is_set) {
1573  LOG_WARNING("breakpoint not set");
1574  return ERROR_OK;
1575  }
1576 
1577  if (breakpoint->type == BKPT_HARD) {
1578  if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
1579  int brp_i = breakpoint->number;
1580  int brp_j = breakpoint->linked_brp;
1581  if (brp_i >= aarch64->brp_num) {
1582  LOG_DEBUG("Invalid BRP number in breakpoint");
1583  return ERROR_OK;
1584  }
1585  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1586  brp_list[brp_i].control, brp_list[brp_i].value);
1587  brp_list[brp_i].used = 0;
1588  brp_list[brp_i].value = 0;
1589  brp_list[brp_i].control = 0;
1590  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1591  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1592  brp_list[brp_i].control);
1593  if (retval != ERROR_OK)
1594  return retval;
1595  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1596  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1597  (uint32_t)brp_list[brp_i].value);
1598  if (retval != ERROR_OK)
1599  return retval;
1600  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1601  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
1602  (uint32_t)brp_list[brp_i].value);
1603  if (retval != ERROR_OK)
1604  return retval;
1605  if ((brp_j < 0) || (brp_j >= aarch64->brp_num)) {
1606  LOG_DEBUG("Invalid BRP number in breakpoint");
1607  return ERROR_OK;
1608  }
1609  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_j,
1610  brp_list[brp_j].control, brp_list[brp_j].value);
1611  brp_list[brp_j].used = 0;
1612  brp_list[brp_j].value = 0;
1613  brp_list[brp_j].control = 0;
1614  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1615  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_j].brpn,
1616  brp_list[brp_j].control);
1617  if (retval != ERROR_OK)
1618  return retval;
1619  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1620  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].brpn,
1621  (uint32_t)brp_list[brp_j].value);
1622  if (retval != ERROR_OK)
1623  return retval;
1624  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1625  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].brpn,
1626  (uint32_t)brp_list[brp_j].value);
1627  if (retval != ERROR_OK)
1628  return retval;
1629 
1630  breakpoint->linked_brp = 0;
1631  breakpoint->is_set = false;
1632  return ERROR_OK;
1633 
1634  } else {
1635  int brp_i = breakpoint->number;
1636  if (brp_i >= aarch64->brp_num) {
1637  LOG_DEBUG("Invalid BRP number in breakpoint");
1638  return ERROR_OK;
1639  }
1640  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_i,
1641  brp_list[brp_i].control, brp_list[brp_i].value);
1642  brp_list[brp_i].used = 0;
1643  brp_list[brp_i].value = 0;
1644  brp_list[brp_i].control = 0;
1645  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1646  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1647  brp_list[brp_i].control);
1648  if (retval != ERROR_OK)
1649  return retval;
1650  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1651  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1652  brp_list[brp_i].value);
1653  if (retval != ERROR_OK)
1654  return retval;
1655 
1656  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1657  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
1658  (uint32_t)brp_list[brp_i].value);
1659  if (retval != ERROR_OK)
1660  return retval;
1661  breakpoint->is_set = false;
1662  return ERROR_OK;
1663  }
1664  } else {
1665  /* restore original instruction (kept in target endianness) */
1666 
1667  armv8_cache_d_inner_flush_virt(armv8,
1668  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1669  breakpoint->length);
1670 
1671  if (breakpoint->length == 4) {
1672  retval = target_write_memory(target,
1673  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1674  4, 1, breakpoint->orig_instr);
1675  if (retval != ERROR_OK)
1676  return retval;
1677  } else {
1678  retval = target_write_memory(target,
1679  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1680  2, 1, breakpoint->orig_instr);
1681  if (retval != ERROR_OK)
1682  return retval;
1683  }
1684 
1685  armv8_cache_d_inner_flush_virt(armv8,
1686  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1687  breakpoint->length);
1688 
1689  armv8_cache_i_inner_inval_virt(armv8,
1690  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1691  breakpoint->length);
1692  }
1693  breakpoint->is_set = false;
1694 
1695  return ERROR_OK;
1696 }
1697 
1698 static int aarch64_add_breakpoint(struct target *target,
1699  struct breakpoint *breakpoint)
1700 {
1701  struct aarch64_common *aarch64 = target_to_aarch64(target);
1702 
1703  if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1704  LOG_INFO("no hardware breakpoint available");
1705  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1706  }
1707 
1708  if (breakpoint->type == BKPT_HARD)
1709  aarch64->brp_num_available--;
1710 
1711  return aarch64_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1712 }
1713 
1714 static int aarch64_add_context_breakpoint(struct target *target,
1715  struct breakpoint *breakpoint)
1716 {
1717  struct aarch64_common *aarch64 = target_to_aarch64(target);
1718 
1719  if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1720  LOG_INFO("no hardware breakpoint available");
1721  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1722  }
1723 
1724  if (breakpoint->type == BKPT_HARD)
1725  aarch64->brp_num_available--;
1726 
1727  return aarch64_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */
1728 }
1729 
1730 static int aarch64_add_hybrid_breakpoint(struct target *target,
1731  struct breakpoint *breakpoint)
1732 {
1733  struct aarch64_common *aarch64 = target_to_aarch64(target);
1734 
1735  if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1736  LOG_INFO("no hardware breakpoint available");
1737  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1738  }
1739 
1740  if (breakpoint->type == BKPT_HARD)
1741  aarch64->brp_num_available--;
1742 
1743  return aarch64_set_hybrid_breakpoint(target, breakpoint); /* ??? */
1744 }
1745 
1746 static int aarch64_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1747 {
1748  struct aarch64_common *aarch64 = target_to_aarch64(target);
1749 
1750 #if 0
1751 /* It is perfectly possible to remove breakpoints while the target is running */
1752  if (target->state != TARGET_HALTED) {
1753  LOG_WARNING("target not halted");
1754  return ERROR_TARGET_NOT_HALTED;
1755  }
1756 #endif
1757 
1758  if (breakpoint->is_set) {
1759  aarch64_unset_breakpoint(target, breakpoint);
1760  if (breakpoint->type == BKPT_HARD)
1761  aarch64->brp_num_available++;
1762  }
1763 
1764  return ERROR_OK;
1765 }
1766 
1767 /* Setup hardware Watchpoint Register Pair */
1768 static int aarch64_set_watchpoint(struct target *target,
1769  struct watchpoint *watchpoint)
1770 {
1771  int retval;
1772  int wp_i = 0;
1773  uint32_t control, offset, length;
1774  struct aarch64_common *aarch64 = target_to_aarch64(target);
1775  struct armv8_common *armv8 = &aarch64->armv8_common;
1776  struct aarch64_brp *wp_list = aarch64->wp_list;
1777 
1778  if (watchpoint->is_set) {
1779  LOG_WARNING("watchpoint already set");
1780  return ERROR_OK;
1781  }
1782 
1783  while (wp_list[wp_i].used && (wp_i < aarch64->wp_num))
1784  wp_i++;
1785  if (wp_i >= aarch64->wp_num) {
1786  LOG_ERROR("ERROR Can not find free Watchpoint Register Pair");
1787  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1788  }
1789 
1790  control = (1 << 0) /* enable */
1791  | (3 << 1) /* both user and privileged access */
1792  | (1 << 13); /* higher mode control */
1793 
1794  switch (watchpoint->rw) {
1795  case WPT_READ:
1796  control |= 1 << 3;
1797  break;
1798  case WPT_WRITE:
1799  control |= 2 << 3;
1800  break;
1801  case WPT_ACCESS:
1802  control |= 3 << 3;
1803  break;
1804  }
1805 
1806  /* Match up to 8 bytes. */
1807  offset = watchpoint->address & 7;
1808  length = watchpoint->length;
1809  if (offset + length > sizeof(uint64_t)) {
1810  length = sizeof(uint64_t) - offset;
1811  LOG_WARNING("Adjust watchpoint match inside 8-byte boundary");
1812  }
1813  for (; length > 0; offset++, length--)
1814  control |= (1 << offset) << 5;
1815 
1816  wp_list[wp_i].value = watchpoint->address & 0xFFFFFFFFFFFFFFF8ULL;
1817  wp_list[wp_i].control = control;
1818 
1819  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1820  + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn,
1821  (uint32_t)(wp_list[wp_i].value & 0xFFFFFFFF));
1822  if (retval != ERROR_OK)
1823  return retval;
1824  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1825  + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn,
1826  (uint32_t)(wp_list[wp_i].value >> 32));
1827  if (retval != ERROR_OK)
1828  return retval;
1829 
1830  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1831  + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn,
1832  control);
1833  if (retval != ERROR_OK)
1834  return retval;
1835  LOG_DEBUG("wp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, wp_i,
1836  wp_list[wp_i].control, wp_list[wp_i].value);
1837 
1838  /* Ensure that halting debug mode is enable */
1839  retval = aarch64_set_dscr_bits(target, DSCR_HDE, DSCR_HDE);
1840  if (retval != ERROR_OK) {
1841  LOG_DEBUG("Failed to set DSCR.HDE");
1842  return retval;
1843  }
1844 
1845  wp_list[wp_i].used = 1;
1846  watchpoint_set(watchpoint, wp_i);
1847 
1848  return ERROR_OK;
1849 }
1850 
1851 /* Clear hardware Watchpoint Register Pair */
1852 static int aarch64_unset_watchpoint(struct target *target,
1853  struct watchpoint *watchpoint)
1854 {
1855  int retval;
1856  struct aarch64_common *aarch64 = target_to_aarch64(target);
1857  struct armv8_common *armv8 = &aarch64->armv8_common;
1858  struct aarch64_brp *wp_list = aarch64->wp_list;
1859 
1860  if (!watchpoint->is_set) {
1861  LOG_WARNING("watchpoint not set");
1862  return ERROR_OK;
1863  }
1864 
1865  int wp_i = watchpoint->number;
1866  if (wp_i >= aarch64->wp_num) {
1867  LOG_DEBUG("Invalid WP number in watchpoint");
1868  return ERROR_OK;
1869  }
1870  LOG_DEBUG("rwp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, wp_i,
1871  wp_list[wp_i].control, wp_list[wp_i].value);
1872  wp_list[wp_i].used = 0;
1873  wp_list[wp_i].value = 0;
1874  wp_list[wp_i].control = 0;
1875  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1876  + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn,
1877  wp_list[wp_i].control);
1878  if (retval != ERROR_OK)
1879  return retval;
1880  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1881  + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn,
1882  wp_list[wp_i].value);
1883  if (retval != ERROR_OK)
1884  return retval;
1885 
1886  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1887  + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn,
1888  (uint32_t)wp_list[wp_i].value);
1889  if (retval != ERROR_OK)
1890  return retval;
1891  watchpoint->is_set = false;
1892 
1893  return ERROR_OK;
1894 }
1895 
1896 static int aarch64_add_watchpoint(struct target *target,
1897  struct watchpoint *watchpoint)
1898 {
1899  int retval;
1900  struct aarch64_common *aarch64 = target_to_aarch64(target);
1901 
1902  if (aarch64->wp_num_available < 1) {
1903  LOG_INFO("no hardware watchpoint available");
1904  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1905  }
1906 
1907  retval = aarch64_set_watchpoint(target, watchpoint);
1908  if (retval == ERROR_OK)
1909  aarch64->wp_num_available--;
1910 
1911  return retval;
1912 }
1913 
1914 static int aarch64_remove_watchpoint(struct target *target,
1915  struct watchpoint *watchpoint)
1916 {
1917  struct aarch64_common *aarch64 = target_to_aarch64(target);
1918 
1919  if (watchpoint->is_set) {
1920  aarch64_unset_watchpoint(target, watchpoint);
1921  aarch64->wp_num_available++;
1922  }
1923 
1924  return ERROR_OK;
1925 }
1926 
1931 static int aarch64_hit_watchpoint(struct target *target,
1932  struct watchpoint **hit_watchpoint)
1933 {
1934  if (target->debug_reason != DBG_REASON_WATCHPOINT)
1935  return ERROR_FAIL;
1936 
1937  struct armv8_common *armv8 = target_to_armv8(target);
1938 
1939  target_addr_t exception_address;
1940  struct watchpoint *wp;
1941 
1942  exception_address = armv8->dpm.wp_addr;
1943 
1944  if (exception_address == 0xFFFFFFFF)
1945  return ERROR_FAIL;
1946 
1947  for (wp = target->watchpoints; wp; wp = wp->next)
1948  if (exception_address >= wp->address && exception_address < (wp->address + wp->length)) {
1949  *hit_watchpoint = wp;
1950  return ERROR_OK;
1951  }
1952 
1953  return ERROR_FAIL;
1954 }
1955 
1956 /*
1957  * Cortex-A8 Reset functions
1958  */
1959 
1960 static int aarch64_enable_reset_catch(struct target *target, bool enable)
1961 {
1962  struct armv8_common *armv8 = target_to_armv8(target);
1963  uint32_t edecr;
1964  int retval;
1965 
1966  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1967  armv8->debug_base + CPUV8_DBG_EDECR, &edecr);
1968  LOG_DEBUG("EDECR = 0x%08" PRIx32 ", enable=%d", edecr, enable);
1969  if (retval != ERROR_OK)
1970  return retval;
1971 
1972  if (enable)
1973  edecr |= ECR_RCE;
1974  else
1975  edecr &= ~ECR_RCE;
1976 
1977  return mem_ap_write_atomic_u32(armv8->debug_ap,
1978  armv8->debug_base + CPUV8_DBG_EDECR, edecr);
1979 }
1980 
1981 static int aarch64_clear_reset_catch(struct target *target)
1982 {
1983  struct armv8_common *armv8 = target_to_armv8(target);
1984  uint32_t edesr;
1985  int retval;
1986  bool was_triggered;
1987 
1988  /* check if Reset Catch debug event triggered as expected */
1989  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1990  armv8->debug_base + CPUV8_DBG_EDESR, &edesr);
1991  if (retval != ERROR_OK)
1992  return retval;
1993 
1994  was_triggered = !!(edesr & ESR_RC);
1995  LOG_DEBUG("Reset Catch debug event %s",
1996  was_triggered ? "triggered" : "NOT triggered!");
1997 
1998  if (was_triggered) {
1999  /* clear pending Reset Catch debug event */
2000  edesr &= ~ESR_RC;
2001  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2002  armv8->debug_base + CPUV8_DBG_EDESR, edesr);
2003  if (retval != ERROR_OK)
2004  return retval;
2005  }
2006 
2007  return ERROR_OK;
2008 }
2009 
2010 static int aarch64_assert_reset(struct target *target)
2011 {
2012  struct armv8_common *armv8 = target_to_armv8(target);
2013  enum reset_types reset_config = jtag_get_reset_config();
2014  int retval;
2015 
2016  LOG_DEBUG(" ");
2017 
2018  /* Issue some kind of warm reset. */
2019  if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
2020  target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
2021  else if (reset_config & RESET_HAS_SRST) {
2022  bool srst_asserted = false;
2023 
2024  if (target->reset_halt && !(reset_config & RESET_SRST_PULLS_TRST)) {
2025  if (target_was_examined(target)) {
2026 
2027  if (reset_config & RESET_SRST_NO_GATING) {
2028  /*
2029  * SRST needs to be asserted *before* Reset Catch
2030  * debug event can be set up.
2031  */
2032  adapter_assert_reset();
2033  srst_asserted = true;
2034  }
2035 
2036  /* make sure to clear all sticky errors */
2037  mem_ap_write_atomic_u32(armv8->debug_ap,
2038  armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
2039 
2040  /* set up Reset Catch debug event to halt the CPU after reset */
2041  retval = aarch64_enable_reset_catch(target, true);
2042  if (retval != ERROR_OK)
2043  LOG_WARNING("%s: Error enabling Reset Catch debug event; the CPU will not halt immediately after reset!",
2044  target_name(target));
2045  } else {
2046  LOG_WARNING("%s: Target not examined, will not halt immediately after reset!",
2047  target_name(target));
2048  }
2049  }
2050 
2051  /* REVISIT handle "pulls" cases, if there's
2052  * hardware that needs them to work.
2053  */
2054  if (!srst_asserted)
2055  adapter_assert_reset();
2056  } else {
2057  LOG_ERROR("%s: how to reset?", target_name(target));
2058  return ERROR_FAIL;
2059  }
2060 
2061  /* registers are now invalid */
2062  if (armv8->arm.core_cache) {
2063  register_cache_invalidate(armv8->arm.core_cache);
2064  register_cache_invalidate(armv8->arm.core_cache->next);
2065  }
2066 
2067  target->state = TARGET_RESET;
2068 
2069  return ERROR_OK;
2070 }
2071 
2072 static int aarch64_deassert_reset(struct target *target)
2073 {
2074  int retval;
2075 
2076  LOG_DEBUG(" ");
2077 
2078  /* be certain SRST is off */
2079  adapter_deassert_reset();
2080 
2081  if (!target_was_examined(target))
2082  return ERROR_OK;
2083 
2084  retval = aarch64_init_debug_access(target);
2085  if (retval != ERROR_OK)
2086  return retval;
2087 
2088  retval = aarch64_poll(target);
2089  if (retval != ERROR_OK)
2090  return retval;
2091 
2092  if (target->reset_halt) {
2093  /* clear pending Reset Catch debug event */
2094  retval = aarch64_clear_reset_catch(target);
2095  if (retval != ERROR_OK)
2096  LOG_WARNING("%s: Clearing Reset Catch debug event failed",
2097  target_name(target));
2098 
2099  /* disable Reset Catch debug event */
2100  retval = aarch64_enable_reset_catch(target, false);
2101  if (retval != ERROR_OK)
2102  LOG_WARNING("%s: Disabling Reset Catch debug event failed",
2103  target_name(target));
2104 
2105  if (target->state != TARGET_HALTED) {
2106  LOG_WARNING("%s: ran after reset and before halt ...",
2107  target_name(target));
2108  if (target_was_examined(target)) {
2109  retval = aarch64_halt_one(target, HALT_LAZY);
2110  if (retval != ERROR_OK)
2111  return retval;
2112  } else {
2113  target->state = TARGET_UNKNOWN;
2114  }
2115  }
2116  }
2117 
2118  return ERROR_OK;
2119 }
2120 
2121 static int aarch64_write_cpu_memory_slow(struct target *target,
2122  uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2123 {
2124  struct armv8_common *armv8 = target_to_armv8(target);
2125  struct arm_dpm *dpm = &armv8->dpm;
2126  struct arm *arm = &armv8->arm;
2127  int retval;
2128 
2129  if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
2130  LOG_ERROR("memory write sizes greater than 4 bytes is only supported for AArch64 state");
2131  return ERROR_FAIL;
2132  }
2133 
2134  armv8_reg_current(arm, 1)->dirty = true;
2135 
2136  /* change DCC to normal mode if necessary */
2137  if (*dscr & DSCR_MA) {
2138  *dscr &= ~DSCR_MA;
2139  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2140  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2141  if (retval != ERROR_OK)
2142  return retval;
2143  }
2144 
2145  while (count) {
2146  uint32_t opcode;
2147  uint64_t data;
2148 
2149  /* write the data to store into DTRRX (and DTRTX for 64-bit) */
2150  if (size == 1)
2151  data = *buffer;
2152  else if (size == 2)
2153  data = target_buffer_get_u16(target, buffer);
2154  else if (size == 4)
2155  data = target_buffer_get_u32(target, buffer);
2156  else
2157  data = target_buffer_get_u64(target, buffer);
2158 
2159  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2160  armv8->debug_base + CPUV8_DBG_DTRRX, (uint32_t)data);
2161  if (retval == ERROR_OK && size > 4)
2162  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2163  armv8->debug_base + CPUV8_DBG_DTRTX, (uint32_t)(data >> 32));
2164  if (retval != ERROR_OK)
2165  return retval;
2166 
2167  if (arm->core_state == ARM_STATE_AARCH64)
2168  if (size <= 4)
2169  retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 1));
2170  else
2171  retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 1));
2172  else
2173  retval = dpm->instr_execute(dpm, ARMV4_5_MRC(14, 0, 1, 0, 5, 0));
2174  if (retval != ERROR_OK)
2175  return retval;
2176 
2177  if (size == 1)
2178  opcode = armv8_opcode(armv8, ARMV8_OPC_STRB_IP);
2179  else if (size == 2)
2180  opcode = armv8_opcode(armv8, ARMV8_OPC_STRH_IP);
2181  else if (size == 4)
2182  opcode = armv8_opcode(armv8, ARMV8_OPC_STRW_IP);
2183  else
2184  opcode = armv8_opcode(armv8, ARMV8_OPC_STRD_IP);
2185 
2186  retval = dpm->instr_execute(dpm, opcode);
2187  if (retval != ERROR_OK)
2188  return retval;
2189 
2190  /* Advance */
2191  buffer += size;
2192  --count;
2193  }
2194 
2195  return ERROR_OK;
2196 }
2197 
2198 static int aarch64_write_cpu_memory_fast(struct target *target,
2199  uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2200 {
2201  struct armv8_common *armv8 = target_to_armv8(target);
2202  struct arm *arm = &armv8->arm;
2203  int retval;
2204 
2205  armv8_reg_current(arm, 1)->dirty = true;
2206 
2207  /* Step 1.d - Change DCC to memory mode */
2208  *dscr |= DSCR_MA;
2209  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2210  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2211  if (retval != ERROR_OK)
2212  return retval;
2213 
2214 
2215  /* Step 2.a - Do the write */
2216  retval = mem_ap_write_buf_noincr(armv8->debug_ap,
2217  buffer, 4, count, armv8->debug_base + CPUV8_DBG_DTRRX);
2218  if (retval != ERROR_OK)
2219  return retval;
2220 
2221  /* Step 3.a - Switch DTR mode back to Normal mode */
2222  *dscr &= ~DSCR_MA;
2223  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2224  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2225  if (retval != ERROR_OK)
2226  return retval;
2227 
2228  return ERROR_OK;
2229 }
2230 
2231 static int aarch64_write_cpu_memory(struct target *target,
2232  uint64_t address, uint32_t size,
2233  uint32_t count, const uint8_t *buffer)
2234 {
2235  /* write memory through APB-AP */
2236  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2237  struct armv8_common *armv8 = target_to_armv8(target);
2238  struct arm_dpm *dpm = &armv8->dpm;
2239  struct arm *arm = &armv8->arm;
2240  uint32_t dscr;
2241 
2242  if (target->state != TARGET_HALTED) {
2243  LOG_TARGET_ERROR(target, "not halted");
2244  return ERROR_TARGET_NOT_HALTED;
2245  }
2246 
2247  /* Mark register X0 as dirty, as it will be used
2248  * for transferring the data.
2249  * It will be restored automatically when exiting
2250  * debug mode
2251  */
2252  armv8_reg_current(arm, 0)->dirty = true;
2253 
2254  /* This algorithm comes from DDI0487A.g, chapter J9.1 */
2255 
2256  /* Read DSCR */
2257  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2258  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2259  if (retval != ERROR_OK)
2260  return retval;
2261 
2262  /* Set Normal access mode */
2263  dscr = (dscr & ~DSCR_MA);
2264  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2265  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2266  if (retval != ERROR_OK)
2267  return retval;
2268 
2269  if (arm->core_state == ARM_STATE_AARCH64) {
2270  /* Write X0 with value 'address' using write procedure */
2271  /* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
2272  /* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
2273  retval = dpm->instr_write_data_dcc_64(dpm,
2274  ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), address);
2275  } else {
2276  /* Write R0 with value 'address' using write procedure */
2277  /* Step 1.a+b - Write the address for read access into DBGDTRRX */
2278  /* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
2279  retval = dpm->instr_write_data_dcc(dpm,
2280  ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
2281  }
2282 
2283  if (retval != ERROR_OK)
2284  return retval;
2285 
2286  if (size == 4 && (address % 4) == 0)
2287  retval = aarch64_write_cpu_memory_fast(target, count, buffer, &dscr);
2288  else
2289  retval = aarch64_write_cpu_memory_slow(target, size, count, buffer, &dscr);
2290 
2291  if (retval != ERROR_OK) {
2292  /* Unset DTR mode */
2293  mem_ap_read_atomic_u32(armv8->debug_ap,
2294  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2295  dscr &= ~DSCR_MA;
2296  mem_ap_write_atomic_u32(armv8->debug_ap,
2297  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2298  }
2299 
2300  /* Check for sticky abort flags in the DSCR */
2301  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2302  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2303  if (retval != ERROR_OK)
2304  return retval;
2305 
2306  dpm->dscr = dscr;
2307  if (dscr & (DSCR_ERR | DSCR_SYS_ERROR_PEND)) {
2308  /* Abort occurred - clear it and exit */
2309  LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
2310  armv8_dpm_handle_exception(dpm, true);
2311  return ERROR_FAIL;
2312  }
2313 
2314  /* Done */
2315  return ERROR_OK;
2316 }
2317 
2318 static int aarch64_read_cpu_memory_slow(struct target *target,
2319  uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
2320 {
2321  struct armv8_common *armv8 = target_to_armv8(target);
2322  struct arm_dpm *dpm = &armv8->dpm;
2323  struct arm *arm = &armv8->arm;
2324  int retval;
2325 
2326  if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
2327  LOG_ERROR("memory read sizes greater than 4 bytes is only supported for AArch64 state");
2328  return ERROR_FAIL;
2329  }
2330 
2331  armv8_reg_current(arm, 1)->dirty = true;
2332 
2333  /* change DCC to normal mode (if necessary) */
2334  if (*dscr & DSCR_MA) {
2335  *dscr &= DSCR_MA;
2336  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2337  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2338  if (retval != ERROR_OK)
2339  return retval;
2340  }
2341 
2342  while (count) {
2343  uint32_t opcode;
2344  uint32_t lower;
2345  uint32_t higher;
2346  uint64_t data;
2347 
2348  if (size == 1)
2349  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRB_IP);
2350  else if (size == 2)
2351  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRH_IP);
2352  else if (size == 4)
2353  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRW_IP);
2354  else
2355  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRD_IP);
2356 
2357  retval = dpm->instr_execute(dpm, opcode);
2358  if (retval != ERROR_OK)
2359  return retval;
2360 
2361  if (arm->core_state == ARM_STATE_AARCH64)
2362  if (size <= 4)
2363  retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 1));
2364  else
2365  retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 1));
2366  else
2367  retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 1, 0, 5, 0));
2368  if (retval != ERROR_OK)
2369  return retval;
2370 
2371  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2372  armv8->debug_base + CPUV8_DBG_DTRTX, &lower);
2373  if (retval == ERROR_OK) {
2374  if (size > 4)
2375  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2376  armv8->debug_base + CPUV8_DBG_DTRRX, &higher);
2377  else
2378  higher = 0;
2379  }
2380  if (retval != ERROR_OK)
2381  return retval;
2382 
2383  data = (uint64_t)lower | (uint64_t)higher << 32;
2384 
2385  if (size == 1)
2386  *buffer = (uint8_t)data;
2387  else if (size == 2)
2388  target_buffer_set_u16(target, buffer, (uint16_t)data);
2389  else if (size == 4)
2390  target_buffer_set_u32(target, buffer, (uint32_t)data);
2391  else
2392  target_buffer_set_u64(target, buffer, data);
2393 
2394  /* Advance */
2395  buffer += size;
2396  --count;
2397  }
2398 
2399  return ERROR_OK;
2400 }
2401 
2402 static int aarch64_read_cpu_memory_fast(struct target *target,
2403  uint32_t count, uint8_t *buffer, uint32_t *dscr)
2404 {
2405  struct armv8_common *armv8 = target_to_armv8(target);
2406  struct arm_dpm *dpm = &armv8->dpm;
2407  struct arm *arm = &armv8->arm;
2408  int retval;
2409  uint32_t value;
2410 
2411  /* Mark X1 as dirty */
2412  armv8_reg_current(arm, 1)->dirty = true;
2413 
2414  if (arm->core_state == ARM_STATE_AARCH64) {
2415  /* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
2416  retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0));
2417  } else {
2418  /* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
2419  retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
2420  }
2421 
2422  if (retval != ERROR_OK)
2423  return retval;
2424 
2425  /* Step 1.e - Change DCC to memory mode */
2426  *dscr |= DSCR_MA;
2427  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2428  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2429  if (retval != ERROR_OK)
2430  return retval;
2431 
2432  /* Step 1.f - read DBGDTRTX and discard the value */
2433  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2434  armv8->debug_base + CPUV8_DBG_DTRTX, &value);
2435  if (retval != ERROR_OK)
2436  return retval;
2437 
2438  count--;
2439  /* Read the data - Each read of the DTRTX register causes the instruction to be reissued
2440  * Abort flags are sticky, so can be read at end of transactions
2441  *
2442  * This data is read in aligned to 32 bit boundary.
2443  */
2444 
2445  if (count) {
2446  /* Step 2.a - Loop n-1 times, each read of DBGDTRTX reads the data from [X0] and
2447  * increments X0 by 4. */
2448  retval = mem_ap_read_buf_noincr(armv8->debug_ap, buffer, 4, count,
2449  armv8->debug_base + CPUV8_DBG_DTRTX);
2450  if (retval != ERROR_OK)
2451  return retval;
2452  }
2453 
2454  /* Step 3.a - set DTR access mode back to Normal mode */
2455  *dscr &= ~DSCR_MA;
2456  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2457  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2458  if (retval != ERROR_OK)
2459  return retval;
2460 
2461  /* Step 3.b - read DBGDTRTX for the final value */
2462  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2463  armv8->debug_base + CPUV8_DBG_DTRTX, &value);
2464  if (retval != ERROR_OK)
2465  return retval;
2466 
2467  target_buffer_set_u32(target, buffer + count * 4, value);
2468  return retval;
2469 }
2470 
2471 static int aarch64_read_cpu_memory(struct target *target,
2472  target_addr_t address, uint32_t size,
2473  uint32_t count, uint8_t *buffer)
2474 {
2475  /* read memory through APB-AP */
2476  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2477  struct armv8_common *armv8 = target_to_armv8(target);
2478  struct arm_dpm *dpm = &armv8->dpm;
2479  struct arm *arm = &armv8->arm;
2480  uint32_t dscr;
2481 
2482  LOG_DEBUG("Reading CPU memory address 0x%016" PRIx64 " size %" PRIu32 " count %" PRIu32,
2483  address, size, count);
2484 
2485  if (target->state != TARGET_HALTED) {
2486  LOG_TARGET_ERROR(target, "not halted");
2487  return ERROR_TARGET_NOT_HALTED;
2488  }
2489 
2490  /* Mark register X0 as dirty, as it will be used
2491  * for transferring the data.
2492  * It will be restored automatically when exiting
2493  * debug mode
2494  */
2495  armv8_reg_current(arm, 0)->dirty = true;
2496 
2497  /* Read DSCR */
2498  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2499  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2500  if (retval != ERROR_OK)
2501  return retval;
2502 
2503  /* This algorithm comes from DDI0487A.g, chapter J9.1 */
2504 
2505  /* Set Normal access mode */
2506  dscr &= ~DSCR_MA;
2507  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2508  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2509  if (retval != ERROR_OK)
2510  return retval;
2511 
2512  if (arm->core_state == ARM_STATE_AARCH64) {
2513  /* Write X0 with value 'address' using write procedure */
2514  /* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
2515  /* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
2516  retval = dpm->instr_write_data_dcc_64(dpm,
2517  ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), address);
2518  } else {
2519  /* Write R0 with value 'address' using write procedure */
2520  /* Step 1.a+b - Write the address for read access into DBGDTRRXint */
2521  /* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
2522  retval = dpm->instr_write_data_dcc(dpm,
2523  ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
2524  }
2525 
2526  if (retval != ERROR_OK)
2527  return retval;
2528 
2529  if (size == 4 && (address % 4) == 0)
2530  retval = aarch64_read_cpu_memory_fast(target, count, buffer, &dscr);
2531  else
2532  retval = aarch64_read_cpu_memory_slow(target, size, count, buffer, &dscr);
2533 
2534  if (dscr & DSCR_MA) {
2535  dscr &= ~DSCR_MA;
2536  mem_ap_write_atomic_u32(armv8->debug_ap,
2537  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2538  }
2539 
2540  if (retval != ERROR_OK)
2541  return retval;
2542 
2543  /* Check for sticky abort flags in the DSCR */
2544  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2545  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2546  if (retval != ERROR_OK)
2547  return retval;
2548 
2549  dpm->dscr = dscr;
2550 
2551  if (dscr & (DSCR_ERR | DSCR_SYS_ERROR_PEND)) {
2552  /* Abort occurred - clear it and exit */
2553  LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
2554  armv8_dpm_handle_exception(dpm, true);
2555  return ERROR_FAIL;
2556  }
2557 
2558  /* Done */
2559  return ERROR_OK;
2560 }
2561 
2562 static int aarch64_read_phys_memory(struct target *target,
2563  target_addr_t address, uint32_t size,
2564  uint32_t count, uint8_t *buffer)
2565 {
2566  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2567 
2568  if (count && buffer) {
2569  /* read memory through APB-AP */
2570  retval = aarch64_mmu_modify(target, 0);
2571  if (retval != ERROR_OK)
2572  return retval;
2573  retval = aarch64_read_cpu_memory(target, address, size, count, buffer);
2574  }
2575  return retval;
2576 }
2577 
2578 static int aarch64_read_memory(struct target *target, target_addr_t address,
2579  uint32_t size, uint32_t count, uint8_t *buffer)
2580 {
2581  bool mmu_enabled = false;
2582  int retval;
2583 
2584  /* determine if MMU was enabled on target stop */
2585  retval = aarch64_mmu(target, &mmu_enabled);
2586  if (retval != ERROR_OK)
2587  return retval;
2588 
2589  if (mmu_enabled) {
2590  /* enable MMU as we could have disabled it for phys access */
2591  retval = aarch64_mmu_modify(target, 1);
2592  if (retval != ERROR_OK)
2593  return retval;
2594  }
2595  return aarch64_read_cpu_memory(target, address, size, count, buffer);
2596 }
2597 
2598 static int aarch64_write_phys_memory(struct target *target,
2599  target_addr_t address, uint32_t size,
2600  uint32_t count, const uint8_t *buffer)
2601 {
2602  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2603 
2604  if (count && buffer) {
2605  /* write memory through APB-AP */
2606  retval = aarch64_mmu_modify(target, 0);
2607  if (retval != ERROR_OK)
2608  return retval;
2609  return aarch64_write_cpu_memory(target, address, size, count, buffer);
2610  }
2611 
2612  return retval;
2613 }
2614 
2615 static int aarch64_write_memory(struct target *target, target_addr_t address,
2616  uint32_t size, uint32_t count, const uint8_t *buffer)
2617 {
2618  bool mmu_enabled = false;
2619  int retval;
2620 
2621  /* determine if MMU was enabled on target stop */
2622  retval = aarch64_mmu(target, &mmu_enabled);
2623  if (retval != ERROR_OK)
2624  return retval;
2625 
2626  if (mmu_enabled) {
2627  /* enable MMU as we could have disabled it for phys access */
2628  retval = aarch64_mmu_modify(target, 1);
2629  if (retval != ERROR_OK)
2630  return retval;
2631  }
2632  return aarch64_write_cpu_memory(target, address, size, count, buffer);
2633 }
2634 
2635 static int aarch64_handle_target_request(void *priv)
2636 {
2637  struct target *target = priv;
2638  struct armv8_common *armv8 = target_to_armv8(target);
2639  int retval;
2640 
2641  if (!target_was_examined(target))
2642  return ERROR_OK;
2643  if (!target->dbg_msg_enabled)
2644  return ERROR_OK;
2645 
2646  if (target->state == TARGET_RUNNING) {
2647  uint32_t request;
2648  uint32_t dscr;
2649  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2650  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2651 
2652  /* check if we have data */
2653  while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
2654  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2655  armv8->debug_base + CPUV8_DBG_DTRTX, &request);
2656  if (retval == ERROR_OK) {
2657  target_request(target, request);
2658  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2659  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2660  }
2661  }
2662  }
2663 
2664  return ERROR_OK;
2665 }
2666 
2667 static int aarch64_examine_first(struct target *target)
2668 {
2669  struct aarch64_common *aarch64 = target_to_aarch64(target);
2670  struct armv8_common *armv8 = &aarch64->armv8_common;
2671  struct adiv5_dap *swjdp = armv8->arm.dap;
2672  struct aarch64_private_config *pc = target->private_config;
2673  int i;
2674  int retval = ERROR_OK;
2675  uint64_t debug, ttypr;
2676  uint32_t cpuid;
2677  uint32_t tmp0, tmp1, tmp2, tmp3;
2678  debug = ttypr = cpuid = 0;
2679 
2680  if (!pc)
2681  return ERROR_FAIL;
2682 
2683  if (!armv8->debug_ap) {
2684  if (pc->adiv5_config.ap_num == DP_APSEL_INVALID) {
2685  /* Search for the APB-AB */
2686  retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap);
2687  if (retval != ERROR_OK) {
2688  LOG_ERROR("Could not find APB-AP for debug access");
2689  return retval;
2690  }
2691  } else {
2692  armv8->debug_ap = dap_get_ap(swjdp, pc->adiv5_config.ap_num);
2693  if (!armv8->debug_ap) {
2694  LOG_ERROR("Cannot get AP");
2695  return ERROR_FAIL;
2696  }
2697  }
2698  }
2699 
2700  retval = mem_ap_init(armv8->debug_ap);
2701  if (retval != ERROR_OK) {
2702  LOG_ERROR("Could not initialize the APB-AP");
2703  return retval;
2704  }
2705 
2706  armv8->debug_ap->memaccess_tck = 10;
2707 
2708  if (!target->dbgbase_set) {
2709  /* Lookup Processor DAP */
2710  retval = dap_lookup_cs_component(armv8->debug_ap, ARM_CS_C9_DEVTYPE_CORE_DEBUG,
2711  &armv8->debug_base, target->coreid);
2712  if (retval != ERROR_OK)
2713  return retval;
2714  LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT,
2715  target->coreid, armv8->debug_base);
2716  } else
2717  armv8->debug_base = target->dbgbase;
2718 
2719  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2720  armv8->debug_base + CPUV8_DBG_OSLAR, 0);
2721  if (retval != ERROR_OK) {
2722  LOG_DEBUG("Examine %s failed", "oslock");
2723  return retval;
2724  }
2725 
2726  retval = mem_ap_read_u32(armv8->debug_ap,
2727  armv8->debug_base + CPUV8_DBG_MAINID0, &cpuid);
2728  if (retval != ERROR_OK) {
2729  LOG_DEBUG("Examine %s failed", "CPUID");
2730  return retval;
2731  }
2732 
2733  retval = mem_ap_read_u32(armv8->debug_ap,
2734  armv8->debug_base + CPUV8_DBG_MEMFEATURE0, &tmp0);
2735  if (retval == ERROR_OK)
2736  retval = mem_ap_read_u32(armv8->debug_ap,
2737  armv8->debug_base + CPUV8_DBG_MEMFEATURE0 + 4, &tmp1);
2738  if (retval != ERROR_OK) {
2739  LOG_DEBUG("Examine %s failed", "Memory Model Type");
2740  return retval;
2741  }
2742  retval = mem_ap_read_u32(armv8->debug_ap,
2743  armv8->debug_base + CPUV8_DBG_DBGFEATURE0, &tmp2);
2744  if (retval == ERROR_OK)
2745  retval = mem_ap_read_u32(armv8->debug_ap,
2746  armv8->debug_base + CPUV8_DBG_DBGFEATURE0 + 4, &tmp3);
2747  if (retval != ERROR_OK) {
2748  LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
2749  return retval;
2750  }
2751 
2752  retval = dap_run(armv8->debug_ap->dap);
2753  if (retval != ERROR_OK) {
2754  LOG_ERROR("%s: examination failed\n", target_name(target));
2755  return retval;
2756  }
2757 
2758  ttypr |= tmp1;
2759  ttypr = (ttypr << 32) | tmp0;
2760  debug |= tmp3;
2761  debug = (debug << 32) | tmp2;
2762 
2763  LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
2764  LOG_DEBUG("ttypr = 0x%08" PRIx64, ttypr);
2765  LOG_DEBUG("debug = 0x%08" PRIx64, debug);
2766 
2767  if (!pc->cti) {
2768  LOG_TARGET_ERROR(target, "CTI not specified");
2769  return ERROR_FAIL;
2770  }
2771 
2772  armv8->cti = pc->cti;
2773 
2774  retval = aarch64_dpm_setup(aarch64, debug);
2775  if (retval != ERROR_OK)
2776  return retval;
2777 
2778  /* Setup Breakpoint Register Pairs */
2779  aarch64->brp_num = (uint32_t)((debug >> 12) & 0x0F) + 1;
2780  aarch64->brp_num_context = (uint32_t)((debug >> 28) & 0x0F) + 1;
2781  aarch64->brp_num_available = aarch64->brp_num;
2782  aarch64->brp_list = calloc(aarch64->brp_num, sizeof(struct aarch64_brp));
2783  for (i = 0; i < aarch64->brp_num; i++) {
2784  aarch64->brp_list[i].used = 0;
2785  if (i < (aarch64->brp_num-aarch64->brp_num_context))
2786  aarch64->brp_list[i].type = BRP_NORMAL;
2787  else
2788  aarch64->brp_list[i].type = BRP_CONTEXT;
2789  aarch64->brp_list[i].value = 0;
2790  aarch64->brp_list[i].control = 0;
2791  aarch64->brp_list[i].brpn = i;
2792  }
2793 
2794  /* Setup Watchpoint Register Pairs */
2795  aarch64->wp_num = (uint32_t)((debug >> 20) & 0x0F) + 1;
2796  aarch64->wp_num_available = aarch64->wp_num;
2797  aarch64->wp_list = calloc(aarch64->wp_num, sizeof(struct aarch64_brp));
2798  for (i = 0; i < aarch64->wp_num; i++) {
2799  aarch64->wp_list[i].used = 0;
2800  aarch64->wp_list[i].type = BRP_NORMAL;
2801  aarch64->wp_list[i].value = 0;
2802  aarch64->wp_list[i].control = 0;
2803  aarch64->wp_list[i].brpn = i;
2804  }
2805 
2806  LOG_DEBUG("Configured %i hw breakpoints, %i watchpoints",
2807  aarch64->brp_num, aarch64->wp_num);
2808 
2809  target->state = TARGET_UNKNOWN;
2810  target->debug_reason = DBG_REASON_NOTHALTED;
2811  aarch64->isrmasking_mode = AARCH64_ISRMASK_ON;
2812  target_set_examined(target);
2813  return ERROR_OK;
2814 }
2815 
2816 static int aarch64_examine(struct target *target)
2817 {
2818  int retval = ERROR_OK;
2819 
2820  /* don't re-probe hardware after each reset */
2821  if (!target_was_examined(target))
2822  retval = aarch64_examine_first(target);
2823 
2824  /* Configure core debug access */
2825  if (retval == ERROR_OK)
2826  retval = aarch64_init_debug_access(target);
2827 
2828  if (retval == ERROR_OK)
2829  retval = aarch64_poll(target);
2830 
2831  return retval;
2832 }
2833 
2834 /*
2835  * Cortex-A8 target creation and initialization
2836  */
2837 
2838 static int aarch64_init_target(struct command_context *cmd_ctx,
2839  struct target *target)
2840 {
2841  /* examine_first() does a bunch of this */
2842  arm_semihosting_init(target);
2843  return ERROR_OK;
2844 }
2845 
2846 static int aarch64_init_arch_info(struct target *target,
2847  struct aarch64_common *aarch64, struct adiv5_dap *dap)
2848 {
2849  struct armv8_common *armv8 = &aarch64->armv8_common;
2850 
2851  /* Setup struct aarch64_common */
2852  aarch64->common_magic = AARCH64_COMMON_MAGIC;
2853  armv8->arm.dap = dap;
2854 
2855  /* register arch-specific functions */
2856  armv8->examine_debug_reason = NULL;
2857  armv8->post_debug_entry = aarch64_post_debug_entry;
2858  armv8->pre_restore_context = NULL;
2859  armv8->armv8_mmu.read_physical_memory = aarch64_read_phys_memory;
2860 
2861  armv8_init_arch_info(target, armv8);
2862  target_register_timer_callback(aarch64_handle_target_request, 1,
2863  TARGET_TIMER_TYPE_PERIODIC, target);
2864 
2865  return ERROR_OK;
2866 }
2867 
2868 static int armv8r_target_create(struct target *target)
2869 {
2870  struct aarch64_private_config *pc = target->private_config;
2871  struct aarch64_common *aarch64;
2872 
2873  if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK)
2874  return ERROR_FAIL;
2875 
2876  aarch64 = calloc(1, sizeof(struct aarch64_common));
2877  if (!aarch64) {
2878  LOG_ERROR("Out of memory");
2879  return ERROR_FAIL;
2880  }
2881 
2882  aarch64->armv8_common.is_armv8r = true;
2883 
2884  return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap);
2885 }
2886 
2887 static int aarch64_target_create(struct target *target)
2888 {
2889  struct aarch64_private_config *pc = target->private_config;
2890  struct aarch64_common *aarch64;
2891 
2892  if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK)
2893  return ERROR_FAIL;
2894 
2895  aarch64 = calloc(1, sizeof(struct aarch64_common));
2896  if (!aarch64) {
2897  LOG_ERROR("Out of memory");
2898  return ERROR_FAIL;
2899  }
2900 
2901  aarch64->armv8_common.is_armv8r = false;
2902 
2903  return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap);
2904 }
2905 
2906 static void aarch64_deinit_target(struct target *target)
2907 {
2908  struct aarch64_common *aarch64 = target_to_aarch64(target);
2909  struct armv8_common *armv8 = &aarch64->armv8_common;
2910  struct arm_dpm *dpm = &armv8->dpm;
2911  uint64_t address;
2912 
2913  if (target->state == TARGET_HALTED) {
2914  // Restore the previous state of the target (gp registers, MMU, caches, etc)
2915  int retval = aarch64_restore_one(target, true, &address, false, false);
2916  if (retval != ERROR_OK)
2917  LOG_TARGET_ERROR(target, "Failed to restore target state");
2918  }
2919 
2920  if (armv8->debug_ap)
2921  dap_put_ap(armv8->debug_ap);
2922 
2923  armv8_free_reg_cache(target);
2924  free(aarch64->brp_list);
2925  free(dpm->dbp);
2926  free(dpm->dwp);
2927  free(target->private_config);
2928  free(aarch64);
2929 }
2930 
2931 static int aarch64_mmu(struct target *target, bool *enabled)
2932 {
2933  struct aarch64_common *aarch64 = target_to_aarch64(target);
2934  struct armv8_common *armv8 = &aarch64->armv8_common;
2935  if (target->state != TARGET_HALTED) {
2936  LOG_TARGET_ERROR(target, "not halted");
2937  return ERROR_TARGET_NOT_HALTED;
2938  }
2939  if (armv8->is_armv8r)
2940  *enabled = false;
2941  else
2942  *enabled = target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled;
2943  return ERROR_OK;
2944 }
2945 
2946 static int aarch64_virt2phys(struct target *target, target_addr_t virt,
2947  target_addr_t *phys)
2948 {
2949  return armv8_mmu_translate_va_pa(target, virt, phys, 1);
2950 }
2951 
2952 static int aarch64_insn_set(struct command_invocation *cmd,
2953  struct target *target, const char **insn_set)
2954 {
2955  if (target->state != TARGET_HALTED) {
2956  command_print(cmd, "[%s] not halted", target_name(target));
2957  return ERROR_TARGET_NOT_HALTED;
2958  }
2959 
2960  struct arm *arm = target_to_arm(target);
2961 
2962  switch (arm->core_state) {
2963  case ARM_STATE_AARCH64:
2964  if (target->endianness == TARGET_BIG_ENDIAN)
2965  *insn_set = "arm64be";
2966  else
2967  *insn_set = "arm64";
2968  break;
2969 
2970  case ARM_STATE_ARM:
2971  if (target->endianness == TARGET_BIG_ENDIAN)
2972  *insn_set = "armbe";
2973  else
2974  *insn_set = "arm";
2975  break;
2976 
2977  case ARM_STATE_THUMB:
2978  case ARM_STATE_THUMB_EE:
2979  *insn_set = "thumb";
2980  break;
2981 
2982  default:
2983  command_print(cmd, "[%s] unknown core_state %d", target_name(target),
2984  arm->core_state);
2985  return ERROR_FAIL;
2986  }
2987 
2988  return ERROR_OK;
2989 }
2990 
2991 /*
2992  * private target configuration items
2993  */
2994 enum aarch64_cfg_param {
2995  CFG_CTI,
2996 };
2997 
2998 static const struct jim_nvp nvp_config_opts[] = {
2999  { .name = "-cti", .value = CFG_CTI },
3000  { .name = NULL, .value = -1 }
3001 };
3002 
3003 static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *goi)
3004 {
3005  struct aarch64_private_config *pc;
3006  struct jim_nvp *n;
3007  int e;
3008 
3009  pc = (struct aarch64_private_config *)target->private_config;
3010  if (!pc) {
3011  pc = calloc(1, sizeof(struct aarch64_private_config));
3012  pc->adiv5_config.ap_num = DP_APSEL_INVALID;
3013  target->private_config = pc;
3014  }
3015 
3016  /*
3017  * Call adiv5_jim_configure() to parse the common DAP options
3018  * It will return JIM_CONTINUE if it didn't find any known
3019  * options, JIM_OK if it correctly parsed the topmost option
3020  * and JIM_ERR if an error occurred during parameter evaluation.
3021  * For JIM_CONTINUE, we check our own params.
3022  */
3023  e = adiv5_jim_configure_ext(target, goi, &pc->adiv5_config, ADI_CONFIGURE_DAP_COMPULSORY);
3024  if (e != JIM_CONTINUE)
3025  return e;
3026 
3027  /* parse config or cget options ... */
3028  if (goi->argc > 0) {
3029  Jim_SetEmptyResult(goi->interp);
3030 
3031  /* check first if topmost item is for us */
3032  e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts,
3033  goi->argv[0], &n);
3034  if (e != JIM_OK)
3035  return JIM_CONTINUE;
3036 
3037  e = jim_getopt_obj(goi, NULL);
3038  if (e != JIM_OK)
3039  return e;
3040 
3041  switch (n->value) {
3042  case CFG_CTI: {
3043  if (goi->is_configure) {
3044  Jim_Obj *o_cti;
3045  struct arm_cti *cti;
3046  e = jim_getopt_obj(goi, &o_cti);
3047  if (e != JIM_OK)
3048  return e;
3049  cti = cti_instance_by_jim_obj(goi->interp, o_cti);
3050  if (!cti) {
3051  Jim_SetResultString(goi->interp, "CTI name invalid!", -1);
3052  return JIM_ERR;
3053  }
3054  pc->cti = cti;
3055  } else {
3056  if (goi->argc != 0) {
3057  Jim_WrongNumArgs(goi->interp,
3058  goi->argc, goi->argv,
3059  "NO PARAMS");
3060  return JIM_ERR;
3061  }
3062 
3063  if (!pc || !pc->cti) {
3064  Jim_SetResultString(goi->interp, "CTI not configured", -1);
3065  return JIM_ERR;
3066  }
3067  Jim_SetResultString(goi->interp, arm_cti_name(pc->cti), -1);
3068  }
3069  break;
3070  }
3071 
3072  default:
3073  return JIM_CONTINUE;
3074  }
3075  }
3076 
3077  return JIM_OK;
3078 }
3079 
3080 COMMAND_HANDLER(aarch64_handle_cache_info_command)
3081 {
3082  struct target *target = get_current_target(CMD_CTX);
3083  struct armv8_common *armv8 = target_to_armv8(target);
3084 
3085  return armv8_handle_cache_info_command(CMD,
3086  &armv8->armv8_mmu.armv8_cache);
3087 }
3088 
3089 COMMAND_HANDLER(aarch64_handle_dbginit_command)
3090 {
3091  struct target *target = get_current_target(CMD_CTX);
3092  if (!target_was_examined(target)) {
3093  LOG_ERROR("target not examined yet");
3094  return ERROR_FAIL;
3095  }
3096 
3097  return aarch64_init_debug_access(target);
3098 }
3099 
3100 COMMAND_HANDLER(aarch64_mask_interrupts_command)
3101 {
3102  struct target *target = get_current_target(CMD_CTX);
3103  struct aarch64_common *aarch64 = target_to_aarch64(target);
3104 
3105  static const struct nvp nvp_maskisr_modes[] = {
3106  { .name = "off", .value = AARCH64_ISRMASK_OFF },
3107  { .name = "on", .value = AARCH64_ISRMASK_ON },
3108  { .name = NULL, .value = -1 },
3109  };
3110  const struct nvp *n;
3111 
3112  if (CMD_ARGC > 0) {
3113  n = nvp_name2value(nvp_maskisr_modes, CMD_ARGV[0]);
3114  if (!n->name) {
3115  LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]);
3116  return ERROR_COMMAND_SYNTAX_ERROR;
3117  }
3118 
3119  aarch64->isrmasking_mode = n->value;
3120  }
3121 
3122  n = nvp_value2name(nvp_maskisr_modes, aarch64->isrmasking_mode);
3123  command_print(CMD, "aarch64 interrupt mask %s", n->name);
3124 
3125  return ERROR_OK;
3126 }
3127 
3128 COMMAND_HANDLER(aarch64_mcrmrc_command)
3129 {
3130  bool is_mcr = false;
3131  unsigned int arg_cnt = 5;
3132 
3133  if (!strcmp(CMD_NAME, "mcr")) {
3134  is_mcr = true;
3135  arg_cnt = 6;
3136  }
3137 
3138  if (arg_cnt != CMD_ARGC)
3139  return ERROR_COMMAND_SYNTAX_ERROR;
3140 
3141  struct target *target = get_current_target(CMD_CTX);
3142  if (!target) {
3143  command_print(CMD, "no current target");
3144  return ERROR_FAIL;
3145  }
3146  if (!target_was_examined(target)) {
3147  command_print(CMD, "%s: not yet examined", target_name(target));
3148  return ERROR_TARGET_NOT_EXAMINED;
3149  }
3150 
3151  struct arm *arm = target_to_arm(target);
3152  if (!is_arm(arm)) {
3153  command_print(CMD, "%s: not an ARM", target_name(target));
3154  return ERROR_FAIL;
3155  }
3156 
3157  if (target->state != TARGET_HALTED) {
3158  command_print(CMD, "Error: [%s] not halted", target_name(target));
3159  return ERROR_TARGET_NOT_HALTED;
3160  }
3161 
3162  if (arm->core_state == ARM_STATE_AARCH64) {
3163  command_print(CMD, "%s: not 32-bit arm target", target_name(target));
3164  return ERROR_FAIL;
3165  }
3166 
3167  int cpnum;
3168  uint32_t op1;
3169  uint32_t op2;
3170  uint32_t crn;
3171  uint32_t crm;
3172  uint32_t value;
3173 
3174  /* NOTE: parameter sequence matches ARM instruction set usage:
3175  * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
3176  * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
3177  * The "rX" is necessarily omitted; it uses Tcl mechanisms.
3178  */
3179  COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum);
3180  if (cpnum & ~0xf) {
3181  command_print(CMD, "coprocessor %d out of range", cpnum);
3182  return ERROR_COMMAND_ARGUMENT_INVALID;
3183  }
3184 
3185  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1);
3186  if (op1 & ~0x7) {
3187  command_print(CMD, "op1 %d out of range", op1);
3188  return ERROR_COMMAND_ARGUMENT_INVALID;
3189  }
3190 
3191  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crn);
3192  if (crn & ~0xf) {
3193  command_print(CMD, "CRn %d out of range", crn);
3194  return ERROR_COMMAND_ARGUMENT_INVALID;
3195  }
3196 
3197  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], crm);
3198  if (crm & ~0xf) {
3199  command_print(CMD, "CRm %d out of range", crm);
3200  return ERROR_COMMAND_ARGUMENT_INVALID;
3201  }
3202 
3203  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], op2);
3204  if (op2 & ~0x7) {
3205  command_print(CMD, "op2 %d out of range", op2);
3206  return ERROR_COMMAND_ARGUMENT_INVALID;
3207  }
3208 
3209  if (is_mcr) {
3210  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[5], value);
3211 
3212  /* NOTE: parameters reordered! */
3213  /* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */
3214  int retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value);
3215  if (retval != ERROR_OK)
3216  return retval;
3217  } else {
3218  value = 0;
3219  /* NOTE: parameters reordered! */
3220  /* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */
3221  int retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value);
3222  if (retval != ERROR_OK)
3223  return retval;
3224 
3225  command_print(CMD, "0x%" PRIx32, value);
3226  }
3227 
3228  return ERROR_OK;
3229 }
3230 
3231 static const struct command_registration aarch64_exec_command_handlers[] = {
3232  {
3233  .name = "cache_info",
3234  .handler = aarch64_handle_cache_info_command,
3235  .mode = COMMAND_EXEC,
3236  .help = "display information about target caches",
3237  .usage = "",
3238  },
3239  {
3240  .name = "dbginit",
3241  .handler = aarch64_handle_dbginit_command,
3242  .mode = COMMAND_EXEC,
3243  .help = "Initialize core debug",
3244  .usage = "",
3245  },
3246  {
3247  .name = "maskisr",
3248  .handler = aarch64_mask_interrupts_command,
3249  .mode = COMMAND_ANY,
3250  .help = "mask aarch64 interrupts during single-step",
3251  .usage = "['on'|'off']",
3252  },
3253  {
3254  .name = "mcr",
3255  .mode = COMMAND_EXEC,
3256  .handler = aarch64_mcrmrc_command,
3257  .help = "write coprocessor register",
3258  .usage = "cpnum op1 CRn CRm op2 value",
3259  },
3260  {
3261  .name = "mrc",
3262  .mode = COMMAND_EXEC,
3263  .handler = aarch64_mcrmrc_command,
3264  .help = "read coprocessor register",
3265  .usage = "cpnum op1 CRn CRm op2",
3266  },
3267  {
3268  .chain = smp_command_handlers,
3269  },
3270 
3271 
3272  COMMAND_REGISTRATION_DONE
3273 };
3274 
3275 static const struct command_registration aarch64_command_handlers[] = {
3276  {
3277  .name = "arm",
3278  .mode = COMMAND_ANY,
3279  .help = "ARM Command Group",
3280  .usage = "",
3281  .chain = semihosting_common_handlers
3282  },
3283  {
3284  .chain = armv8_command_handlers,
3285  },
3286  {
3287  .name = "aarch64",
3288  .mode = COMMAND_ANY,
3289  .help = "Aarch64 command group",
3290  .usage = "",
3291  .chain = aarch64_exec_command_handlers,
3292  },
3293  COMMAND_REGISTRATION_DONE
3294 };
3295 
3296 struct target_type aarch64_target = {
3297  .name = "aarch64",
3298 
3299  .poll = aarch64_poll,
3300  .arch_state = armv8_arch_state,
3301 
3302  .halt = aarch64_halt,
3303  .resume = aarch64_resume,
3304  .step = aarch64_step,
3305 
3306  .assert_reset = aarch64_assert_reset,
3307  .deassert_reset = aarch64_deassert_reset,
3308 
3309  /* REVISIT allow exporting VFP3 registers ... */
3310  .get_gdb_arch = armv8_get_gdb_arch,
3311  .get_gdb_reg_list = armv8_get_gdb_reg_list,
3312 
3313  .read_memory = aarch64_read_memory,
3314  .write_memory = aarch64_write_memory,
3315 
3316  .add_breakpoint = aarch64_add_breakpoint,
3317  .add_context_breakpoint = aarch64_add_context_breakpoint,
3318  .add_hybrid_breakpoint = aarch64_add_hybrid_breakpoint,
3319  .remove_breakpoint = aarch64_remove_breakpoint,
3320  .add_watchpoint = aarch64_add_watchpoint,
3321  .remove_watchpoint = aarch64_remove_watchpoint,
3322  .hit_watchpoint = aarch64_hit_watchpoint,
3323 
3324  .commands = aarch64_command_handlers,
3325  .target_create = aarch64_target_create,
3326  .target_jim_configure = aarch64_jim_configure,
3327  .init_target = aarch64_init_target,
3328  .deinit_target = aarch64_deinit_target,
3329  .examine = aarch64_examine,
3330 
3331  .read_phys_memory = aarch64_read_phys_memory,
3332  .write_phys_memory = aarch64_write_phys_memory,
3333  .mmu = aarch64_mmu,
3334  .virt2phys = aarch64_virt2phys,
3335 
3336  .insn_set = aarch64_insn_set,
3337 };
3338 
3339 struct target_type armv8r_target = {
3340  .name = "armv8r",
3341 
3342  .poll = aarch64_poll,
3343  .arch_state = armv8_arch_state,
3344 
3345  .halt = aarch64_halt,
3346  .resume = aarch64_resume,
3347  .step = aarch64_step,
3348 
3349  .assert_reset = aarch64_assert_reset,
3350  .deassert_reset = aarch64_deassert_reset,
3351 
3352  /* REVISIT allow exporting VFP3 registers ... */
3353  .get_gdb_arch = armv8_get_gdb_arch,
3354  .get_gdb_reg_list = armv8_get_gdb_reg_list,
3355 
3356  .read_memory = aarch64_read_phys_memory,
3357  .write_memory = aarch64_write_phys_memory,
3358 
3359  .add_breakpoint = aarch64_add_breakpoint,
3360  .add_context_breakpoint = aarch64_add_context_breakpoint,
3361  .add_hybrid_breakpoint = aarch64_add_hybrid_breakpoint,
3362  .remove_breakpoint = aarch64_remove_breakpoint,
3363  .add_watchpoint = aarch64_add_watchpoint,
3364  .remove_watchpoint = aarch64_remove_watchpoint,
3365  .hit_watchpoint = aarch64_hit_watchpoint,
3366 
3367  .commands = aarch64_command_handlers,
3368  .target_create = armv8r_target_create,
3369  .target_jim_configure = aarch64_jim_configure,
3370  .init_target = aarch64_init_target,
3371  .deinit_target = aarch64_deinit_target,
3372  .examine = aarch64_examine,
3373 
3374  .insn_set = aarch64_insn_set,
3375 };
aarch64_update_halt_gdb
static int aarch64_update_halt_gdb(struct target *target, enum target_debug_reason debug_reason)
Definition: aarch64.c:488
aarch64_write_cpu_memory_slow
static int aarch64_write_cpu_memory_slow(struct target *target, uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2121
aarch64_set_breakpoint
static int aarch64_set_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode)
Definition: aarch64.c:1307
aarch64_poll_smp
static int aarch64_poll_smp(struct target *target, bool smp, bool postpone_event)
Definition: aarch64.c:544
aarch64_unset_watchpoint
static int aarch64_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1852
aarch64_add_watchpoint
static int aarch64_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1896
COMMAND_HANDLER
COMMAND_HANDLER(aarch64_handle_cache_info_command)
Definition: aarch64.c:3080
aarch64_set_dscr_bits
static int aarch64_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
Definition: aarch64.c:304
aarch64_assert_reset
static int aarch64_assert_reset(struct target *target)
Definition: aarch64.c:2010
halt_mode
halt_mode
Definition: aarch64.c:31
HALT_SYNC
@ HALT_SYNC
Definition: aarch64.c:33
HALT_LAZY
@ HALT_LAZY
Definition: aarch64.c:32
aarch64_deinit_target
static void aarch64_deinit_target(struct target *target)
Definition: aarch64.c:2906
aarch64_add_context_breakpoint
static int aarch64_add_context_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1714
aarch64_write_phys_memory
static int aarch64_write_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: aarch64.c:2598
nvp_config_opts
static const struct jim_nvp nvp_config_opts[]
Definition: aarch64.c:2998
aarch64_examine
static int aarch64_examine(struct target *target)
Definition: aarch64.c:2816
aarch64_exec_command_handlers
static const struct command_registration aarch64_exec_command_handlers[]
Definition: aarch64.c:3231
aarch64_add_breakpoint
static int aarch64_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1698
aarch64_read_prsr
static int aarch64_read_prsr(struct target *target, uint32_t *prsr)
Definition: aarch64.c:196
aarch64_set_context_breakpoint
static int aarch64_set_context_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode)
Definition: aarch64.c:1428
aarch64_mmu_modify
static int aarch64_mmu_modify(struct target *target, int enable)
Definition: aarch64.c:123
aarch64_read_cpu_memory_fast
static int aarch64_read_cpu_memory_fast(struct target *target, uint32_t count, uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2402
aarch64_examine_first
static int aarch64_examine_first(struct target *target)
Definition: aarch64.c:2667
aarch64_poll
static int aarch64_poll(struct target *target)
Definition: aarch64.c:620
aarch64_init_target
static int aarch64_init_target(struct command_context *cmd_ctx, struct target *target)
Definition: aarch64.c:2838
aarch64_read_cpu_memory
static int aarch64_read_cpu_memory(struct target *target, uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: aarch64.c:2471
armv8r_target_create
static int armv8r_target_create(struct target *target)
Definition: aarch64.c:2868
aarch64_prepare_restart_one
static int aarch64_prepare_restart_one(struct target *target)
prepare single target for restart
Definition: aarch64.c:697
aarch64_step
static int aarch64_step(struct target *target, bool current, target_addr_t address, bool handle_breakpoints)
Definition: aarch64.c:1167
aarch64_restore_context
static int aarch64_restore_context(struct target *target, bool bpwp)
Definition: aarch64.c:1280
aarch64_enable_reset_catch
static int aarch64_enable_reset_catch(struct target *target, bool enable)
Definition: aarch64.c:1960
aarch64_jim_configure
static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *goi)
Definition: aarch64.c:3003
aarch64_mmu
static int aarch64_mmu(struct target *target, bool *enabled)
Definition: aarch64.c:2931
aarch64_halt
static int aarch64_halt(struct target *target)
Definition: aarch64.c:626
aarch64_restore_one
static int aarch64_restore_one(struct target *target, bool current, uint64_t *address, bool handle_breakpoints, bool debug_execution)
Definition: aarch64.c:637
aarch64_read_phys_memory
static int aarch64_read_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: aarch64.c:2562
aarch64_check_state_one
static int aarch64_check_state_one(struct target *target, uint32_t mask, uint32_t val, int *p_result, uint32_t *p_prsr)
Definition: aarch64.c:310
aarch64_restore_system_control_reg
static int aarch64_restore_system_control_reg(struct target *target)
Definition: aarch64.c:59
postponed_halt_events_op
postponed_halt_events_op
Definition: aarch64.c:518
POSTPONED_HALT_EVENT_CLEAR
@ POSTPONED_HALT_EVENT_CLEAR
Definition: aarch64.c:519
POSTPONED_HALT_EVENT_EMIT
@ POSTPONED_HALT_EVENT_EMIT
Definition: aarch64.c:520
aarch64_write_cpu_memory_fast
static int aarch64_write_cpu_memory_fast(struct target *target, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2198
aarch64_set_watchpoint
static int aarch64_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1768
aarch64_remove_watchpoint
static int aarch64_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1914
aarch64_restart_one
static int aarch64_restart_one(struct target *target, enum restart_mode mode)
Definition: aarch64.c:788
aarch64_step_restart_smp
static int aarch64_step_restart_smp(struct target *target)
Definition: aarch64.c:844
aarch64_dap_write_memap_register_u32
static int aarch64_dap_write_memap_register_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: aarch64.c:280
aarch64_debug_entry
static int aarch64_debug_entry(struct target *target)
Definition: aarch64.c:1024
aarch64_prep_restart_smp
static int aarch64_prep_restart_smp(struct target *target, bool handle_breakpoints, struct target **p_first)
Definition: aarch64.c:804
aarch64_insn_set
static int aarch64_insn_set(struct command_invocation *cmd, struct target *target, const char **insn_set)
Definition: aarch64.c:2952
aarch64_smp_postponed_halt_events
static void aarch64_smp_postponed_halt_events(struct list_head *smp_targets, enum postponed_halt_events_op op)
Definition: aarch64.c:523
aarch64_prepare_halt_smp
static int aarch64_prepare_halt_smp(struct target *target, bool exc_target, struct target **p_first)
Definition: aarch64.c:351
aarch64_target
struct target_type aarch64_target
Definition: aarch64.c:3296
aarch64_command_handlers
static const struct command_registration aarch64_command_handlers[]
Definition: aarch64.c:3275
aarch64_write_cpu_memory
static int aarch64_write_cpu_memory(struct target *target, uint64_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: aarch64.c:2231
aarch64_unset_breakpoint
static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1565
aarch64_virt2phys
static int aarch64_virt2phys(struct target *target, target_addr_t virt, target_addr_t *phys)
Definition: aarch64.c:2946
aarch64_handle_target_request
static int aarch64_handle_target_request(void *priv)
Definition: aarch64.c:2635
aarch64_clear_reset_catch
static int aarch64_clear_reset_catch(struct target *target)
Definition: aarch64.c:1981
aarch64_halt_one
static int aarch64_halt_one(struct target *target, enum halt_mode mode)
Definition: aarch64.c:396
aarch64_hit_watchpoint
static int aarch64_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
find out which watchpoint hits get exception address and compare the address to watchpoints
Definition: aarch64.c:1931
aarch64_cfg_param
aarch64_cfg_param
Definition: aarch64.c:2994
CFG_CTI
@ CFG_CTI
Definition: aarch64.c:2995
aarch64_deassert_reset
static int aarch64_deassert_reset(struct target *target)
Definition: aarch64.c:2072
aarch64_write_memory
static int aarch64_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: aarch64.c:2615
armv8r_target
struct target_type armv8r_target
Definition: aarch64.c:3339
aarch64_do_restart_one
static int aarch64_do_restart_one(struct target *target, enum restart_mode mode)
Definition: aarch64.c:743
aarch64_target_create
static int aarch64_target_create(struct target *target)
Definition: aarch64.c:2887
aarch64_dpm_setup
static int aarch64_dpm_setup(struct aarch64_common *a8, uint64_t debug)
Definition: aarch64.c:289
aarch64_add_hybrid_breakpoint
static int aarch64_add_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1730
aarch64_wait_halt_one
static int aarch64_wait_halt_one(struct target *target)
Definition: aarch64.c:329
aarch64_read_cpu_memory_slow
static int aarch64_read_cpu_memory_slow(struct target *target, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2318
aarch64_init_arch_info
static int aarch64_init_arch_info(struct target *target, struct aarch64_common *aarch64, struct adiv5_dap *dap)
Definition: aarch64.c:2846
aarch64_remove_breakpoint
static int aarch64_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1746
aarch64_resume
static int aarch64_resume(struct target *target, bool current, target_addr_t address, bool handle_breakpoints, bool debug_execution)
Definition: aarch64.c:917
aarch64_set_hybrid_breakpoint
static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1478
aarch64_read_memory
static int aarch64_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: aarch64.c:2578
restart_mode
restart_mode
Definition: aarch64.c:26
RESTART_SYNC
@ RESTART_SYNC
Definition: aarch64.c:28
RESTART_LAZY
@ RESTART_LAZY
Definition: aarch64.c:27
aarch64_halt_smp
static int aarch64_halt_smp(struct target *target, bool exc_target)
Definition: aarch64.c:425
aarch64_post_debug_entry
static int aarch64_post_debug_entry(struct target *target)
Definition: aarch64.c:1093
aarch64_init_debug_access
static int aarch64_init_debug_access(struct target *target)
Definition: aarch64.c:213
target_to_aarch64
static struct aarch64_common * target_to_aarch64(struct target *target)
Definition: aarch64.h:62
BRP_CONTEXT
#define BRP_CONTEXT
Definition: aarch64.h:21
AARCH64_ISRMASK_ON
@ AARCH64_ISRMASK_ON
Definition: aarch64.h:27
AARCH64_ISRMASK_OFF
@ AARCH64_ISRMASK_OFF
Definition: aarch64.h:26
BRP_NORMAL
#define BRP_NORMAL
Definition: aarch64.h:20
AARCH64_COMMON_MAGIC
#define AARCH64_COMMON_MAGIC
Definition: aarch64.h:12
armv8_get_gdb_arch
const char * armv8_get_gdb_arch(const struct target *target)
Definition: armv8.c:1988
armv8_reg_current
struct reg * armv8_reg_current(struct arm *arm, unsigned int regnum)
Definition: armv8.c:1923
armv8_get_gdb_reg_list
int armv8_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: armv8.c:1994
is_arm
static bool is_arm(struct arm *arm)
Definition: arm.h:268
arm_mode
arm_mode
Represent state of an ARM core.
Definition: arm.h:82
ARM_MODE_IRQ
@ ARM_MODE_IRQ
Definition: arm.h:85
ARM_MODE_SYS
@ ARM_MODE_SYS
Definition: arm.h:92
ARM_MODE_HYP
@ ARM_MODE_HYP
Definition: arm.h:89
ARMV8_64_EL0T
@ ARMV8_64_EL0T
Definition: arm.h:98
ARMV8_64_EL3H
@ ARMV8_64_EL3H
Definition: arm.h:104
ARM_MODE_MON
@ ARM_MODE_MON
Definition: arm.h:87
ARMV8_64_EL3T
@ ARMV8_64_EL3T
Definition: arm.h:103
ARM_MODE_FIQ
@ ARM_MODE_FIQ
Definition: arm.h:84
ARM_MODE_UND
@ ARM_MODE_UND
Definition: arm.h:90
ARM_MODE_ANY
@ ARM_MODE_ANY
Definition: arm.h:106
ARMV8_64_EL1H
@ ARMV8_64_EL1H
Definition: arm.h:100
ARM_MODE_SVC
@ ARM_MODE_SVC
Definition: arm.h:86
ARMV8_64_EL2H
@ ARMV8_64_EL2H
Definition: arm.h:102
ARMV8_64_EL2T
@ ARMV8_64_EL2T
Definition: arm.h:101
ARMV8_64_EL1T
@ ARMV8_64_EL1T
Definition: arm.h:99
ARM_MODE_ABT
@ ARM_MODE_ABT
Definition: arm.h:88
target_to_arm
static struct arm * target_to_arm(const struct target *target)
Convert target handle to generic ARM target state handle.
Definition: arm.h:262
arm_state
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
Definition: arm.h:151
ARM_STATE_JAZELLE
@ ARM_STATE_JAZELLE
Definition: arm.h:154
ARM_STATE_THUMB
@ ARM_STATE_THUMB
Definition: arm.h:153
ARM_STATE_ARM
@ ARM_STATE_ARM
Definition: arm.h:152
ARM_STATE_AARCH64
@ ARM_STATE_AARCH64
Definition: arm.h:156
ARM_STATE_THUMB_EE
@ ARM_STATE_THUMB_EE
Definition: arm.h:155
dap_lookup_cs_component
int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type, target_addr_t *addr, int32_t core_id)
Definition: arm_adi_v5.c:2320
mem_ap_read_buf_noincr
int mem_ap_read_buf_noincr(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:742
adiv5_verify_config
int adiv5_verify_config(struct adiv5_private_config *pc)
Definition: arm_adi_v5.c:2519
mem_ap_read_u32
int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Asynchronous (queued) read of a word from memory or a system register.
Definition: arm_adi_v5.c:245
mem_ap_write_buf_noincr
int mem_ap_write_buf_noincr(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:748
adiv5_jim_configure_ext
int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi, struct adiv5_private_config *pc, enum adiv5_configure_dap_optional optional)
Definition: arm_adi_v5.c:2474
mem_ap_read_atomic_u32
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
Definition: arm_adi_v5.c:274
dap_get_ap
struct adiv5_ap * dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1222
dap_put_ap
int dap_put_ap(struct adiv5_ap *ap)
Definition: arm_adi_v5.c:1242
mem_ap_init
int mem_ap_init(struct adiv5_ap *ap)
Initialize a DAP.
Definition: arm_adi_v5.c:896
mem_ap_write_atomic_u32
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
Definition: arm_adi_v5.c:326
dap_find_get_ap
static int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
Definition: arm_adi_v5.h:749
AP_TYPE_APB_AP
@ AP_TYPE_APB_AP
Definition: arm_adi_v5.h:491
ADI_CONFIGURE_DAP_COMPULSORY
@ ADI_CONFIGURE_DAP_COMPULSORY
Definition: arm_adi_v5.h:804
DP_APSEL_INVALID
#define DP_APSEL_INVALID
Definition: arm_adi_v5.h:110
dap_run
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
Definition: arm_adi_v5.h:648
arm_coresight.h
ARM_CS_LAR
#define ARM_CS_LAR
Definition: arm_coresight.h:29
ARM_CS_LSR
#define ARM_CS_LSR
Definition: arm_coresight.h:30
ARM_CS_C9_DEVTYPE_CORE_DEBUG
#define ARM_CS_C9_DEVTYPE_CORE_DEBUG
Definition: arm_coresight.h:97
ARM_CS_LSR_SLK
#define ARM_CS_LSR_SLK
Definition: arm_coresight.h:32
ARM_CS_LAR_UNLOCK_KEY
#define ARM_CS_LAR_UNLOCK_KEY
Definition: arm_coresight.h:35
ARM_CS_LSR_SLI
#define ARM_CS_LSR_SLI
Definition: arm_coresight.h:31
arm_cti_ack_events
int arm_cti_ack_events(struct arm_cti *self, uint32_t event)
Definition: arm_cti.c:96
arm_cti_write_reg
int arm_cti_write_reg(struct arm_cti *self, unsigned int reg, uint32_t value)
Definition: arm_cti.c:140
arm_cti_gate_channel
int arm_cti_gate_channel(struct arm_cti *self, uint32_t channel)
Definition: arm_cti.c:124
arm_cti_pulse_channel
int arm_cti_pulse_channel(struct arm_cti *self, uint32_t channel)
Definition: arm_cti.c:155
arm_cti_enable
int arm_cti_enable(struct arm_cti *self, bool enable)
Definition: arm_cti.c:87
arm_cti_name
const char * arm_cti_name(struct arm_cti *self)
Definition: arm_cti.c:31
cti_instance_by_jim_obj
struct arm_cti * cti_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o)
Definition: arm_cti.c:36
arm_cti_ungate_channel
int arm_cti_ungate_channel(struct arm_cti *self, uint32_t channel)
Definition: arm_cti.c:132
CTI_CHNL
#define CTI_CHNL(x)
Definition: arm_cti.h:44
CTI_GATE
#define CTI_GATE
Definition: arm_cti.h:41
CTI_TRIG
#define CTI_TRIG(n)
Definition: arm_cti.h:47
CTI_OUTEN0
#define CTI_OUTEN0
Definition: arm_cti.h:27
CTI_OUTEN1
#define CTI_OUTEN1
Definition: arm_cti.h:28
DSCR_DTR_TX_FULL
#define DSCR_DTR_TX_FULL
Definition: arm_dpm.h:194
ARMV4_5_MRC
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:186
ARMV4_5_MCR
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:209
arm_semihosting
int arm_semihosting(struct target *target, int *retval)
Checks for and processes an ARM semihosting request.
Definition: arm_semihosting.c:176
arm_semihosting_init
int arm_semihosting_init(struct target *target)
Initialize ARM semihosting support.
Definition: arm_semihosting.c:154
arm_semihosting.h
mode
enum arm_mode mode
Definition: armv4_5.c:280
armv8_init_arch_info
int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
Definition: armv8.c:1326
armv8_set_dbgreg_bits
int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
Definition: armv8.c:2056
armv8_read_mpidr
int armv8_read_mpidr(struct armv8_common *armv8)
Definition: armv8.c:887
armv8_free_reg_cache
void armv8_free_reg_cache(struct target *target)
Definition: armv8.c:1952
armv8_arch_state
int armv8_arch_state(struct target *target)
Definition: armv8.c:1366
armv8_mmu_translate_va_pa
int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, target_addr_t *val, int meminfo)
Definition: armv8.c:1143
armv8_command_handlers
const struct command_registration armv8_command_handlers[]
Definition: armv8.c:1966
armv8_select_reg_access
void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64)
Definition: armv8.c:870
armv8_mode_name
const char * armv8_mode_name(unsigned int psr_mode)
Map PSR mode bits to the name of an ARM processor operating mode.
Definition: armv8.c:108
armv8_handle_cache_info_command
int armv8_handle_cache_info_command(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
Definition: armv8.c:1308
armv8_identify_cache
int armv8_identify_cache(struct armv8_common *armv8)
Definition: armv8_cache.c:353
CPUV8_DBG_DRCR
#define CPUV8_DBG_DRCR
Definition: armv8.h:255
target_to_armv8
static struct armv8_common * target_to_armv8(struct target *target)
Definition: armv8.h:234
CPUV8_DBG_BVR_BASE
#define CPUV8_DBG_BVR_BASE
Definition: armv8.h:265
CPUV8_DBG_OSLAR
#define CPUV8_DBG_OSLAR
Definition: armv8.h:271
CPUV8_DBG_EDWAR0
#define CPUV8_DBG_EDWAR0
Definition: armv8.h:252
ARMV8_RUNCONTROL_HALT
@ ARMV8_RUNCONTROL_HALT
Definition: armv8.h:111
ARMV8_RUNCONTROL_RESUME
@ ARMV8_RUNCONTROL_RESUME
Definition: armv8.h:110
ARMV8_RUNCONTROL_STEP
@ ARMV8_RUNCONTROL_STEP
Definition: armv8.h:112
CPUV8_DBG_MAINID0
#define CPUV8_DBG_MAINID0
Definition: armv8.h:245
CPUV8_DBG_MEMFEATURE0
#define CPUV8_DBG_MEMFEATURE0
Definition: armv8.h:248
CPUV8_DBG_DSCR
#define CPUV8_DBG_DSCR
Definition: armv8.h:254
CPUV8_DBG_DTRTX
#define CPUV8_DBG_DTRTX
Definition: armv8.h:263
CPUV8_DBG_EDWAR1
#define CPUV8_DBG_EDWAR1
Definition: armv8.h:253
CPUV8_DBG_EDESR
#define CPUV8_DBG_EDESR
Definition: armv8.h:250
CPUV8_DBG_PRSR
#define CPUV8_DBG_PRSR
Definition: armv8.h:258
CPUV8_DBG_DBGFEATURE0
#define CPUV8_DBG_DBGFEATURE0
Definition: armv8.h:247
CPUV8_DBG_WVR_BASE
#define CPUV8_DBG_WVR_BASE
Definition: armv8.h:267
CPUV8_DBG_WCR_BASE
#define CPUV8_DBG_WCR_BASE
Definition: armv8.h:268
CPUV8_DBG_EDECR
#define CPUV8_DBG_EDECR
Definition: armv8.h:251
CPUV8_DBG_DTRRX
#define CPUV8_DBG_DTRRX
Definition: armv8.h:260
CPUV8_DBG_BCR_BASE
#define CPUV8_DBG_BCR_BASE
Definition: armv8.h:266
armv8_cache_d_inner_flush_virt
int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
Definition: armv8_cache.c:104
armv8_cache_i_inner_inval_virt
int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
Definition: armv8_cache.c:173
armv8_cache.h
armv8_dpm_report_dscr
void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
Definition: armv8_dpm.c:1357
armv8_dpm_write_dirty_registers
int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
Writes all modified core registers for all processor modes.
Definition: armv8_dpm.c:878
armv8_dpm_get_core_state
enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
Get core state from EDSCR, without necessity to retrieve CPSR.
Definition: armv8_dpm.c:41
armv8_dpm_read_current_registers
int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
Read basic registers of the current context: R0 to R15, and CPSR in AArch32 state or R0 to R31,...
Definition: armv8_dpm.c:740
armv8_dpm_initialize
int armv8_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
Definition: armv8_dpm.c:1489
armv8_dpm_modeswitch
int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
Definition: armv8_dpm.c:538
armv8_dpm_handle_exception
void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
Definition: armv8_dpm.c:1301
armv8_dpm_setup
int armv8_dpm_setup(struct arm_dpm *dpm)
Hooks up this DPM to its associated target; call only once.
Definition: armv8_dpm.c:1407
PRSR_RESET
#define PRSR_RESET
Definition: armv8_dpm.h:99
PRSR_SDR
#define PRSR_SDR
Definition: armv8_dpm.h:108
ESR_RC
#define ESR_RC
Definition: armv8_dpm.h:94
DSCR_MA
#define DSCR_MA
Definition: armv8_dpm.h:44
PRSR_HALT
#define PRSR_HALT
Definition: armv8_dpm.h:101
DRCR_CSE
#define DRCR_CSE
Definition: armv8_dpm.h:74
DSCR_HDE
#define DSCR_HDE
Definition: armv8_dpm.h:41
ECR_RCE
#define ECR_RCE
Definition: armv8_dpm.h:91
PRSR_SR
#define PRSR_SR
Definition: armv8_dpm.h:100
DSCR_SYS_ERROR_PEND
#define DSCR_SYS_ERROR_PEND
Definition: armv8_dpm.h:38
DSCR_ERR
#define DSCR_ERR
Definition: armv8_dpm.h:37
DSCR_ITE
#define DSCR_ITE
Definition: armv8_dpm.h:47
armv8_select_opcodes
void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)
Definition: armv8_opcodes.c:75
armv8_opcodes.h
ARMV8_HLT_T1
#define ARMV8_HLT_T1(im)
Definition: armv8_opcodes.h:150
SYSTEM_SCTLR_EL1
#define SYSTEM_SCTLR_EL1
Definition: armv8_opcodes.h:37
ARMV8_MSR_GP
#define ARMV8_MSR_GP(system, rt)
Definition: armv8_opcodes.h:136
SYSTEM_SCTLR_EL3
#define SYSTEM_SCTLR_EL3
Definition: armv8_opcodes.h:39
ARMV8_MRS
#define ARMV8_MRS(system, rt)
Definition: armv8_opcodes.h:134
ARMV8_HLT
#define ARMV8_HLT(im)
Definition: armv8_opcodes.h:148
armv8_opcode
armv8_opcode
Definition: armv8_opcodes.h:185
ARMV8_OPC_LDRD_IP
@ ARMV8_OPC_LDRD_IP
Definition: armv8_opcodes.h:211
ARMV8_OPC_LDRW_IP
@ ARMV8_OPC_LDRW_IP
Definition: armv8_opcodes.h:210
ARMV8_OPC_LDRB_IP
@ ARMV8_OPC_LDRB_IP
Definition: armv8_opcodes.h:208
ARMV8_OPC_LDRH_IP
@ ARMV8_OPC_LDRH_IP
Definition: armv8_opcodes.h:209
ARMV8_OPC_STRD_IP
@ ARMV8_OPC_STRD_IP
Definition: armv8_opcodes.h:207
ARMV8_OPC_STRH_IP
@ ARMV8_OPC_STRH_IP
Definition: armv8_opcodes.h:205
ARMV8_OPC_STRW_IP
@ ARMV8_OPC_STRW_IP
Definition: armv8_opcodes.h:206
ARMV8_OPC_STRB_IP
@ ARMV8_OPC_STRB_IP
Definition: armv8_opcodes.h:204
SYSTEM_SCTLR_EL2
#define SYSTEM_SCTLR_EL2
Definition: armv8_opcodes.h:38
SYSTEM_DBG_DTRTX_EL0
#define SYSTEM_DBG_DTRTX_EL0
Definition: armv8_opcodes.h:63
SYSTEM_DBG_DBGDTR_EL0
#define SYSTEM_DBG_DBGDTR_EL0
Definition: armv8_opcodes.h:64
SYSTEM_DBG_DTRRX_EL0
#define SYSTEM_DBG_DTRRX_EL0
Definition: armv8_opcodes.h:62
ARMV8_HLT_A1
#define ARMV8_HLT_A1(im)
Definition: armv8_opcodes.h:149
buf_set_u32
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
buf_get_u64
static uint64_t buf_get_u64(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 64-bit word.
Definition: binarybuffer.h:134
buf_set_u64
static void buf_set_u64(uint8_t *_buffer, unsigned int first, unsigned int num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:65
BKPT_HARD
@ BKPT_HARD
Definition: breakpoints.h:18
BKPT_SOFT
@ BKPT_SOFT
Definition: breakpoints.h:19
watchpoint_set
static void watchpoint_set(struct watchpoint *watchpoint, unsigned int number)
Definition: breakpoints.h:81
breakpoint_hw_set
static void breakpoint_hw_set(struct breakpoint *breakpoint, unsigned int hw_number)
Definition: breakpoints.h:65
WPT_ACCESS
@ WPT_ACCESS
Definition: breakpoints.h:23
WPT_READ
@ WPT_READ
Definition: breakpoints.h:23
WPT_WRITE
@ WPT_WRITE
Definition: breakpoints.h:23
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:389
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:146
CMD_NAME
#define CMD_NAME
Use this macro to access the name of the command being handled, rather than accessing the variable di...
Definition: command.h:171
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:161
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:405
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:156
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:445
CMD_CTX
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:151
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:256
ERROR_COMMAND_ARGUMENT_INVALID
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:407
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
halted
static int halted(struct target *target, const char *label)
Definition: davinci.c:58
buffer
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
size
uint32_t size
Size of dw_spi_transaction::buffer.
Definition: dw-spi-helper.h:4
address
uint32_t address
Starting address. Sector aligned.
Definition: dw-spi-helper.h:0
type
uint8_t type
Definition: esp_usb_jtag.c:0
priv
static struct esp_usb_jtag * priv
Definition: esp_usb_jtag.c:219
length
uint8_t length
Definition: esp_usb_jtag.c:1
jim_nvp_name2value_obj
int jim_nvp_name2value_obj(Jim_Interp *interp, const struct jim_nvp *p, Jim_Obj *o, struct jim_nvp **result)
Definition: jim-nvp.c:66
jim_getopt_obj
int jim_getopt_obj(struct jim_getopt_info *goi, Jim_Obj **puthere)
Remove argv[0] from the list.
Definition: jim-nvp.c:169
adapter_deassert_reset
int adapter_deassert_reset(void)
Definition: jtag/core.c:1911
jtag_get_reset_config
enum reset_types jtag_get_reset_config(void)
Definition: jtag/core.c:1746
adapter_assert_reset
int adapter_assert_reset(void)
Definition: jtag/core.c:1891
reset_types
reset_types
Definition: jtag.h:215
RESET_SRST_NO_GATING
@ RESET_SRST_NO_GATING
Definition: jtag.h:224
RESET_HAS_SRST
@ RESET_HAS_SRST
Definition: jtag.h:218
RESET_SRST_PULLS_TRST
@ RESET_SRST_PULLS_TRST
Definition: jtag.h:220
op
uint64_t op
Definition: lakemont.c:68
LOG_TARGET_INFO
#define LOG_TARGET_INFO(target, fmt_str,...)
Definition: log.h:167
LOG_WARNING
#define LOG_WARNING(expr ...)
Definition: log.h:144
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:188
LOG_TARGET_ERROR
#define LOG_TARGET_ERROR(target, fmt_str,...)
Definition: log.h:176
LOG_TARGET_DEBUG
#define LOG_TARGET_DEBUG(target, fmt_str,...)
Definition: log.h:164
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:147
LOG_INFO
#define LOG_INFO(expr ...)
Definition: log.h:141
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:124
ERROR_OK
#define ERROR_OK
Definition: log.h:182
nvp_name2value
const struct nvp * nvp_name2value(const struct nvp *p, const char *name)
Definition: nvp.c:29
nvp_value2name
const struct nvp * nvp_value2name(const struct nvp *p, int value)
Definition: nvp.c:39
mask
uint8_t mask
Definition: parport.c:70
register_cache_invalidate
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
Definition: register.c:94
addr
target_addr_t addr
Start address to search for the control block.
Definition: rtt/rtt.c:28
target
struct target * target
Definition: rtt/rtt.c:26
semihosting_common_handlers
const struct command_registration semihosting_common_handlers[]
Definition: semihosting_common.c:2116
smp_command_handlers
const struct command_registration smp_command_handlers[]
Definition: smp.c:150
foreach_smp_target
#define foreach_smp_target(pos, head)
Definition: smp.h:15
aarch64_brp
Definition: aarch64.h:30
aarch64_brp::brpn
uint8_t brpn
Definition: aarch64.h:35
aarch64_brp::value
target_addr_t value
Definition: aarch64.h:33
aarch64_brp::type
int type
Definition: aarch64.h:32
aarch64_brp::control
uint32_t control
Definition: aarch64.h:34
aarch64_brp::used
int used
Definition: aarch64.h:31
aarch64_common
Definition: aarch64.h:38
aarch64_common::common_magic
unsigned int common_magic
Definition: aarch64.h:39
aarch64_common::wp_num_available
int wp_num_available
Definition: aarch64.h:55
aarch64_common::wp_list
struct aarch64_brp * wp_list
Definition: aarch64.h:56
aarch64_common::brp_num_available
int brp_num_available
Definition: aarch64.h:50
aarch64_common::brp_num
int brp_num
Definition: aarch64.h:49
aarch64_common::system_control_reg_curr
uint64_t system_control_reg_curr
Definition: aarch64.h:45
aarch64_common::wp_num
int wp_num
Definition: aarch64.h:54
aarch64_common::armv8_common
struct armv8_common armv8_common
Definition: aarch64.h:41
aarch64_common::brp_list
struct aarch64_brp * brp_list
Definition: aarch64.h:51
aarch64_common::isrmasking_mode
enum aarch64_isrmasking_mode isrmasking_mode
Definition: aarch64.h:58
aarch64_common::system_control_reg
uint64_t system_control_reg
Definition: aarch64.h:44
aarch64_common::brp_num_context
int brp_num_context
Definition: aarch64.h:48
aarch64_private_config
Definition: aarch64.c:36
aarch64_private_config::cti
struct arm_cti * cti
Definition: aarch64.c:38
aarch64_private_config::adiv5_config
struct adiv5_private_config adiv5_config
Definition: aarch64.c:37
adiv5_ap::dap
struct adiv5_dap * dap
DAP this AP belongs to.
Definition: arm_adi_v5.h:254
adiv5_ap::memaccess_tck
uint32_t memaccess_tck
Configures how many extra tck clocks are added after starting a MEM-AP access before we try to read i...
Definition: arm_adi_v5.h:306
adiv5_dap
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
Definition: arm_adi_v5.h:348
adiv5_private_config
Definition: arm_adi_v5.h:796
adiv5_private_config::ap_num
uint64_t ap_num
Definition: arm_adi_v5.h:797
adiv5_private_config::dap
struct adiv5_dap * dap
Definition: arm_adi_v5.h:798
arm_cti
Definition: arm_cti.c:22
arm_dpm
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
arm_dpm::wp_addr
target_addr_t wp_addr
Target dependent watchpoint address.
Definition: arm_dpm.h:147
arm_dpm::didr
uint64_t didr
Cache of DIDR.
Definition: arm_dpm.h:51
arm_dpm::instr_write_data_r0_64
int(* instr_write_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:82
arm_dpm::instr_execute
int(* instr_execute)(struct arm_dpm *dpm, uint32_t opcode)
Runs one instruction.
Definition: arm_dpm.h:60
arm_dpm::instr_write_data_dcc_64
int(* instr_write_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Definition: arm_dpm.h:68
arm_dpm::arm
struct arm * arm
Definition: arm_dpm.h:48
arm_dpm::dbp
struct dpm_bp * dbp
Definition: arm_dpm.h:139
arm_dpm::instr_write_data_dcc
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
Definition: arm_dpm.h:65
arm_dpm::instr_read_data_r0_64
int(* instr_read_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Definition: arm_dpm.h:108
arm_dpm::dwp
struct dpm_wp * dwp
Definition: arm_dpm.h:140
arm_dpm::instr_cpsr_sync
int(* instr_cpsr_sync)(struct arm_dpm *dpm)
Optional core-specific operation invoked after CPSR writes.
Definition: arm_dpm.h:86
arm_dpm::dscr
uint32_t dscr
Recent value of DSCR.
Definition: arm_dpm.h:150
arm
Represents a generic ARM core, with standard application registers.
Definition: arm.h:176
arm::mrc
int(* mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Read coprocessor register.
Definition: arm.h:231
arm::core_mode
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
Definition: arm.h:197
arm::dap
struct adiv5_dap * dap
For targets conforming to ARM Debug Interface v5, this handle references the Debug Access Port (DAP) ...
Definition: arm.h:258
arm::pc
struct reg * pc
Handle to the PC; valid in all core modes.
Definition: arm.h:182
arm::core_cache
struct reg_cache * core_cache
Definition: arm.h:179
arm::dpm
struct arm_dpm * dpm
Handle for the debug module, if one is present.
Definition: arm.h:214
arm::mcr
int(* mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Write coprocessor register.
Definition: arm.h:242
arm::core_state
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
Definition: arm.h:200
armv8_cache_common::d_u_cache_enabled
bool d_u_cache_enabled
Definition: armv8.h:160
armv8_cache_common::info_valid
bool info_valid
Definition: armv8.h:154
armv8_cache_common::i_cache_enabled
bool i_cache_enabled
Definition: armv8.h:159
armv8_cache_common::flush_all_data_cache
int(* flush_all_data_cache)(struct target *target)
Definition: armv8.h:164
armv8_common
Definition: armv8.h:185
armv8_common::arm
struct arm arm
Definition: armv8.h:188
armv8_common::dpm
struct arm_dpm dpm
Definition: armv8.h:192
armv8_common::is_armv8r
bool is_armv8r
Definition: armv8.h:203
armv8_common::debug_base
target_addr_t debug_base
Definition: armv8.h:193
armv8_common::sticky_reset
bool sticky_reset
Definition: armv8.h:212
armv8_common::last_run_control_op
enum run_control_op last_run_control_op
Definition: armv8.h:215
armv8_common::armv8_mmu
struct armv8_mmu_common armv8_mmu
Definition: armv8.h:205
armv8_common::debug_ap
struct adiv5_ap * debug_ap
Definition: armv8.h:194
armv8_common::cti
struct arm_cti * cti
Definition: armv8.h:207
armv8_common::pre_restore_context
void(* pre_restore_context)(struct target *target)
Definition: armv8.h:230
armv8_common::examine_debug_reason
int(* examine_debug_reason)(struct target *target)
Definition: armv8.h:227
armv8_common::post_debug_entry
int(* post_debug_entry)(struct target *target)
Definition: armv8.h:228
armv8_mmu_common::read_physical_memory
int(* read_physical_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: armv8.h:179
armv8_mmu_common::armv8_cache
struct armv8_cache_common armv8_cache
Definition: armv8.h:181
armv8_mmu_common::mmu_enabled
bool mmu_enabled
Definition: armv8.h:182
breakpoint::linked_brp
int linked_brp
Definition: breakpoints.h:36
breakpoint::length
unsigned int length
Definition: breakpoints.h:29
breakpoint::orig_instr
uint8_t * orig_instr
Definition: breakpoints.h:33
breakpoint::type
enum breakpoint_type type
Definition: breakpoints.h:30
breakpoint::is_set
bool is_set
Definition: breakpoints.h:31
breakpoint::number
unsigned int number
Definition: breakpoints.h:32
breakpoint::asid
uint32_t asid
Definition: breakpoints.h:28
breakpoint::address
target_addr_t address
Definition: breakpoints.h:27
command_context
Definition: command.h:52
command_invocation
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
command_registration
Definition: command.h:238
command_registration::name
const char * name
Definition: command.h:239
command_registration::chain
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
Definition: command.h:252
jim_getopt_info
A TCL -ish GetOpt like code.
Definition: jim-nvp.h:136
jim_getopt_info::interp
Jim_Interp * interp
Definition: jim-nvp.h:137
jim_getopt_info::is_configure
bool is_configure
Definition: jim-nvp.h:140
jim_getopt_info::argc
int argc
Definition: jim-nvp.h:138
jim_getopt_info::argv
Jim_Obj *const * argv
Definition: jim-nvp.h:139
jim_nvp
Name Value Pairs, aka: NVP.
Definition: jim-nvp.h:60
jim_nvp::name
const char * name
Definition: jim-nvp.h:61
jim_nvp::value
int value
Definition: jim-nvp.h:62
list_head
Definition: list.h:41
nvp
Name Value Pairs, aka: NVP.
Definition: nvp.h:61
nvp::value
int value
Definition: nvp.h:63
nvp::name
const char * name
Definition: nvp.h:62
reg_cache::next
struct reg_cache * next
Definition: register.h:146
reg::valid
bool valid
Definition: register.h:126
reg::value
uint8_t * value
Definition: register.h:122
reg::dirty
bool dirty
Definition: register.h:124
target_list
Definition: target.h:225
target_list::target
struct target * target
Definition: target.h:227
target_type
This holds methods shared between all instances of a given target type.
Definition: target_type.h:27
target_type::name
const char * name
Name of this type of target.
Definition: target_type.h:32
target
Definition: target.h:119
target::coreid
int32_t coreid
Definition: target.h:123
target::dbgbase_set
bool dbgbase_set
Definition: target.h:184
target::dbg_msg_enabled
bool dbg_msg_enabled
Definition: target.h:173
target::debug_reason
enum target_debug_reason debug_reason
Definition: target.h:164
target::state
enum target_state state
Definition: target.h:167
target::dbgbase
uint32_t dbgbase
Definition: target.h:185
target::private_config
void * private_config
Definition: target.h:175
target::endianness
enum target_endianness endianness
Definition: target.h:165
target::smp_targets
struct list_head * smp_targets
Definition: target.h:201
target::smp
unsigned int smp
Definition: target.h:200
target::watchpoints
struct watchpoint * watchpoints
Definition: target.h:170
target::smp_halt_event_postponed
bool smp_halt_event_postponed
Definition: target.h:204
target::reset_halt
bool reset_halt
Definition: target.h:154
target::next
struct target * next
Definition: target.h:176
watchpoint::rw
enum watchpoint_rw rw
Definition: breakpoints.h:46
watchpoint::is_set
bool is_set
Definition: breakpoints.h:47
watchpoint::next
struct watchpoint * next
Definition: breakpoints.h:49
watchpoint::length
unsigned int length
Definition: breakpoints.h:43
watchpoint::number
unsigned int number
Definition: breakpoints.h:48
watchpoint::address
target_addr_t address
Definition: breakpoints.h:42
target_buffer_get_u64
uint64_t target_buffer_get_u64(struct target *target, const uint8_t *buffer)
Definition: target.c:318
target_call_event_callbacks
int target_call_event_callbacks(struct target *target, enum target_event event)
Definition: target.c:1816
target_free_all_working_areas
void target_free_all_working_areas(struct target *target)
Definition: target.c:2202
target_buffer_set_u16
void target_buffer_set_u16(struct target *target, uint8_t *buffer, uint16_t value)
Definition: target.c:381
target_buffer_set_u32
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
Definition: target.c:363
target_write_memory
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1289
target_register_timer_callback
int target_register_timer_callback(int(*callback)(void *priv), unsigned int time_ms, enum target_timer_type type, void *priv)
The period is very approximate, the callback can happen much more often or much more rarely than spec...
Definition: target.c:1701
target_buffer_set_u64
void target_buffer_set_u64(struct target *target, uint8_t *buffer, uint64_t value)
Definition: target.c:354
target_buffer_get_u16
uint16_t target_buffer_get_u16(struct target *target, const uint8_t *buffer)
Definition: target.c:345
target_read_memory
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1261
target_has_event_action
bool target_has_event_action(const struct target *target, enum target_event event)
Returns true only if the target has a handler for the specified event.
Definition: target.c:4877
get_current_target
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:469
target_handle_event
void target_handle_event(struct target *target, enum target_event e)
Definition: target.c:4691
target_buffer_get_u32
uint32_t target_buffer_get_u32(struct target *target, const uint8_t *buffer)
Definition: target.c:327
target_debug_reason
target_debug_reason
Definition: target.h:71
DBG_REASON_NOTHALTED
@ DBG_REASON_NOTHALTED
Definition: target.h:77
DBG_REASON_DBGRQ
@ DBG_REASON_DBGRQ
Definition: target.h:72
DBG_REASON_WATCHPOINT
@ DBG_REASON_WATCHPOINT
Definition: target.h:74
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:817
target_was_examined
static bool target_was_examined(const struct target *target)
Definition: target.h:443
TARGET_TIMER_TYPE_PERIODIC
@ TARGET_TIMER_TYPE_PERIODIC
Definition: target.h:333
TARGET_EVENT_DEBUG_RESUMED
@ TARGET_EVENT_DEBUG_RESUMED
Definition: target.h:285
TARGET_EVENT_HALTED
@ TARGET_EVENT_HALTED
Definition: target.h:265
TARGET_EVENT_RESUMED
@ TARGET_EVENT_RESUMED
Definition: target.h:266
TARGET_EVENT_DEBUG_HALTED
@ TARGET_EVENT_DEBUG_HALTED
Definition: target.h:284
TARGET_EVENT_RESET_ASSERT
@ TARGET_EVENT_RESET_ASSERT
Definition: target.h:277
target_name
static const char * target_name(const struct target *target)
Returns the instance-specific name of the specified target.
Definition: target.h:246
target_state
target_state
Definition: target.h:55
TARGET_RESET
@ TARGET_RESET
Definition: target.h:59
TARGET_DEBUG_RUNNING
@ TARGET_DEBUG_RUNNING
Definition: target.h:60
TARGET_UNKNOWN
@ TARGET_UNKNOWN
Definition: target.h:56
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:58
TARGET_RUNNING
@ TARGET_RUNNING
Definition: target.h:57
ERROR_TARGET_NOT_EXAMINED
#define ERROR_TARGET_NOT_EXAMINED
Definition: target.h:824
TARGET_BIG_ENDIAN
@ TARGET_BIG_ENDIAN
Definition: target.h:85
ERROR_TARGET_TIMEOUT
#define ERROR_TARGET_TIMEOUT
Definition: target.h:816
ERROR_TARGET_RESOURCE_NOT_AVAILABLE
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:821
target_set_examined
static void target_set_examined(struct target *target)
Sets the examined and active_polled flags for the given target.
Definition: target.h:460
target_request
int target_request(struct target *target, uint32_t request)
Definition: target_request.c:108
target_request.h
target_type.h
time_support.h
timeval_ms
int64_t timeval_ms(void)
Definition: time_support_common.c:34
TARGET_ADDR_FMT
#define TARGET_ADDR_FMT
Definition: types.h:286
target_addr_t
uint64_t target_addr_t
Definition: types.h:279
TARGET_PRIxADDR
#define TARGET_PRIxADDR
Definition: types.h:284
NULL
#define NULL
Definition: usb.h:16
cmd
uint8_t cmd
Definition: vdebug.c:1
offset
uint8_t offset[4]
Definition: vdebug.c:9
dummy
uint8_t dummy[96]
Definition: vdebug.c:23
count
uint8_t count[4]
Definition: vdebug.c:22