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arm_adi_v5.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2006 by Magnus Lundin *
5  * lundin@mlu.mine.nu *
6  * *
7  * Copyright (C) 2008 by Spencer Oliver *
8  * spen@spen-soft.co.uk *
9  * *
10  * Copyright (C) 2009-2010 by Oyvind Harboe *
11  * oyvind.harboe@zylin.com *
12  * *
13  * Copyright (C) 2009-2010 by David Brownell *
14  * *
15  * Copyright (C) 2013 by Andreas Fritiofson *
16  * andreas.fritiofson@gmail.com *
17  * *
18  * Copyright (C) 2019-2021, Ampere Computing LLC *
19  ***************************************************************************/
20 
50 /*
51  * Relevant specifications from ARM include:
52  *
53  * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031G
54  * https://developer.arm.com/documentation/ihi0031/latest/
55  *
56  * ARM(tm) Debug Interface v6 Architecture Specification ARM IHI 0074C
57  * https://developer.arm.com/documentation/ihi0074/latest/
58  *
59  * Note that diagrams B4-1 to B4-7 in both ADI specifications show
60  * SWCLK signal mostly in wrong polarity. See detailed SWD timing
61  * https://developer.arm.com/documentation/dui0499/b/arm-dstream-target-interface-connections/swd-timing-requirements
62  *
63  * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64  *
65  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66  * Cortex-M3(tm) TRM, ARM DDI 0337G
67  */
68 
69 #ifdef HAVE_CONFIG_H
70 #include "config.h"
71 #endif
72 
73 #include "jtag/interface.h"
74 #include "arm.h"
75 #include "arm_adi_v5.h"
76 #include "arm_coresight.h"
77 #include "jtag/swd.h"
78 #include "transport/transport.h"
79 #include <helper/align.h>
80 #include <helper/jep106.h>
81 #include <helper/time_support.h>
82 #include <helper/list.h>
83 #include <helper/jim-nvp.h>
84 
85 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
86 
87 /*
88  uint32_t tar_block_size(uint32_t address)
89  Return the largest block starting at address that does not cross a tar block size alignment boundary
90 */
91 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, target_addr_t address)
92 {
93  return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
94 }
95 
96 /***************************************************************************
97  * *
98  * DP and MEM-AP register access through APACC and DPACC *
99  * *
100 ***************************************************************************/
101 
102 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
103 {
104  csw |= ap->csw_default;
105 
106  if (csw != ap->csw_value) {
107  /* LOG_DEBUG("DAP: Set CSW %x",csw); */
108  int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW(ap->dap), csw);
109  if (retval != ERROR_OK) {
110  ap->csw_value = 0;
111  return retval;
112  }
113  ap->csw_value = csw;
114  }
115  return ERROR_OK;
116 }
117 
118 static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar)
119 {
120  if (!ap->tar_valid || tar != ap->tar_value) {
121  /* LOG_DEBUG("DAP: Set TAR %x",tar); */
122  int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR(ap->dap), (uint32_t)(tar & 0xffffffffUL));
123  if (retval == ERROR_OK && is_64bit_ap(ap)) {
124  /* See if bits 63:32 of tar is different from last setting */
125  if (!ap->tar_valid || (ap->tar_value >> 32) != (tar >> 32))
126  retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64(ap->dap), (uint32_t)(tar >> 32));
127  }
128  if (retval != ERROR_OK) {
129  ap->tar_valid = false;
130  return retval;
131  }
132  ap->tar_value = tar;
133  ap->tar_valid = true;
134  }
135  return ERROR_OK;
136 }
137 
138 static int mem_ap_read_tar(struct adiv5_ap *ap, target_addr_t *tar)
139 {
140  uint32_t lower;
141  uint32_t upper = 0;
142 
143  int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR(ap->dap), &lower);
144  if (retval == ERROR_OK && is_64bit_ap(ap))
145  retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR64(ap->dap), &upper);
146 
147  if (retval != ERROR_OK) {
148  ap->tar_valid = false;
149  return retval;
150  }
151 
152  retval = dap_run(ap->dap);
153  if (retval != ERROR_OK) {
154  ap->tar_valid = false;
155  return retval;
156  }
157 
158  *tar = (((target_addr_t)upper) << 32) | (target_addr_t)lower;
159 
160  ap->tar_value = *tar;
161  ap->tar_valid = true;
162  return ERROR_OK;
163 }
164 
165 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
166 {
167  switch (ap->csw_value & CSW_ADDRINC_MASK) {
168  case CSW_ADDRINC_SINGLE:
169  switch (ap->csw_value & CSW_SIZE_MASK) {
170  case CSW_8BIT:
171  return 1;
172  case CSW_16BIT:
173  return 2;
174  case CSW_32BIT:
175  return 4;
176  case CSW_64BIT:
177  return 8;
178  case CSW_128BIT:
179  return 16;
180  case CSW_256BIT:
181  return 32;
182  default:
183  return 0;
184  }
185  case CSW_ADDRINC_PACKED:
186  return 4;
187  }
188  return 0;
189 }
190 
191 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
192  */
193 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
194 {
195  if (!ap->tar_valid)
196  return;
197 
198  uint32_t inc = mem_ap_get_tar_increment(ap);
199  if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
200  ap->tar_valid = false;
201  else
202  ap->tar_value += inc;
203 }
204 
222 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, target_addr_t tar)
223 {
224  int retval;
225  retval = mem_ap_setup_csw(ap, csw);
226  if (retval != ERROR_OK)
227  return retval;
228  retval = mem_ap_setup_tar(ap, tar);
229  if (retval != ERROR_OK)
230  return retval;
231  return ERROR_OK;
232 }
233 
245 int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address,
246  uint32_t *value)
247 {
248  int retval;
249 
250  /* Use banked addressing (REG_BDx) to avoid some link traffic
251  * (updating TAR) when reading several consecutive addresses.
252  */
253  retval = mem_ap_setup_transfer(ap,
254  CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
255  address & 0xFFFFFFFFFFFFFFF0ull);
256  if (retval != ERROR_OK)
257  return retval;
258 
259  return dap_queue_ap_read(ap, MEM_AP_REG_BD0(ap->dap) | (address & 0xC), value);
260 }
261 
274 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
275  uint32_t *value)
276 {
277  int retval;
278 
279  retval = mem_ap_read_u32(ap, address, value);
280  if (retval != ERROR_OK)
281  return retval;
282 
283  return dap_run(ap->dap);
284 }
285 
297 int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address,
298  uint32_t value)
299 {
300  int retval;
301 
302  /* Use banked addressing (REG_BDx) to avoid some link traffic
303  * (updating TAR) when writing several consecutive addresses.
304  */
305  retval = mem_ap_setup_transfer(ap,
306  CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
307  address & 0xFFFFFFFFFFFFFFF0ull);
308  if (retval != ERROR_OK)
309  return retval;
310 
311  return dap_queue_ap_write(ap, MEM_AP_REG_BD0(ap->dap) | (address & 0xC),
312  value);
313 }
314 
326 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
327  uint32_t value)
328 {
329  int retval = mem_ap_write_u32(ap, address, value);
330 
331  if (retval != ERROR_OK)
332  return retval;
333 
334  return dap_run(ap->dap);
335 }
336 
353 static int mem_ap_setup_transfer_verify_size_packing(struct adiv5_ap *ap,
354  unsigned int size, target_addr_t address,
355  bool addrinc, bool pack, unsigned int *this_size)
356 {
357  int retval;
358  uint32_t csw_size;
359 
360  switch (size) {
361  case 1:
362  csw_size = CSW_8BIT;
363  break;
364  case 2:
365  csw_size = CSW_16BIT;
366  break;
367  case 4:
368  csw_size = CSW_32BIT;
369  break;
370  case 8:
371  csw_size = CSW_64BIT;
372  break;
373  case 16:
374  csw_size = CSW_128BIT;
375  break;
376  case 32:
377  csw_size = CSW_256BIT;
378  break;
379  default:
380  LOG_ERROR("Size %u not supported", size);
381  return ERROR_TARGET_SIZE_NOT_SUPPORTED;
382  }
383 
384  if (!addrinc || size >= 4
385  || (ap->packed_transfers_probed && !ap->packed_transfers_supported)
386  || max_tar_block_size(ap->tar_autoincr_block, address) < 4)
387  pack = false;
388 
389  uint32_t csw_addrinc = pack ? CSW_ADDRINC_PACKED :
390  addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
391  retval = mem_ap_setup_csw(ap, csw_size | csw_addrinc);
392  if (retval != ERROR_OK)
393  return retval;
394 
395  bool do_probe = !(ap->csw_size_probed_mask & size)
396  || (pack && !ap->packed_transfers_probed);
397  if (do_probe) {
398  uint32_t csw_readback;
399  retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW(ap->dap), &csw_readback);
400  if (retval != ERROR_OK)
401  return retval;
402 
403  retval = dap_run(ap->dap);
404  if (retval != ERROR_OK)
405  return retval;
406 
407  bool size_supported = ((csw_readback & CSW_SIZE_MASK) == csw_size);
408  LOG_DEBUG("AP#0x%" PRIx64 " probed size %u: %s", ap->ap_num, size,
409  size_supported ? "supported" : "not supported");
410  ap->csw_size_probed_mask |= size;
411  if (size_supported) {
412  ap->csw_size_supported_mask |= size;
413  if (pack && !ap->packed_transfers_probed) {
414  ap->packed_transfers_probed = true;
415  ap->packed_transfers_supported =
416  ((csw_readback & CSW_ADDRINC_MASK) == csw_addrinc);
417  LOG_DEBUG("probed packing: %s",
418  ap->packed_transfers_supported ? "supported" : "not supported");
419  }
420  }
421  }
422 
423  if (!(ap->csw_size_supported_mask & size)) {
424  LOG_ERROR("Size %u not supported", size);
425  return ERROR_TARGET_SIZE_NOT_SUPPORTED;
426  }
427 
428  if (pack && !ap->packed_transfers_supported)
429  return ERROR_TARGET_PACKING_NOT_SUPPORTED;
430 
431  *this_size = pack ? 4 : size;
432 
433  return mem_ap_setup_tar(ap, address);
434 }
435 
453 static int mem_ap_setup_transfer_verify_size_packing_fallback(struct adiv5_ap *ap,
454  unsigned int size, target_addr_t address,
455  bool addrinc, bool pack, unsigned int *this_size)
456 {
457  int retval = mem_ap_setup_transfer_verify_size_packing(ap,
458  size, address,
459  addrinc, pack, this_size);
460  if (retval == ERROR_TARGET_PACKING_NOT_SUPPORTED) {
461  /* Retry without packing */
462  retval = mem_ap_setup_transfer_verify_size_packing(ap,
463  size, address,
464  addrinc, false, this_size);
465  }
466  return retval;
467 }
468 
482 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
483  target_addr_t address, bool addrinc)
484 {
485  struct adiv5_dap *dap = ap->dap;
486  size_t nbytes = size * count;
487  int retval = ERROR_OK;
488 
489  /* TI BE-32 Quirks mode:
490  * Writes on big-endian TMS570 behave very strangely. Observed behavior:
491  * size write address bytes written in order
492  * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
493  * 2 TAR ^ 2 (val >> 8), (val)
494  * 1 TAR ^ 3 (val)
495  * For example, if you attempt to write a single byte to address 0, the processor
496  * will actually write a byte to address 3.
497  *
498  * To make writes of size < 4 work as expected, we xor a value with the address before
499  * setting the TAP, and we set the TAP after every transfer rather then relying on
500  * address increment. */
501  target_addr_t ti_be_addr_xor = 0;
502  target_addr_t ti_be_lane_xor = 0;
503  if (dap->ti_be_32_quirks) {
504  ti_be_lane_xor = 3;
505  switch (size) {
506  case 1:
507  ti_be_addr_xor = 3;
508  break;
509  case 2:
510  ti_be_addr_xor = 2;
511  break;
512  case 4:
513  break;
514  default:
515  LOG_ERROR("Write more than 32 bits not supported with ti_be_32_quirks");
516  return ERROR_TARGET_SIZE_NOT_SUPPORTED;
517  }
518  }
519 
520  if (ap->unaligned_access_bad && (address % size != 0))
521  return ERROR_TARGET_UNALIGNED_ACCESS;
522 
523  /* Nuvoton NPCX quirks prevent packed writes */
524  bool pack = !dap->nu_npcx_quirks;
525 
526  while (nbytes > 0) {
527  unsigned int this_size;
528  retval = mem_ap_setup_transfer_verify_size_packing_fallback(ap,
529  size, address ^ ti_be_addr_xor,
530  addrinc, pack && nbytes >= 4, &this_size);
531  if (retval != ERROR_OK)
532  return retval;
533 
534  /* How many source bytes each transfer will consume, and their location in the DRW,
535  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
536  uint32_t drw_byte_idx = address;
537  unsigned int drw_ops = DIV_ROUND_UP(this_size, 4);
538 
539  while (drw_ops--) {
540  uint32_t outvalue = 0;
541  if (dap->nu_npcx_quirks && this_size <= 2) {
542  switch (this_size) {
543  case 2:
544  {
545  /* Alternate low and high byte to all byte lanes */
546  uint32_t low = *buffer++;
547  uint32_t high = *buffer++;
548  outvalue |= low << 8 * (drw_byte_idx++ & 3);
549  outvalue |= high << 8 * (drw_byte_idx++ & 3);
550  outvalue |= low << 8 * (drw_byte_idx++ & 3);
551  outvalue |= high << 8 * (drw_byte_idx & 3);
552  }
553  break;
554  case 1:
555  {
556  /* Mirror output byte to all byte lanes */
557  uint32_t data = *buffer++;
558  outvalue |= data;
559  outvalue |= data << 8;
560  outvalue |= data << 16;
561  outvalue |= data << 24;
562  }
563  }
564  } else {
565  unsigned int drw_bytes = MIN(this_size, 4);
566  while (drw_bytes--)
567  outvalue |= (uint32_t)*buffer++ <<
568  8 * ((drw_byte_idx++ & 3) ^ ti_be_lane_xor);
569  }
570 
571  retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW(dap), outvalue);
572  if (retval != ERROR_OK)
573  break;
574  }
575  if (retval != ERROR_OK)
576  break;
577 
578  mem_ap_update_tar_cache(ap);
579  nbytes -= this_size;
580  if (addrinc)
581  address += this_size;
582  }
583 
584  /* REVISIT: Might want to have a queued version of this function that does not run. */
585  if (retval == ERROR_OK)
586  retval = dap_run(dap);
587 
588  if (retval != ERROR_OK) {
589  target_addr_t tar;
590  if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
591  LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT, tar);
592  else
593  LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
594  }
595 
596  return retval;
597 }
598 
612 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
613  target_addr_t adr, bool addrinc)
614 {
615  struct adiv5_dap *dap = ap->dap;
616  size_t nbytes = size * count;
617  target_addr_t address = adr;
618  int retval = ERROR_OK;
619 
620  /* TI BE-32 Quirks mode:
621  * Reads on big-endian TMS570 behave strangely differently than writes.
622  * They read from the physical address requested, but with DRW byte-reversed.
623  * For example, a byte read from address 0 will place the result in the high bytes of DRW.
624  * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
625  * so avoid them (ap->packed_transfers is forced to false in mem_ap_init). */
626 
627  if (dap->ti_be_32_quirks && size > 4) {
628  LOG_ERROR("Read more than 32 bits not supported with ti_be_32_quirks");
629  return ERROR_TARGET_SIZE_NOT_SUPPORTED;
630  }
631 
632  if (ap->unaligned_access_bad && (adr % size != 0))
633  return ERROR_TARGET_UNALIGNED_ACCESS;
634 
635  /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
636  * over-allocation if packed transfers are going to be used, but determining the real need at
637  * this point would be messy. */
638  uint32_t *read_buf = calloc(count, MAX(sizeof(uint32_t), size));
639 
640  /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
641  uint32_t *read_ptr = read_buf;
642  if (!read_buf) {
643  LOG_ERROR("Failed to allocate read buffer");
644  return ERROR_FAIL;
645  }
646 
647  /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
648  * useful bytes it contains, and their location in the word, depends on the type of transfer
649  * and alignment. */
650  while (nbytes > 0) {
651  unsigned int this_size;
652  retval = mem_ap_setup_transfer_verify_size_packing_fallback(ap,
653  size, address,
654  addrinc, nbytes >= 4, &this_size);
655  if (retval != ERROR_OK)
656  break;
657 
658 
659  unsigned int drw_ops = DIV_ROUND_UP(this_size, 4);
660  while (drw_ops--) {
661  retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW(dap), read_ptr++);
662  if (retval != ERROR_OK)
663  break;
664  }
665 
666  nbytes -= this_size;
667  if (addrinc)
668  address += this_size;
669 
670  mem_ap_update_tar_cache(ap);
671  }
672 
673  if (retval == ERROR_OK)
674  retval = dap_run(dap);
675 
676  /* Restore state */
677  address = adr;
678  nbytes = size * count;
679  read_ptr = read_buf;
680 
681  /* If something failed, read TAR to find out how much data was successfully read, so we can
682  * at least give the caller what we have. */
683  if (retval == ERROR_TARGET_SIZE_NOT_SUPPORTED) {
684  nbytes = 0;
685  } else if (retval != ERROR_OK) {
686  target_addr_t tar;
687  if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
688  /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
689  LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT, tar);
690  if (nbytes > tar - address)
691  nbytes = tar - address;
692  } else {
693  LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
694  nbytes = 0;
695  }
696  }
697 
698  target_addr_t ti_be_lane_xor = dap->ti_be_32_quirks ? 3 : 0;
699 
700  /* Replay loop to populate caller's buffer from the correct word and byte lane */
701  while (nbytes > 0) {
702  /* Convert transfers longer than 32-bit on word-at-a-time basis */
703  unsigned int this_size = MIN(size, 4);
704 
705  if (size < 4 && addrinc && ap->packed_transfers_supported && nbytes >= 4
706  && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
707  this_size = 4; /* Packed read of 4 bytes or 2 halfwords */
708  }
709 
710  switch (this_size) {
711  case 4:
712  *buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor);
713  *buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor);
714  /* fallthrough */
715  case 2:
716  *buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor);
717  /* fallthrough */
718  case 1:
719  *buffer++ = *read_ptr >> 8 * ((address++ & 3) ^ ti_be_lane_xor);
720  }
721 
722  read_ptr++;
723  nbytes -= this_size;
724  }
725 
726  free(read_buf);
727  return retval;
728 }
729 
730 int mem_ap_read_buf(struct adiv5_ap *ap,
731  uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
732 {
733  return mem_ap_read(ap, buffer, size, count, address, true);
734 }
735 
736 int mem_ap_write_buf(struct adiv5_ap *ap,
737  const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
738 {
739  return mem_ap_write(ap, buffer, size, count, address, true);
740 }
741 
742 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
743  uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
744 {
745  return mem_ap_read(ap, buffer, size, count, address, false);
746 }
747 
748 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
749  const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
750 {
751  return mem_ap_write(ap, buffer, size, count, address, false);
752 }
753 
754 /*--------------------------------------------------------------------------*/
755 
756 
757 #define DAP_POWER_DOMAIN_TIMEOUT (10)
758 
759 /*--------------------------------------------------------------------------*/
760 
764 void dap_invalidate_cache(struct adiv5_dap *dap)
765 {
766  dap->select = 0; /* speculate the first AP access will select AP 0, bank 0 */
767  dap->select_valid = false;
768  dap->select1_valid = false;
769  dap->select_dpbanksel_valid = false;
770 
771  dap->last_read = NULL;
772 
773  int i;
774  for (i = 0; i <= DP_APSEL_MAX; i++) {
775  /* force csw and tar write on the next mem-ap access */
776  dap->ap[i].tar_valid = false;
777  dap->ap[i].csw_value = 0;
778  }
779 }
780 
787 int dap_dp_init(struct adiv5_dap *dap)
788 {
789  int retval;
790 
791  LOG_DEBUG("%s", adiv5_dap_name(dap));
792 
793  dap->do_reconnect = false;
794  dap_invalidate_cache(dap);
795 
796  /*
797  * Early initialize dap->dp_ctrl_stat.
798  * In jtag mode only, if the following queue run (in dap_dp_poll_register)
799  * fails and sets the sticky error, it will trigger the clearing
800  * of the sticky. Without this initialization system and debug power
801  * would be disabled while clearing the sticky error bit.
802  */
803  dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
804 
805  /*
806  * This write operation clears the sticky error and overrun bits in jtag
807  * mode only and is ignored in swd mode. It also powers-up system and
808  * debug domains in both jtag and swd modes, if not done before.
809  */
810  retval = dap_queue_dp_write(dap, DP_CTRL_STAT,
811  dap->dp_ctrl_stat | SSTICKYERR | SSTICKYORUN);
812  if (retval != ERROR_OK)
813  return retval;
814 
815  retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
816  if (retval != ERROR_OK)
817  return retval;
818 
819  retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
820  if (retval != ERROR_OK)
821  return retval;
822 
823  /* Check that we have debug power domains activated */
824  LOG_DEBUG("DAP: wait CDBGPWRUPACK");
825  retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
826  CDBGPWRUPACK, CDBGPWRUPACK,
827  DAP_POWER_DOMAIN_TIMEOUT);
828  if (retval != ERROR_OK)
829  return retval;
830 
831  if (!dap->ignore_syspwrupack) {
832  LOG_DEBUG("DAP: wait CSYSPWRUPACK");
833  retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
834  CSYSPWRUPACK, CSYSPWRUPACK,
835  DAP_POWER_DOMAIN_TIMEOUT);
836  if (retval != ERROR_OK)
837  return retval;
838  }
839 
840  retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
841  if (retval != ERROR_OK)
842  return retval;
843 
844  /* With debug power on we can activate OVERRUN checking */
845  dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
846  retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
847  if (retval != ERROR_OK)
848  return retval;
849  retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
850  if (retval != ERROR_OK)
851  return retval;
852 
853  retval = dap_run(dap);
854  if (retval != ERROR_OK)
855  return retval;
856 
857  return retval;
858 }
859 
865 int dap_dp_init_or_reconnect(struct adiv5_dap *dap)
866 {
867  LOG_DEBUG("%s", adiv5_dap_name(dap));
868 
869  /*
870  * Early initialize dap->dp_ctrl_stat.
871  * In jtag mode only, if the following atomic reads fail and set the
872  * sticky error, it will trigger the clearing of the sticky. Without this
873  * initialization system and debug power would be disabled while clearing
874  * the sticky error bit.
875  */
876  dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
877 
878  dap->do_reconnect = false;
879 
880  dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
881  if (dap->do_reconnect) {
882  /* dap connect calls dap_dp_init() after transport dependent initialization */
883  return dap->ops->connect(dap);
884  } else {
885  return dap_dp_init(dap);
886  }
887 }
888 
896 int mem_ap_init(struct adiv5_ap *ap)
897 {
898  /* check that we support packed transfers */
899  uint32_t cfg;
900  int retval;
901  struct adiv5_dap *dap = ap->dap;
902 
903  /* Set ap->cfg_reg before calling mem_ap_setup_transfer(). */
904  /* mem_ap_setup_transfer() needs to know if the MEM_AP supports LPAE. */
905  retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG(dap), &cfg);
906  if (retval != ERROR_OK)
907  return retval;
908 
909  retval = dap_run(dap);
910  if (retval != ERROR_OK)
911  return retval;
912 
913  ap->cfg_reg = cfg;
914  ap->tar_valid = false;
915  ap->csw_value = 0; /* force csw and tar write */
916 
917  /* CSW 32-bit size must be supported (IHI 0031F and 0074D). */
918  ap->csw_size_supported_mask = BIT(CSW_32BIT);
919  ap->csw_size_probed_mask = BIT(CSW_32BIT);
920 
921  /* Suppress probing sizes longer than 32 bit if AP has no large data extension */
922  if (!(cfg & MEM_AP_REG_CFG_LD))
923  ap->csw_size_probed_mask |= BIT(CSW_64BIT) | BIT(CSW_128BIT) | BIT(CSW_256BIT);
924 
925  /* Both IHI 0031F and 0074D state: Implementations that support transfers
926  * smaller than a word must support packed transfers. Unfortunately at least
927  * Cortex-M0 and Cortex-M0+ do not comply with this rule.
928  * Probe for packed transfers except we know they are broken.
929  * Packed transfers on TI BE-32 processors do not work correctly in
930  * many cases. */
931  ap->packed_transfers_supported = false;
932  ap->packed_transfers_probed = dap->ti_be_32_quirks ? true : false;
933 
934  /* The ARM ADI spec leaves implementation-defined whether unaligned
935  * memory accesses work, only work partially, or cause a sticky error.
936  * On TI BE-32 processors, reads seem to return garbage in some bytes
937  * and unaligned writes seem to cause a sticky error.
938  * TODO: it would be nice to have a way to detect whether unaligned
939  * operations are supported on other processors. */
940  ap->unaligned_access_bad = dap->ti_be_32_quirks;
941 
942  LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
943  !!(cfg & MEM_AP_REG_CFG_LD), !!(cfg & MEM_AP_REG_CFG_LA), !!(cfg & MEM_AP_REG_CFG_BE));
944 
945  return ERROR_OK;
946 }
947 
960 int dap_to_swd(struct adiv5_dap *dap)
961 {
962  LOG_DEBUG("Enter SWD mode");
963 
964  return dap_send_sequence(dap, JTAG_TO_SWD);
965 }
966 
978 int dap_to_jtag(struct adiv5_dap *dap)
979 {
980  LOG_DEBUG("Enter JTAG mode");
981 
982  return dap_send_sequence(dap, SWD_TO_JTAG);
983 }
984 
985 /* CID interpretation -- see ARM IHI 0029E table B2-7
986  * and ARM IHI 0031E table D1-2.
987  *
988  * From 2009/11/25 commit 21378f58b604:
989  * "OptimoDE DESS" is ARM's semicustom DSPish stuff.
990  * Let's keep it as is, for the time being
991  */
992 static const char *class_description[16] = {
993  [0x0] = "Generic verification component",
994  [0x1] = "ROM table",
995  [0x2] = "Reserved",
996  [0x3] = "Reserved",
997  [0x4] = "Reserved",
998  [0x5] = "Reserved",
999  [0x6] = "Reserved",
1000  [0x7] = "Reserved",
1001  [0x8] = "Reserved",
1002  [0x9] = "CoreSight component",
1003  [0xA] = "Reserved",
1004  [0xB] = "Peripheral Test Block",
1005  [0xC] = "Reserved",
1006  [0xD] = "OptimoDE DESS", /* see above */
1007  [0xE] = "Generic IP component",
1008  [0xF] = "CoreLink, PrimeCell or System component",
1009 };
1010 
1011 #define ARCH_ID(architect, archid) ( \
1012  (((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \
1013  (((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \
1014 )
1015 
1016 static const struct {
1017  uint32_t arch_id;
1018  const char *description;
1019 } class0x9_devarch[] = {
1020  /* keep same unsorted order as in ARM IHI0029E */
1021  { ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" },
1022  { ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
1023  { ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" },
1024  { ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
1025  { ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" },
1026  { ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" },
1027  { ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" },
1028  { ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
1029  { ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
1030  { ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" },
1031  { ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" },
1032  { ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" },
1033  { ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
1034  { ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" },
1035  { ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" },
1036  { ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" },
1037  { ARCH_ID(ARM_ID, 0x0A37), "Power requestor" },
1038  { ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" },
1039  { ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" },
1040  { ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" },
1041  { ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" },
1042  { ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" },
1043 };
1044 
1045 #define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
1046 #define DEVARCH_MEM_AP ARCH_ID(ARM_ID, 0x0A17)
1047 #define DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)
1048 #define DEVARCH_UNKNOWN_V2 ARCH_ID(ARM_ID, 0x0A47)
1049 
1050 static const char *class0x9_devarch_description(uint32_t devarch)
1051 {
1052  if (!(devarch & ARM_CS_C9_DEVARCH_PRESENT))
1053  return "not present";
1054 
1055  for (unsigned int i = 0; i < ARRAY_SIZE(class0x9_devarch); i++)
1056  if ((devarch & DEVARCH_ID_MASK) == class0x9_devarch[i].arch_id)
1057  return class0x9_devarch[i].description;
1058 
1059  return "unknown";
1060 }
1061 
1062 static const struct {
1063  enum ap_type type;
1064  const char *description;
1065 } ap_types[] = {
1066  { AP_TYPE_JTAG_AP, "JTAG-AP" },
1067  { AP_TYPE_COM_AP, "COM-AP" },
1068  { AP_TYPE_AHB3_AP, "MEM-AP AHB3" },
1069  { AP_TYPE_APB_AP, "MEM-AP APB2 or APB3" },
1070  { AP_TYPE_AXI_AP, "MEM-AP AXI3 or AXI4" },
1071  { AP_TYPE_AHB5_AP, "MEM-AP AHB5" },
1072  { AP_TYPE_APB4_AP, "MEM-AP APB4" },
1073  { AP_TYPE_AXI5_AP, "MEM-AP AXI5" },
1074  { AP_TYPE_AHB5H_AP, "MEM-AP AHB5 with enhanced HPROT" },
1075 };
1076 
1077 static const char *ap_type_to_description(enum ap_type type)
1078 {
1079  for (unsigned int i = 0; i < ARRAY_SIZE(ap_types); i++)
1080  if (type == ap_types[i].type)
1081  return ap_types[i].description;
1082 
1083  return "Unknown";
1084 }
1085 
1086 bool is_ap_num_valid(struct adiv5_dap *dap, uint64_t ap_num)
1087 {
1088  if (!dap)
1089  return false;
1090 
1091  /* no autodetection, by now, so uninitialized is equivalent to ADIv5 for
1092  * backward compatibility */
1093  if (!is_adiv6(dap)) {
1094  if (ap_num > DP_APSEL_MAX)
1095  return false;
1096  return true;
1097  }
1098 
1099  if (is_adiv6(dap)) {
1100  if (ap_num & 0x0fffULL)
1101  return false;
1102  if (dap->asize != 0)
1103  if (ap_num & ((~0ULL) << dap->asize))
1104  return false;
1105  return true;
1106  }
1107 
1108  return false;
1109 }
1110 
1111 /*
1112  * This function checks the ID for each access port to find the requested Access Port type
1113  * It also calls dap_get_ap() to increment the AP refcount
1114  */
1115 int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
1116 {
1117  if (is_adiv6(dap)) {
1118  /* TODO: scan the ROM table and detect the AP available */
1119  LOG_DEBUG("On ADIv6 we cannot scan all the possible AP");
1120  return ERROR_FAIL;
1121  }
1122 
1123  /* Maximum AP number is 255 since the SELECT register is 8 bits */
1124  for (unsigned int ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) {
1125  struct adiv5_ap *ap = dap_get_ap(dap, ap_num);
1126  if (!ap)
1127  continue;
1128 
1129  /* read the IDR register of the Access Port */
1130  uint32_t id_val = 0;
1131 
1132  int retval = dap_queue_ap_read(ap, AP_REG_IDR(dap), &id_val);
1133  if (retval != ERROR_OK) {
1134  dap_put_ap(ap);
1135  return retval;
1136  }
1137 
1138  retval = dap_run(dap);
1139 
1140  /* Reading register for a non-existent AP should not cause an error,
1141  * but just to be sure, try to continue searching if an error does happen.
1142  */
1143  if (retval == ERROR_OK && (id_val & AP_TYPE_MASK) == type_to_find) {
1144  LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
1145  ap_type_to_description(type_to_find),
1146  ap_num, id_val);
1147 
1148  *ap_out = ap;
1149  return ERROR_OK;
1150  }
1151  dap_put_ap(ap);
1152  }
1153 
1154  LOG_DEBUG("No %s found", ap_type_to_description(type_to_find));
1155  return ERROR_FAIL;
1156 }
1157 
1158 static inline bool is_ap_in_use(struct adiv5_ap *ap)
1159 {
1160  return ap->refcount > 0 || ap->config_ap_never_release;
1161 }
1162 
1163 static struct adiv5_ap *_dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
1164 {
1165  if (!is_ap_num_valid(dap, ap_num)) {
1166  LOG_ERROR("Invalid AP#0x%" PRIx64, ap_num);
1167  return NULL;
1168  }
1169  if (is_adiv6(dap)) {
1170  for (unsigned int i = 0; i <= DP_APSEL_MAX; i++) {
1171  struct adiv5_ap *ap = &dap->ap[i];
1172  if (is_ap_in_use(ap) && ap->ap_num == ap_num) {
1173  ++ap->refcount;
1174  return ap;
1175  }
1176  }
1177  for (unsigned int i = 0; i <= DP_APSEL_MAX; i++) {
1178  struct adiv5_ap *ap = &dap->ap[i];
1179  if (!is_ap_in_use(ap)) {
1180  ap->ap_num = ap_num;
1181  ++ap->refcount;
1182  return ap;
1183  }
1184  }
1185  LOG_ERROR("No more AP available!");
1186  return NULL;
1187  }
1188 
1189  /* ADIv5 */
1190  struct adiv5_ap *ap = &dap->ap[ap_num];
1191  ap->ap_num = ap_num;
1192  ++ap->refcount;
1193  return ap;
1194 }
1195 
1196 /* Return AP with specified ap_num. Increment AP refcount */
1197 struct adiv5_ap *dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
1198 {
1199  struct adiv5_ap *ap = _dap_get_ap(dap, ap_num);
1200  if (ap)
1201  LOG_DEBUG("refcount AP#0x%" PRIx64 " get %u", ap_num, ap->refcount);
1202  return ap;
1203 }
1204 
1205 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
1206 struct adiv5_ap *dap_get_config_ap(struct adiv5_dap *dap, uint64_t ap_num)
1207 {
1208  struct adiv5_ap *ap = _dap_get_ap(dap, ap_num);
1209  if (ap) {
1210  ap->config_ap_never_release = true;
1211  LOG_DEBUG("refcount AP#0x%" PRIx64 " get_config %u", ap_num, ap->refcount);
1212  }
1213  return ap;
1214 }
1215 
1216 /* Decrement AP refcount and release the AP when refcount reaches zero */
1217 int dap_put_ap(struct adiv5_ap *ap)
1218 {
1219  if (ap->refcount == 0) {
1220  LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " put underflow", ap->ap_num);
1221  return ERROR_FAIL;
1222  }
1223 
1224  --ap->refcount;
1225 
1226  LOG_DEBUG("refcount AP#0x%" PRIx64 " put %u", ap->ap_num, ap->refcount);
1227  if (!is_ap_in_use(ap)) {
1228  /* defaults from dap_instance_init() */
1229  ap->ap_num = DP_APSEL_INVALID;
1230  ap->memaccess_tck = 255;
1231  ap->tar_autoincr_block = (1 << 10);
1232  ap->csw_default = CSW_AHB_DEFAULT;
1233  ap->cfg_reg = MEM_AP_REG_CFG_INVALID;
1234  }
1235  return ERROR_OK;
1236 }
1237 
1238 static int dap_get_debugbase(struct adiv5_ap *ap,
1239  target_addr_t *dbgbase, uint32_t *apid)
1240 {
1241  struct adiv5_dap *dap = ap->dap;
1242  int retval;
1243  uint32_t baseptr_upper, baseptr_lower;
1244 
1245  if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID) {
1246  retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG(dap), &ap->cfg_reg);
1247  if (retval != ERROR_OK)
1248  return retval;
1249  }
1250  retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE(dap), &baseptr_lower);
1251  if (retval != ERROR_OK)
1252  return retval;
1253  retval = dap_queue_ap_read(ap, AP_REG_IDR(dap), apid);
1254  if (retval != ERROR_OK)
1255  return retval;
1256  /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
1257  if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap)) {
1258  retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64(dap), &baseptr_upper);
1259  if (retval != ERROR_OK)
1260  return retval;
1261  }
1262 
1263  retval = dap_run(dap);
1264  if (retval != ERROR_OK)
1265  return retval;
1266 
1267  if (!is_64bit_ap(ap))
1268  baseptr_upper = 0;
1269  *dbgbase = (((target_addr_t)baseptr_upper) << 32) | baseptr_lower;
1270 
1271  return ERROR_OK;
1272 }
1273 
1274 int adiv6_dap_read_baseptr(struct command_invocation *cmd, struct adiv5_dap *dap, uint64_t *baseptr)
1275 {
1276  uint32_t baseptr_lower, baseptr_upper = 0;
1277  int retval;
1278 
1279  if (dap->asize > 32) {
1280  retval = dap_queue_dp_read(dap, DP_BASEPTR1, &baseptr_upper);
1281  if (retval != ERROR_OK)
1282  return retval;
1283  }
1284 
1285  retval = dap_dp_read_atomic(dap, DP_BASEPTR0, &baseptr_lower);
1286  if (retval != ERROR_OK)
1287  return retval;
1288 
1289  if ((baseptr_lower & DP_BASEPTR0_VALID) != DP_BASEPTR0_VALID) {
1290  command_print(cmd, "System root table not present");
1291  return ERROR_FAIL;
1292  }
1293 
1294  baseptr_lower &= ~0x0fff;
1295  *baseptr = (((uint64_t)baseptr_upper) << 32) | baseptr_lower;
1296 
1297  return ERROR_OK;
1298 }
1299 
1306 enum coresight_access_mode {
1307  CS_ACCESS_AP,
1308  CS_ACCESS_MEM_AP,
1309 };
1310 
1312 struct cs_component_vals {
1313  struct adiv5_ap *ap;
1314  target_addr_t component_base;
1315  uint64_t pid;
1316  uint32_t cid;
1317  uint32_t devarch;
1318  uint32_t devid;
1319  uint32_t devtype_memtype;
1320  enum coresight_access_mode mode;
1321 };
1322 
1335 static int dap_queue_read_reg(enum coresight_access_mode mode, struct adiv5_ap *ap,
1336  uint64_t component_base, unsigned int reg, uint32_t *value)
1337 {
1338  if (mode == CS_ACCESS_AP)
1339  return dap_queue_ap_read(ap, reg, value);
1340 
1341  /* mode == CS_ACCESS_MEM_AP */
1342  return mem_ap_read_u32(ap, component_base + reg, value);
1343 }
1344 
1355 static int rtp_read_cs_regs(enum coresight_access_mode mode, struct adiv5_ap *ap,
1356  target_addr_t component_base, struct cs_component_vals *v)
1357 {
1358  assert(IS_ALIGNED(component_base, ARM_CS_ALIGN));
1359  assert(ap && v);
1360 
1361  uint32_t cid0, cid1, cid2, cid3;
1362  uint32_t pid0, pid1, pid2, pid3, pid4;
1363  int retval = ERROR_OK;
1364 
1365  v->ap = ap;
1366  v->component_base = component_base;
1367  v->mode = mode;
1368 
1369  /* sort by offset to gain speed */
1370 
1371  /*
1372  * Registers DEVARCH, DEVID and DEVTYPE are valid on Class 0x9 devices
1373  * only, but are at offset above 0xf00, so can be read on any device
1374  * without triggering error. Read them for eventual use on Class 0x9.
1375  */
1376  if (retval == ERROR_OK)
1377  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVARCH, &v->devarch);
1378 
1379  if (retval == ERROR_OK)
1380  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVID, &v->devid);
1381 
1382  /* Same address as ARM_CS_C1_MEMTYPE */
1383  if (retval == ERROR_OK)
1384  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_C9_DEVTYPE, &v->devtype_memtype);
1385 
1386  if (retval == ERROR_OK)
1387  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR4, &pid4);
1388 
1389  if (retval == ERROR_OK)
1390  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR0, &pid0);
1391  if (retval == ERROR_OK)
1392  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR1, &pid1);
1393  if (retval == ERROR_OK)
1394  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR2, &pid2);
1395  if (retval == ERROR_OK)
1396  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_PIDR3, &pid3);
1397 
1398  if (retval == ERROR_OK)
1399  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR0, &cid0);
1400  if (retval == ERROR_OK)
1401  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR1, &cid1);
1402  if (retval == ERROR_OK)
1403  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR2, &cid2);
1404  if (retval == ERROR_OK)
1405  retval = dap_queue_read_reg(mode, ap, component_base, ARM_CS_CIDR3, &cid3);
1406 
1407  if (retval == ERROR_OK)
1408  retval = dap_run(ap->dap);
1409  if (retval != ERROR_OK) {
1410  LOG_DEBUG("Failed read CoreSight registers");
1411  return retval;
1412  }
1413 
1414  v->cid = (cid3 & 0xff) << 24
1415  | (cid2 & 0xff) << 16
1416  | (cid1 & 0xff) << 8
1417  | (cid0 & 0xff);
1418  v->pid = (uint64_t)(pid4 & 0xff) << 32
1419  | (pid3 & 0xff) << 24
1420  | (pid2 & 0xff) << 16
1421  | (pid1 & 0xff) << 8
1422  | (pid0 & 0xff);
1423 
1424  return ERROR_OK;
1425 }
1426 
1427 /* Part number interpretations are from Cortex
1428  * core specs, the CoreSight components TRM
1429  * (ARM DDI 0314H), CoreSight System Design
1430  * Guide (ARM DGI 0012D) and ETM specs; also
1431  * from chip observation (e.g. TI SDTI).
1432  */
1433 
1434 static const struct dap_part_nums {
1435  uint16_t designer_id;
1436  uint16_t part_num;
1437  const char *type;
1438  const char *full;
1439 } dap_part_nums[] = {
1440  { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1441  { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1442  { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1443  { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1444  { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1445  { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1446  { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1447  { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1448  { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1449  { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1450  { ARM_ID, 0x193, "SoC-600 TSGEN", "(Timestamp Generator)", },
1451  { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1452  { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1453  { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1454  { ARM_ID, 0x492, "Cortex-R52 GICD", "(Distributor)", },
1455  { ARM_ID, 0x493, "Cortex-R52 GICR", "(Redistributor)", },
1456  { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1457  { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1458  { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1459  { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1460  { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1461  { ARM_ID, 0x4aa, "Cortex-A35 ROM", "(v8 Memory Map ROM Table)", },
1462  { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1463  { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1464  { ARM_ID, 0x4b8, "Cortex-R52 ROM", "(ROM Table)", },
1465  { ARM_ID, 0x4bd, "Cortex-R52+ ROM", "(ROM Table)", },
1466  { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1467  { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1468  { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1469  { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1470  { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1471  { ARM_ID, 0x4c9, "STAR ROM", "(ROM Table)", },
1472  { ARM_ID, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", },
1473  { ARM_ID, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", },
1474  { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1475  { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1476  { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1477  { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1478  { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1479  { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1480  { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1481  { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1482  { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1483  { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1484  { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1485  { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1486  { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1487  { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1488  { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1489  { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1490  { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1491  { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1492  { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1493  { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1494  { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1495  { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1496  { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1497  { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1498  { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1499  { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1500  { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1501  { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1502  { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1503  { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1504  { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1505  { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1506  { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1507  { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1508  { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1509  { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1510  { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1511  { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1512  { ARM_ID, 0x9b6, "Cortex-R52 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1513  { ARM_ID, 0x9bb, "Cortex-R52+ PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1514  { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1515  { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1516  { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1517  { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1518  { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1519  { ARM_ID, 0x9e2, "SoC-600 APB-AP", "(APB4 Memory Access Port)", },
1520  { ARM_ID, 0x9e3, "SoC-600 AHB-AP", "(AHB5 Memory Access Port)", },
1521  { ARM_ID, 0x9e4, "SoC-600 AXI-AP", "(AXI Memory Access Port)", },
1522  { ARM_ID, 0x9e5, "SoC-600 APv1 Adapter", "(Access Port v1 Adapter)", },
1523  { ARM_ID, 0x9e6, "SoC-600 JTAG-AP", "(JTAG Access Port)", },
1524  { ARM_ID, 0x9e7, "SoC-600 TPIU", "(Trace Port Interface Unit)", },
1525  { ARM_ID, 0x9e8, "SoC-600 TMC ETR/ETS", "(Embedded Trace Router/Streamer)", },
1526  { ARM_ID, 0x9e9, "SoC-600 TMC ETB", "(Embedded Trace Buffer)", },
1527  { ARM_ID, 0x9ea, "SoC-600 TMC ETF", "(Embedded Trace FIFO)", },
1528  { ARM_ID, 0x9eb, "SoC-600 ATB Funnel", "(Trace Funnel)", },
1529  { ARM_ID, 0x9ec, "SoC-600 ATB Replicator", "(Trace Replicator)", },
1530  { ARM_ID, 0x9ed, "SoC-600 CTI", "(Cross Trigger)", },
1531  { ARM_ID, 0x9ee, "SoC-600 CATU", "(Address Translation Unit)", },
1532  { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1533  { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1534  { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1535  { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1536  { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1537  { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1538  { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1539  { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1540  { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1541  { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1542  { ARM_ID, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", },
1543  { ARM_ID, 0xd05, "Cortex-A55 Debug", "(Debug Unit)", },
1544  { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1545  { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1546  { ARM_ID, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", },
1547  { ARM_ID, 0xd0c, "Neoverse N1", "(Debug Unit)", },
1548  { ARM_ID, 0xd13, "Cortex-R52 Debug", "(Debug Unit)", },
1549  { ARM_ID, 0xd16, "Cortex-R52+ Debug", "(Debug Unit)", },
1550  { ARM_ID, 0xd21, "STAR Debug", "(Debug Unit)", },
1551  { ARM_ID, 0xd22, "Cortex-M55 Debug", "(Debug Unit)", },
1552  { ARM_ID, 0xd43, "Cortex-A65AE Debug", "(Debug Unit)", },
1553  { ARM_ID, 0xd49, "Neoverse N2", "(Debug Unit)", },
1554  { 0x017, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1555  { 0x017, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1556  { 0x017, 0x9af, "MSP432 ROM", "(ROM Table)" },
1557  { 0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1558  { 0x041, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1559  { 0x041, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1560  { 0x041, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1561  { 0x065, 0x000, "SHARC+/Blackfin+", "", },
1562  { 0x070, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1563  { 0x0bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
1564  { 0x0bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
1565  { 0x0bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
1566  { 0x0bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
1567  { 0x1eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1568  { 0x1eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1569  { 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1570  { 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", },
1571  { 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1572  { 0x575, 0x132, "STAR SCS", "(System Control Space)", },
1573  { 0x575, 0x4d2, "Cortex-M52 ROM", "(ROM Table)", },
1574  { 0x575, 0xd24, "Cortex-M52 Debug", "(Debug Unit)", },
1575 };
1576 
1577 static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, unsigned int part_num)
1578 {
1579  static const struct dap_part_nums unknown = {
1580  .type = "Unrecognized",
1581  .full = "",
1582  };
1583 
1584  for (unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++)
1585  if (dap_part_nums[i].designer_id == designer_id && dap_part_nums[i].part_num == part_num)
1586  return &dap_part_nums[i];
1587 
1588  return &unknown;
1589 }
1590 
1591 static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
1592 {
1593  const char *major = "Reserved", *subtype = "Reserved";
1594  const unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
1595  const unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
1596  switch (devtype_major) {
1597  case 0:
1598  major = "Miscellaneous";
1599  switch (minor) {
1600  case 0:
1601  subtype = "other";
1602  break;
1603  case 4:
1604  subtype = "Validation component";
1605  break;
1606  }
1607  break;
1608  case 1:
1609  major = "Trace Sink";
1610  switch (minor) {
1611  case 0:
1612  subtype = "other";
1613  break;
1614  case 1:
1615  subtype = "Port";
1616  break;
1617  case 2:
1618  subtype = "Buffer";
1619  break;
1620  case 3:
1621  subtype = "Router";
1622  break;
1623  }
1624  break;
1625  case 2:
1626  major = "Trace Link";
1627  switch (minor) {
1628  case 0:
1629  subtype = "other";
1630  break;
1631  case 1:
1632  subtype = "Funnel, router";
1633  break;
1634  case 2:
1635  subtype = "Filter";
1636  break;
1637  case 3:
1638  subtype = "FIFO, buffer";
1639  break;
1640  }
1641  break;
1642  case 3:
1643  major = "Trace Source";
1644  switch (minor) {
1645  case 0:
1646  subtype = "other";
1647  break;
1648  case 1:
1649  subtype = "Processor";
1650  break;
1651  case 2:
1652  subtype = "DSP";
1653  break;
1654  case 3:
1655  subtype = "Engine/Coprocessor";
1656  break;
1657  case 4:
1658  subtype = "Bus";
1659  break;
1660  case 6:
1661  subtype = "Software";
1662  break;
1663  }
1664  break;
1665  case 4:
1666  major = "Debug Control";
1667  switch (minor) {
1668  case 0:
1669  subtype = "other";
1670  break;
1671  case 1:
1672  subtype = "Trigger Matrix";
1673  break;
1674  case 2:
1675  subtype = "Debug Auth";
1676  break;
1677  case 3:
1678  subtype = "Power Requestor";
1679  break;
1680  }
1681  break;
1682  case 5:
1683  major = "Debug Logic";
1684  switch (minor) {
1685  case 0:
1686  subtype = "other";
1687  break;
1688  case 1:
1689  subtype = "Processor";
1690  break;
1691  case 2:
1692  subtype = "DSP";
1693  break;
1694  case 3:
1695  subtype = "Engine/Coprocessor";
1696  break;
1697  case 4:
1698  subtype = "Bus";
1699  break;
1700  case 5:
1701  subtype = "Memory";
1702  break;
1703  }
1704  break;
1705  case 6:
1706  major = "Performance Monitor";
1707  switch (minor) {
1708  case 0:
1709  subtype = "other";
1710  break;
1711  case 1:
1712  subtype = "Processor";
1713  break;
1714  case 2:
1715  subtype = "DSP";
1716  break;
1717  case 3:
1718  subtype = "Engine/Coprocessor";
1719  break;
1720  case 4:
1721  subtype = "Bus";
1722  break;
1723  case 5:
1724  subtype = "Memory";
1725  break;
1726  }
1727  break;
1728  }
1729  command_print(cmd, "\t\tType is 0x%02x, %s, %s",
1730  devtype & ARM_CS_C9_DEVTYPE_MASK,
1731  major, subtype);
1732  return ERROR_OK;
1733 }
1734 
1738 struct rtp_ops {
1746  int (*ap_header)(struct adiv5_ap *ap, int depth, void *priv);
1757  int (*mem_ap_header)(int retval, struct adiv5_ap *ap, uint64_t dbgbase,
1758  uint32_t apid, int depth, void *priv);
1768  int (*cs_component)(int retval, struct cs_component_vals *v, int depth, void *priv);
1779  int (*rom_table_entry)(int retval, int depth, unsigned int offset, uint64_t romentry,
1780  void *priv);
1784  void *priv;
1785 };
1786 
1790 static int rtp_ops_ap_header(const struct rtp_ops *ops,
1791  struct adiv5_ap *ap, int depth)
1792 {
1793  if (ops->ap_header)
1794  return ops->ap_header(ap, depth, ops->priv);
1795 
1796  return ERROR_OK;
1797 }
1798 
1803 static int rtp_ops_mem_ap_header(const struct rtp_ops *ops,
1804  int retval, struct adiv5_ap *ap, uint64_t dbgbase, uint32_t apid, int depth)
1805 {
1806  if (!ops->mem_ap_header)
1807  return retval;
1808 
1809  int retval1 = ops->mem_ap_header(retval, ap, dbgbase, apid, depth, ops->priv);
1810  if (retval != ERROR_OK)
1811  return retval;
1812  return retval1;
1813 }
1814 
1819 static int rtp_ops_cs_component(const struct rtp_ops *ops,
1820  int retval, struct cs_component_vals *v, int depth)
1821 {
1822  if (!ops->cs_component)
1823  return retval;
1824 
1825  int retval1 = ops->cs_component(retval, v, depth, ops->priv);
1826  if (retval != ERROR_OK)
1827  return retval;
1828  return retval1;
1829 }
1830 
1835 static int rtp_ops_rom_table_entry(const struct rtp_ops *ops,
1836  int retval, int depth, unsigned int offset, uint64_t romentry)
1837 {
1838  if (!ops->rom_table_entry)
1839  return retval;
1840 
1841  int retval1 = ops->rom_table_entry(retval, depth, offset, romentry, ops->priv);
1842  if (retval != ERROR_OK)
1843  return retval;
1844  return retval1;
1845 }
1846 
1847 /* Broken ROM tables can have circular references. Stop after a while */
1848 #define ROM_TABLE_MAX_DEPTH (16)
1849 
1856 #define CORESIGHT_COMPONENT_FOUND (1)
1857 
1858 static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth);
1859 static int rtp_cs_component(enum coresight_access_mode mode, const struct rtp_ops *ops,
1860  struct adiv5_ap *ap, target_addr_t dbgbase, bool *is_mem_ap, int depth);
1861 
1862 static int rtp_rom_loop(enum coresight_access_mode mode, const struct rtp_ops *ops,
1863  struct adiv5_ap *ap, target_addr_t base_address, int depth,
1864  unsigned int width, unsigned int max_entries)
1865 {
1866  /* ADIv6 AP ROM table provide offset from current AP */
1867  if (mode == CS_ACCESS_AP)
1868  base_address = ap->ap_num;
1869 
1870  assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
1871 
1872  unsigned int offset = 0;
1873  while (max_entries--) {
1874  uint64_t romentry;
1875  uint32_t romentry_low, romentry_high;
1876  target_addr_t component_base;
1877  unsigned int saved_offset = offset;
1878 
1879  int retval = dap_queue_read_reg(mode, ap, base_address, offset, &romentry_low);
1880  offset += 4;
1881  if (retval == ERROR_OK && width == 64) {
1882  retval = dap_queue_read_reg(mode, ap, base_address, offset, &romentry_high);
1883  offset += 4;
1884  }
1885  if (retval == ERROR_OK)
1886  retval = dap_run(ap->dap);
1887  if (retval != ERROR_OK) {
1888  LOG_DEBUG("Failed read ROM table entry");
1889  return retval;
1890  }
1891 
1892  if (width == 64) {
1893  romentry = (((uint64_t)romentry_high) << 32) | romentry_low;
1894  component_base = base_address +
1895  ((((uint64_t)romentry_high) << 32) | (romentry_low & ARM_CS_ROMENTRY_OFFSET_MASK));
1896  } else {
1897  romentry = romentry_low;
1898  /* "romentry" is signed */
1899  component_base = base_address + (int32_t)(romentry_low & ARM_CS_ROMENTRY_OFFSET_MASK);
1900  if (!is_64bit_ap(ap))
1901  component_base = (uint32_t)component_base;
1902  }
1903  retval = rtp_ops_rom_table_entry(ops, retval, depth, saved_offset, romentry);
1904  if (retval != ERROR_OK)
1905  return retval;
1906 
1907  if (romentry == 0) {
1908  /* End of ROM table */
1909  break;
1910  }
1911 
1912  if (!(romentry & ARM_CS_ROMENTRY_PRESENT))
1913  continue;
1914 
1915  /* Recurse */
1916  if (mode == CS_ACCESS_AP) {
1917  struct adiv5_ap *next_ap = dap_get_ap(ap->dap, component_base);
1918  if (!next_ap) {
1919  LOG_DEBUG("Wrong AP # 0x%" PRIx64, component_base);
1920  continue;
1921  }
1922  retval = rtp_ap(ops, next_ap, depth + 1);
1923  dap_put_ap(next_ap);
1924  } else {
1925  /* mode == CS_ACCESS_MEM_AP */
1926  retval = rtp_cs_component(mode, ops, ap, component_base, NULL, depth + 1);
1927  }
1928  if (retval == CORESIGHT_COMPONENT_FOUND)
1929  return CORESIGHT_COMPONENT_FOUND;
1930  if (retval != ERROR_OK) {
1931  /* TODO: do we need to send an ABORT before continuing? */
1932  LOG_DEBUG("Ignore error parsing CoreSight component");
1933  continue;
1934  }
1935  }
1936 
1937  return ERROR_OK;
1938 }
1939 
1940 static int rtp_cs_component(enum coresight_access_mode mode, const struct rtp_ops *ops,
1941  struct adiv5_ap *ap, target_addr_t base_address, bool *is_mem_ap, int depth)
1942 {
1943  struct cs_component_vals v;
1944  int retval;
1945 
1946  assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
1947 
1948  if (is_mem_ap)
1949  *is_mem_ap = false;
1950 
1951  if (depth > ROM_TABLE_MAX_DEPTH)
1952  retval = ERROR_FAIL;
1953  else
1954  retval = rtp_read_cs_regs(mode, ap, base_address, &v);
1955 
1956  retval = rtp_ops_cs_component(ops, retval, &v, depth);
1957  if (retval == CORESIGHT_COMPONENT_FOUND)
1958  return CORESIGHT_COMPONENT_FOUND;
1959  if (retval != ERROR_OK)
1960  return ERROR_OK; /* Don't abort recursion */
1961 
1962  if (!is_valid_arm_cs_cidr(v.cid))
1963  return ERROR_OK; /* Don't abort recursion */
1964 
1965  const unsigned int class = ARM_CS_CIDR_CLASS(v.cid);
1966 
1967  if (class == ARM_CS_CLASS_0X1_ROM_TABLE)
1968  return rtp_rom_loop(mode, ops, ap, base_address, depth, 32, 960);
1969 
1970  if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
1971  if ((v.devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
1972  return ERROR_OK;
1973 
1974  if (is_mem_ap) {
1975  if ((v.devarch & DEVARCH_ID_MASK) == DEVARCH_MEM_AP)
1976  *is_mem_ap = true;
1977 
1978  /* SoC-600 APv1 Adapter */
1979  if ((v.devarch & DEVARCH_ID_MASK) == DEVARCH_UNKNOWN_V2 &&
1980  ARM_CS_PIDR_DESIGNER(v.pid) == ARM_ID &&
1981  ARM_CS_PIDR_PART(v.pid) == 0x9e5)
1982  *is_mem_ap = true;
1983  }
1984 
1985  /* quit if not ROM table */
1986  if ((v.devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9)
1987  return ERROR_OK;
1988 
1989  if ((v.devid & ARM_CS_C9_DEVID_FORMAT_MASK) == ARM_CS_C9_DEVID_FORMAT_64BIT)
1990  return rtp_rom_loop(mode, ops, ap, base_address, depth, 64, 256);
1991  else
1992  return rtp_rom_loop(mode, ops, ap, base_address, depth, 32, 512);
1993  }
1994 
1995  /* Class other than 0x1 and 0x9 */
1996  return ERROR_OK;
1997 }
1998 
1999 static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
2000 {
2001  uint32_t apid;
2002  target_addr_t dbgbase, invalid_entry;
2003 
2004  int retval = rtp_ops_ap_header(ops, ap, depth);
2005  if (retval != ERROR_OK || depth > ROM_TABLE_MAX_DEPTH)
2006  return ERROR_OK; /* Don't abort recursion */
2007 
2008  if (is_adiv6(ap->dap)) {
2009  bool is_mem_ap;
2010  retval = rtp_cs_component(CS_ACCESS_AP, ops, ap, 0, &is_mem_ap, depth);
2011  if (retval == CORESIGHT_COMPONENT_FOUND)
2012  return CORESIGHT_COMPONENT_FOUND;
2013  if (retval != ERROR_OK)
2014  return ERROR_OK; /* Don't abort recursion */
2015 
2016  if (!is_mem_ap)
2017  return ERROR_OK;
2018  /* Continue for an ADIv6 MEM-AP or SoC-600 APv1 Adapter */
2019  }
2020 
2021  /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
2022  retval = dap_get_debugbase(ap, &dbgbase, &apid);
2023  if (retval != ERROR_OK)
2024  return retval;
2025  retval = rtp_ops_mem_ap_header(ops, retval, ap, dbgbase, apid, depth);
2026  if (retval != ERROR_OK)
2027  return retval;
2028 
2029  if (apid == 0)
2030  return ERROR_FAIL;
2031 
2032  /* NOTE: a MEM-AP may have a single CoreSight component that's
2033  * not a ROM table ... or have no such components at all.
2034  */
2035  const unsigned int class = (apid & AP_REG_IDR_CLASS_MASK) >> AP_REG_IDR_CLASS_SHIFT;
2036 
2037  if (class == AP_REG_IDR_CLASS_MEM_AP) {
2038  if (is_64bit_ap(ap))
2039  invalid_entry = 0xFFFFFFFFFFFFFFFFull;
2040  else
2041  invalid_entry = 0xFFFFFFFFul;
2042 
2043  if (dbgbase != invalid_entry && (dbgbase & 0x3) != 0x2) {
2044  retval = rtp_cs_component(CS_ACCESS_MEM_AP, ops, ap,
2045  dbgbase & 0xFFFFFFFFFFFFF000ull, NULL, depth);
2046  if (retval == CORESIGHT_COMPONENT_FOUND)
2047  return CORESIGHT_COMPONENT_FOUND;
2048  }
2049  }
2050 
2051  return ERROR_OK;
2052 }
2053 
2054 /* Actions for command "dap info" */
2055 
2056 static int dap_info_ap_header(struct adiv5_ap *ap, int depth, void *priv)
2057 {
2058  struct command_invocation *cmd = priv;
2059 
2060  if (depth > ROM_TABLE_MAX_DEPTH) {
2061  command_print(cmd, "\tTables too deep");
2062  return ERROR_FAIL;
2063  }
2064 
2065  command_print(cmd, "%sAP # 0x%" PRIx64, (depth) ? "\t\t" : "", ap->ap_num);
2066  return ERROR_OK;
2067 }
2068 
2069 static int dap_info_mem_ap_header(int retval, struct adiv5_ap *ap,
2070  target_addr_t dbgbase, uint32_t apid, int depth, void *priv)
2071 {
2072  struct command_invocation *cmd = priv;
2073  target_addr_t invalid_entry;
2074  char tabs[17] = "";
2075 
2076  if (retval != ERROR_OK) {
2077  command_print(cmd, "\t\tCan't read MEM-AP, the corresponding core might be turned off");
2078  return retval;
2079  }
2080 
2081  if (depth > ROM_TABLE_MAX_DEPTH) {
2082  command_print(cmd, "\tTables too deep");
2083  return ERROR_FAIL;
2084  }
2085 
2086  if (depth)
2087  snprintf(tabs, sizeof(tabs), "\t[L%02d] ", depth);
2088 
2089  command_print(cmd, "\t\tAP ID register 0x%8.8" PRIx32, apid);
2090  if (apid == 0) {
2091  command_print(cmd, "\t\tNo AP found at this AP#0x%" PRIx64, ap->ap_num);
2092  return ERROR_FAIL;
2093  }
2094 
2095  command_print(cmd, "\t\tType is %s", ap_type_to_description(apid & AP_TYPE_MASK));
2096 
2097  /* NOTE: a MEM-AP may have a single CoreSight component that's
2098  * not a ROM table ... or have no such components at all.
2099  */
2100  const unsigned int class = (apid & AP_REG_IDR_CLASS_MASK) >> AP_REG_IDR_CLASS_SHIFT;
2101 
2102  if (class == AP_REG_IDR_CLASS_MEM_AP) {
2103  if (is_64bit_ap(ap))
2104  invalid_entry = 0xFFFFFFFFFFFFFFFFull;
2105  else
2106  invalid_entry = 0xFFFFFFFFul;
2107 
2108  command_print(cmd, "%sMEM-AP BASE " TARGET_ADDR_FMT, tabs, dbgbase);
2109 
2110  if (dbgbase == invalid_entry || (dbgbase & 0x3) == 0x2) {
2111  command_print(cmd, "\t\tNo ROM table present");
2112  } else {
2113  if (dbgbase & 0x01)
2114  command_print(cmd, "\t\tValid ROM table present");
2115  else
2116  command_print(cmd, "\t\tROM table in legacy format");
2117  }
2118  }
2119 
2120  return ERROR_OK;
2121 }
2122 
2123 static int dap_info_cs_component(int retval, struct cs_component_vals *v, int depth, void *priv)
2124 {
2125  struct command_invocation *cmd = priv;
2126 
2127  if (depth > ROM_TABLE_MAX_DEPTH) {
2128  command_print(cmd, "\tTables too deep");
2129  return ERROR_FAIL;
2130  }
2131 
2132  if (v->mode == CS_ACCESS_MEM_AP)
2133  command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, v->component_base);
2134 
2135  if (retval != ERROR_OK) {
2136  command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
2137  return retval;
2138  }
2139 
2140  if (!is_valid_arm_cs_cidr(v->cid)) {
2141  command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, v->cid);
2142  return ERROR_OK; /* Don't abort recursion */
2143  }
2144 
2145  /* component may take multiple 4K pages */
2146  uint32_t size = ARM_CS_PIDR_SIZE(v->pid);
2147  if (size > 0)
2148  command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, v->component_base - 0x1000 * size);
2149 
2150  command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, v->pid);
2151 
2152  const unsigned int part_num = ARM_CS_PIDR_PART(v->pid);
2153  unsigned int designer_id = ARM_CS_PIDR_DESIGNER(v->pid);
2154 
2155  if (v->pid & ARM_CS_PIDR_JEDEC) {
2156  /* JEP106 code */
2157  command_print(cmd, "\t\tDesigner is 0x%03x, %s",
2158  designer_id, jep106_manufacturer(designer_id));
2159  } else {
2160  /* Legacy ASCII ID, clear invalid bits */
2161  designer_id &= 0x7f;
2162  command_print(cmd, "\t\tDesigner ASCII code 0x%02x, %s",
2163  designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
2164  }
2165 
2166  const struct dap_part_nums *partnum = pidr_to_part_num(designer_id, part_num);
2167  command_print(cmd, "\t\tPart is 0x%03x, %s %s", part_num, partnum->type, partnum->full);
2168 
2169  const unsigned int class = ARM_CS_CIDR_CLASS(v->cid);
2170  command_print(cmd, "\t\tComponent class is 0x%x, %s", class, class_description[class]);
2171 
2172  if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
2173  if (v->devtype_memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK)
2174  command_print(cmd, "\t\tMEMTYPE system memory present on bus");
2175  else
2176  command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
2177  return ERROR_OK;
2178  }
2179 
2180  if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
2181  dap_devtype_display(cmd, v->devtype_memtype);
2182 
2183  /* REVISIT also show ARM_CS_C9_DEVID */
2184 
2185  if ((v->devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
2186  return ERROR_OK;
2187 
2188  unsigned int architect_id = ARM_CS_C9_DEVARCH_ARCHITECT(v->devarch);
2189  unsigned int revision = ARM_CS_C9_DEVARCH_REVISION(v->devarch);
2190  command_print(cmd, "\t\tDev Arch is 0x%08" PRIx32 ", %s \"%s\" rev.%u", v->devarch,
2191  jep106_manufacturer(architect_id), class0x9_devarch_description(v->devarch),
2192  revision);
2193 
2194  if ((v->devarch & DEVARCH_ID_MASK) == DEVARCH_ROM_C_0X9) {
2195  command_print(cmd, "\t\tType is ROM table");
2196 
2197  if (v->devid & ARM_CS_C9_DEVID_SYSMEM_MASK)
2198  command_print(cmd, "\t\tMEMTYPE system memory present on bus");
2199  else
2200  command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
2201  }
2202  return ERROR_OK;
2203  }
2204 
2205  /* Class other than 0x1 and 0x9 */
2206  return ERROR_OK;
2207 }
2208 
2209 static int dap_info_rom_table_entry(int retval, int depth,
2210  unsigned int offset, uint64_t romentry, void *priv)
2211 {
2212  struct command_invocation *cmd = priv;
2213  char tabs[16] = "";
2214 
2215  if (depth)
2216  snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
2217 
2218  if (retval != ERROR_OK) {
2219  command_print(cmd, "\t%sROMTABLE[0x%x] Read error", tabs, offset);
2220  command_print(cmd, "\t\tUnable to continue");
2221  command_print(cmd, "\t%s\tStop parsing of ROM table", tabs);
2222  return retval;
2223  }
2224 
2225  command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%08" PRIx64,
2226  tabs, offset, romentry);
2227 
2228  if (romentry == 0) {
2229  command_print(cmd, "\t%s\tEnd of ROM table", tabs);
2230  return ERROR_OK;
2231  }
2232 
2233  if (!(romentry & ARM_CS_ROMENTRY_PRESENT)) {
2234  command_print(cmd, "\t\tComponent not present");
2235  return ERROR_OK;
2236  }
2237 
2238  return ERROR_OK;
2239 }
2240 
2241 int dap_info_command(struct command_invocation *cmd, struct adiv5_ap *ap)
2242 {
2243  struct rtp_ops dap_info_ops = {
2244  .ap_header = dap_info_ap_header,
2245  .mem_ap_header = dap_info_mem_ap_header,
2246  .cs_component = dap_info_cs_component,
2247  .rom_table_entry = dap_info_rom_table_entry,
2248  .priv = cmd,
2249  };
2250 
2251  return rtp_ap(&dap_info_ops, ap, 0);
2252 }
2253 
2254 /* Actions for dap_lookup_cs_component() */
2255 
2256 struct dap_lookup_data {
2257  /* input */
2258  unsigned int idx;
2259  unsigned int type;
2260  /* output */
2261  uint64_t component_base;
2262  uint64_t ap_num;
2263 };
2264 
2265 static int dap_lookup_cs_component_cs_component(int retval,
2266  struct cs_component_vals *v, int depth, void *priv)
2267 {
2268  struct dap_lookup_data *lookup = priv;
2269 
2270  if (retval != ERROR_OK)
2271  return retval;
2272 
2273  if (!is_valid_arm_cs_cidr(v->cid))
2274  return ERROR_OK;
2275 
2276  const unsigned int class = ARM_CS_CIDR_CLASS(v->cid);
2277  if (class != ARM_CS_CLASS_0X9_CS_COMPONENT)
2278  return ERROR_OK;
2279 
2280  if ((v->devtype_memtype & ARM_CS_C9_DEVTYPE_MASK) != lookup->type)
2281  return ERROR_OK;
2282 
2283  if (lookup->idx) {
2284  /* search for next one */
2285  --lookup->idx;
2286  return ERROR_OK;
2287  }
2288 
2289  /* Found! */
2290  lookup->component_base = v->component_base;
2291  lookup->ap_num = v->ap->ap_num;
2292  return CORESIGHT_COMPONENT_FOUND;
2293 }
2294 
2295 int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type,
2296  target_addr_t *addr, int32_t core_id)
2297 {
2298  struct dap_lookup_data lookup = {
2299  .type = type,
2300  .idx = core_id,
2301  };
2302  struct rtp_ops dap_lookup_cs_component_ops = {
2303  .ap_header = NULL,
2304  .mem_ap_header = NULL,
2305  .cs_component = dap_lookup_cs_component_cs_component,
2306  .rom_table_entry = NULL,
2307  .priv = &lookup,
2308  };
2309 
2310  int retval = rtp_ap(&dap_lookup_cs_component_ops, ap, 0);
2311  if (retval == CORESIGHT_COMPONENT_FOUND) {
2312  if (lookup.ap_num != ap->ap_num) {
2313  /* TODO: handle search from root ROM table */
2314  LOG_DEBUG("CS lookup ended in AP # 0x%" PRIx64 ". Ignore it", lookup.ap_num);
2315  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2316  }
2317  LOG_DEBUG("CS lookup found at 0x%" PRIx64, lookup.component_base);
2318  *addr = lookup.component_base;
2319  return ERROR_OK;
2320  }
2321  if (retval != ERROR_OK) {
2322  LOG_DEBUG("CS lookup error %d", retval);
2323  return retval;
2324  }
2325  LOG_DEBUG("CS lookup not found");
2326  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2327 }
2328 
2329 enum adiv5_cfg_param {
2330  CFG_DAP,
2331  CFG_AP_NUM,
2332  CFG_BASEADDR,
2333  CFG_CTIBASE, /* DEPRECATED */
2334 };
2335 
2336 static const struct jim_nvp nvp_config_opts[] = {
2337  { .name = "-dap", .value = CFG_DAP },
2338  { .name = "-ap-num", .value = CFG_AP_NUM },
2339  { .name = "-baseaddr", .value = CFG_BASEADDR },
2340  { .name = "-ctibase", .value = CFG_CTIBASE }, /* DEPRECATED */
2341  { .name = NULL, .value = -1 }
2342 };
2343 
2344 static int adiv5_jim_spot_configure(struct jim_getopt_info *goi,
2345  struct adiv5_dap **dap_p, uint64_t *ap_num_p, uint32_t *base_p)
2346 {
2347  assert(dap_p && ap_num_p);
2348 
2349  if (!goi->argc)
2350  return JIM_OK;
2351 
2352  Jim_SetEmptyResult(goi->interp);
2353 
2354  struct jim_nvp *n;
2355  int e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts,
2356  goi->argv[0], &n);
2357  if (e != JIM_OK)
2358  return JIM_CONTINUE;
2359 
2360  /* base_p can be NULL, then '-baseaddr' option is treated as unknown */
2361  if (!base_p && (n->value == CFG_BASEADDR || n->value == CFG_CTIBASE))
2362  return JIM_CONTINUE;
2363 
2364  e = jim_getopt_obj(goi, NULL);
2365  if (e != JIM_OK)
2366  return e;
2367 
2368  switch (n->value) {
2369  case CFG_DAP:
2370  if (goi->is_configure) {
2371  Jim_Obj *o_t;
2372  struct adiv5_dap *dap;
2373  e = jim_getopt_obj(goi, &o_t);
2374  if (e != JIM_OK)
2375  return e;
2376  dap = dap_instance_by_jim_obj(goi->interp, o_t);
2377  if (!dap) {
2378  const char *dap_name = Jim_GetString(o_t, NULL);
2379  Jim_SetResultFormatted(goi->interp, "DAP '%s' not found",
2380  dap_name);
2381  return JIM_ERR;
2382  }
2383  if (*dap_p && *dap_p != dap) {
2384  Jim_SetResultString(goi->interp,
2385  "DAP assignment cannot be changed!", -1);
2386  return JIM_ERR;
2387  }
2388  *dap_p = dap;
2389  } else {
2390  if (goi->argc)
2391  goto err_no_param;
2392  if (!*dap_p) {
2393  Jim_SetResultString(goi->interp, "DAP not configured", -1);
2394  return JIM_ERR;
2395  }
2396  Jim_SetResultString(goi->interp, adiv5_dap_name(*dap_p), -1);
2397  }
2398  break;
2399 
2400  case CFG_AP_NUM:
2401  if (goi->is_configure) {
2402  /* jim_wide is a signed 64 bits int, ap_num is unsigned with max 52 bits */
2403  jim_wide ap_num;
2404  e = jim_getopt_wide(goi, &ap_num);
2405  if (e != JIM_OK)
2406  return e;
2407  /* we still don't know dap->adi_version */
2408  if (ap_num < 0 || (ap_num > DP_APSEL_MAX && (ap_num & 0xfff))) {
2409  Jim_SetResultString(goi->interp, "Invalid AP number!", -1);
2410  return JIM_ERR;
2411  }
2412  *ap_num_p = ap_num;
2413  } else {
2414  if (goi->argc)
2415  goto err_no_param;
2416  if (*ap_num_p == DP_APSEL_INVALID) {
2417  Jim_SetResultString(goi->interp, "AP number not configured", -1);
2418  return JIM_ERR;
2419  }
2420  Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *ap_num_p));
2421  }
2422  break;
2423 
2424  case CFG_CTIBASE:
2425  LOG_WARNING("DEPRECATED! use \'-baseaddr' not \'-ctibase\'");
2426  /* fall through */
2427  case CFG_BASEADDR:
2428  if (goi->is_configure) {
2429  jim_wide base;
2430  e = jim_getopt_wide(goi, &base);
2431  if (e != JIM_OK)
2432  return e;
2433  *base_p = (uint32_t)base;
2434  } else {
2435  if (goi->argc)
2436  goto err_no_param;
2437  Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *base_p));
2438  }
2439  break;
2440  };
2441 
2442  return JIM_OK;
2443 
2444 err_no_param:
2445  Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "NO PARAMS");
2446  return JIM_ERR;
2447 }
2448 
2449 int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi,
2450  struct adiv5_private_config *pc, enum adiv5_configure_dap_optional optional)
2451 {
2452  int e;
2453 
2454  if (!pc) {
2455  pc = (struct adiv5_private_config *)target->private_config;
2456  if (!pc) {
2457  pc = calloc(1, sizeof(struct adiv5_private_config));
2458  if (!pc) {
2459  LOG_ERROR("Out of memory");
2460  return JIM_ERR;
2461  }
2462  pc->ap_num = DP_APSEL_INVALID;
2463  target->private_config = pc;
2464  }
2465  }
2466 
2467  if (optional == ADI_CONFIGURE_DAP_COMPULSORY)
2468  target->has_dap = true;
2469 
2470  e = adiv5_jim_spot_configure(goi, &pc->dap, &pc->ap_num, NULL);
2471  if (e != JIM_OK)
2472  return e;
2473 
2474  if (pc->dap && !target->dap_configured) {
2475  if (target->tap_configured) {
2476  pc->dap = NULL;
2477  Jim_SetResultString(goi->interp,
2478  "-chain-position and -dap configparams are mutually exclusive!", -1);
2479  return JIM_ERR;
2480  }
2481  target->tap = pc->dap->tap;
2482  target->dap_configured = true;
2483  target->has_dap = true;
2484  }
2485 
2486  return JIM_OK;
2487 }
2488 
2489 int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
2490 {
2491  return adiv5_jim_configure_ext(target, goi, NULL, ADI_CONFIGURE_DAP_COMPULSORY);
2492 }
2493 
2494 int adiv5_verify_config(struct adiv5_private_config *pc)
2495 {
2496  if (!pc)
2497  return ERROR_FAIL;
2498 
2499  if (!pc->dap)
2500  return ERROR_FAIL;
2501 
2502  return ERROR_OK;
2503 }
2504 
2505 int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg,
2506  struct jim_getopt_info *goi)
2507 {
2508  return adiv5_jim_spot_configure(goi, &cfg->dap, &cfg->ap_num, &cfg->base);
2509 }
2510 
2511 int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p)
2512 {
2513  p->dap = NULL;
2514  p->ap_num = DP_APSEL_INVALID;
2515  p->base = 0;
2516  return ERROR_OK;
2517 }
2518 
2519 COMMAND_HANDLER(handle_dap_info_command)
2520 {
2521  struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2522  uint64_t apsel;
2523 
2524  switch (CMD_ARGC) {
2525  case 0:
2526  apsel = dap->apsel;
2527  break;
2528  case 1:
2529  if (!strcmp(CMD_ARGV[0], "root")) {
2530  if (!is_adiv6(dap)) {
2531  command_print(CMD, "Option \"root\" not allowed with ADIv5 DAP");
2532  return ERROR_COMMAND_ARGUMENT_INVALID;
2533  }
2534  int retval = adiv6_dap_read_baseptr(CMD, dap, &apsel);
2535  if (retval != ERROR_OK) {
2536  command_print(CMD, "Failed reading DAP baseptr");
2537  return retval;
2538  }
2539  break;
2540  }
2541  COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
2542  if (!is_ap_num_valid(dap, apsel)) {
2543  command_print(CMD, "Invalid AP number");
2544  return ERROR_COMMAND_ARGUMENT_INVALID;
2545  }
2546  break;
2547  default:
2548  return ERROR_COMMAND_SYNTAX_ERROR;
2549  }
2550 
2551  struct adiv5_ap *ap = dap_get_ap(dap, apsel);
2552  if (!ap) {
2553  command_print(CMD, "Cannot get AP");
2554  return ERROR_FAIL;
2555  }
2556 
2557  int retval = dap_info_command(CMD, ap);
2558  dap_put_ap(ap);
2559  return retval;
2560 }
2561 
2562 COMMAND_HANDLER(dap_baseaddr_command)
2563 {
2564  struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2565  uint64_t apsel;
2566  uint32_t baseaddr_lower, baseaddr_upper;
2567  struct adiv5_ap *ap;
2568  target_addr_t baseaddr;
2569  int retval;
2570 
2571  baseaddr_upper = 0;
2572 
2573  switch (CMD_ARGC) {
2574  case 0:
2575  apsel = dap->apsel;
2576  break;
2577  case 1:
2578  COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
2579  if (!is_ap_num_valid(dap, apsel)) {
2580  command_print(CMD, "Invalid AP number");
2581  return ERROR_COMMAND_ARGUMENT_INVALID;
2582  }
2583  break;
2584  default:
2585  return ERROR_COMMAND_SYNTAX_ERROR;
2586  }
2587 
2588  /* NOTE: assumes we're talking to a MEM-AP, which
2589  * has a base address. There are other kinds of AP,
2590  * though they're not common for now. This should
2591  * use the ID register to verify it's a MEM-AP.
2592  */
2593 
2594  ap = dap_get_ap(dap, apsel);
2595  if (!ap) {
2596  command_print(CMD, "Cannot get AP");
2597  return ERROR_FAIL;
2598  }
2599 
2600  retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE(dap), &baseaddr_lower);
2601 
2602  if (retval == ERROR_OK && ap->cfg_reg == MEM_AP_REG_CFG_INVALID)
2603  retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG(dap), &ap->cfg_reg);
2604 
2605  if (retval == ERROR_OK && (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap))) {
2606  /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
2607  retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64(dap), &baseaddr_upper);
2608  }
2609 
2610  if (retval == ERROR_OK)
2611  retval = dap_run(dap);
2612  dap_put_ap(ap);
2613  if (retval != ERROR_OK)
2614  return retval;
2615 
2616  if (is_64bit_ap(ap)) {
2617  baseaddr = (((target_addr_t)baseaddr_upper) << 32) | baseaddr_lower;
2618  command_print(CMD, "0x%016" PRIx64, baseaddr);
2619  } else
2620  command_print(CMD, "0x%08" PRIx32, baseaddr_lower);
2621 
2622  return ERROR_OK;
2623 }
2624 
2625 COMMAND_HANDLER(dap_memaccess_command)
2626 {
2627  struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2628  struct adiv5_ap *ap;
2629  uint32_t memaccess_tck;
2630 
2631  switch (CMD_ARGC) {
2632  case 0:
2633  ap = dap_get_ap(dap, dap->apsel);
2634  if (!ap) {
2635  command_print(CMD, "Cannot get AP");
2636  return ERROR_FAIL;
2637  }
2638  memaccess_tck = ap->memaccess_tck;
2639  break;
2640  case 1:
2641  ap = dap_get_config_ap(dap, dap->apsel);
2642  if (!ap) {
2643  command_print(CMD, "Cannot get AP");
2644  return ERROR_FAIL;
2645  }
2646  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
2647  ap->memaccess_tck = memaccess_tck;
2648  break;
2649  default:
2650  return ERROR_COMMAND_SYNTAX_ERROR;
2651  }
2652 
2653  dap_put_ap(ap);
2654 
2655  command_print(CMD, "memory bus access delay set to %" PRIu32 " tck",
2656  memaccess_tck);
2657 
2658  return ERROR_OK;
2659 }
2660 
2661 COMMAND_HANDLER(dap_apsel_command)
2662 {
2663  struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2664  uint64_t apsel;
2665 
2666  switch (CMD_ARGC) {
2667  case 0:
2668  command_print(CMD, "0x%" PRIx64, dap->apsel);
2669  return ERROR_OK;
2670  case 1:
2671  COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
2672  if (!is_ap_num_valid(dap, apsel)) {
2673  command_print(CMD, "Invalid AP number");
2674  return ERROR_COMMAND_ARGUMENT_INVALID;
2675  }
2676  break;
2677  default:
2678  return ERROR_COMMAND_SYNTAX_ERROR;
2679  }
2680 
2681  dap->apsel = apsel;
2682  return ERROR_OK;
2683 }
2684 
2685 COMMAND_HANDLER(dap_apcsw_command)
2686 {
2687  struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2688  struct adiv5_ap *ap;
2689  uint32_t csw_val, csw_mask;
2690 
2691  switch (CMD_ARGC) {
2692  case 0:
2693  ap = dap_get_ap(dap, dap->apsel);
2694  if (!ap) {
2695  command_print(CMD, "Cannot get AP");
2696  return ERROR_FAIL;
2697  }
2698  command_print(CMD, "AP#0x%" PRIx64 " selected, csw 0x%8.8" PRIx32,
2699  dap->apsel, ap->csw_default);
2700  break;
2701  case 1:
2702  if (strcmp(CMD_ARGV[0], "default") == 0)
2703  csw_val = CSW_AHB_DEFAULT;
2704  else
2705  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
2706 
2707  if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
2708  LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
2709  return ERROR_COMMAND_ARGUMENT_INVALID;
2710  }
2711  ap = dap_get_config_ap(dap, dap->apsel);
2712  if (!ap) {
2713  command_print(CMD, "Cannot get AP");
2714  return ERROR_FAIL;
2715  }
2716  ap->csw_default = csw_val;
2717  break;
2718  case 2:
2719  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
2720  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
2721  if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
2722  LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
2723  return ERROR_COMMAND_ARGUMENT_INVALID;
2724  }
2725  ap = dap_get_config_ap(dap, dap->apsel);
2726  if (!ap) {
2727  command_print(CMD, "Cannot get AP");
2728  return ERROR_FAIL;
2729  }
2730  ap->csw_default = (ap->csw_default & ~csw_mask) | (csw_val & csw_mask);
2731  break;
2732  default:
2733  return ERROR_COMMAND_SYNTAX_ERROR;
2734  }
2735  dap_put_ap(ap);
2736 
2737  return ERROR_OK;
2738 }
2739 
2740 
2741 
2742 COMMAND_HANDLER(dap_apid_command)
2743 {
2744  struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2745  uint64_t apsel;
2746  uint32_t apid;
2747  int retval;
2748 
2749  switch (CMD_ARGC) {
2750  case 0:
2751  apsel = dap->apsel;
2752  break;
2753  case 1:
2754  COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
2755  if (!is_ap_num_valid(dap, apsel)) {
2756  command_print(CMD, "Invalid AP number");
2757  return ERROR_COMMAND_ARGUMENT_INVALID;
2758  }
2759  break;
2760  default:
2761  return ERROR_COMMAND_SYNTAX_ERROR;
2762  }
2763 
2764  struct adiv5_ap *ap = dap_get_ap(dap, apsel);
2765  if (!ap) {
2766  command_print(CMD, "Cannot get AP");
2767  return ERROR_FAIL;
2768  }
2769  retval = dap_queue_ap_read(ap, AP_REG_IDR(dap), &apid);
2770  if (retval != ERROR_OK) {
2771  dap_put_ap(ap);
2772  return retval;
2773  }
2774  retval = dap_run(dap);
2775  dap_put_ap(ap);
2776  if (retval != ERROR_OK)
2777  return retval;
2778 
2779  command_print(CMD, "0x%8.8" PRIx32, apid);
2780 
2781  return retval;
2782 }
2783 
2784 COMMAND_HANDLER(dap_apreg_command)
2785 {
2786  struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2787  uint64_t apsel;
2788  uint32_t reg, value;
2789  int retval;
2790 
2791  if (CMD_ARGC < 2 || CMD_ARGC > 3)
2792  return ERROR_COMMAND_SYNTAX_ERROR;
2793 
2794  COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
2795  if (!is_ap_num_valid(dap, apsel)) {
2796  command_print(CMD, "Invalid AP number");
2797  return ERROR_COMMAND_ARGUMENT_INVALID;
2798  }
2799 
2800  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
2801  if (is_adiv6(dap)) {
2802  if (reg >= 4096 || (reg & 3)) {
2803  command_print(CMD, "Invalid reg value (should be less than 4096 and 4 bytes aligned)");
2804  return ERROR_COMMAND_ARGUMENT_INVALID;
2805  }
2806  } else { /* ADI version 5 */
2807  if (reg >= 256 || (reg & 3)) {
2808  command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2809  return ERROR_COMMAND_ARGUMENT_INVALID;
2810  }
2811  }
2812 
2813  struct adiv5_ap *ap = dap_get_ap(dap, apsel);
2814  if (!ap) {
2815  command_print(CMD, "Cannot get AP");
2816  return ERROR_FAIL;
2817  }
2818 
2819  if (CMD_ARGC == 3) {
2820  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2821  /* see if user supplied register address is a match for the CSW or TAR register */
2822  if (reg == MEM_AP_REG_CSW(dap)) {
2823  ap->csw_value = 0; /* invalid, in case write fails */
2824  retval = dap_queue_ap_write(ap, reg, value);
2825  if (retval == ERROR_OK)
2826  ap->csw_value = value;
2827  } else if (reg == MEM_AP_REG_TAR(dap)) {
2828  retval = dap_queue_ap_write(ap, reg, value);
2829  if (retval == ERROR_OK)
2830  ap->tar_value = (ap->tar_value & ~0xFFFFFFFFull) | value;
2831  else {
2832  /* To track independent writes to TAR and TAR64, two tar_valid flags */
2833  /* should be used. To keep it simple, tar_valid is only invalidated on a */
2834  /* write fail. This approach causes a later re-write of the TAR and TAR64 */
2835  /* if tar_valid is false. */
2836  ap->tar_valid = false;
2837  }
2838  } else if (reg == MEM_AP_REG_TAR64(dap)) {
2839  retval = dap_queue_ap_write(ap, reg, value);
2840  if (retval == ERROR_OK)
2841  ap->tar_value = (ap->tar_value & 0xFFFFFFFFull) | (((target_addr_t)value) << 32);
2842  else {
2843  /* See above comment for the MEM_AP_REG_TAR failed write case */
2844  ap->tar_valid = false;
2845  }
2846  } else {
2847  retval = dap_queue_ap_write(ap, reg, value);
2848  }
2849  } else {
2850  retval = dap_queue_ap_read(ap, reg, &value);
2851  }
2852  if (retval == ERROR_OK)
2853  retval = dap_run(dap);
2854 
2855  dap_put_ap(ap);
2856 
2857  if (retval != ERROR_OK)
2858  return retval;
2859 
2860  if (CMD_ARGC == 2)
2861  command_print(CMD, "0x%08" PRIx32, value);
2862 
2863  return retval;
2864 }
2865 
2866 COMMAND_HANDLER(dap_dpreg_command)
2867 {
2868  struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2869  uint32_t reg, value;
2870  int retval;
2871 
2872  if (CMD_ARGC < 1 || CMD_ARGC > 2)
2873  return ERROR_COMMAND_SYNTAX_ERROR;
2874 
2875  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg);
2876  if (reg >= 256 || (reg & 3)) {
2877  command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2878  return ERROR_COMMAND_ARGUMENT_INVALID;
2879  }
2880 
2881  if (CMD_ARGC == 2) {
2882  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2883  retval = dap_queue_dp_write(dap, reg, value);
2884  } else {
2885  retval = dap_queue_dp_read(dap, reg, &value);
2886  }
2887  if (retval == ERROR_OK)
2888  retval = dap_run(dap);
2889 
2890  if (retval != ERROR_OK)
2891  return retval;
2892 
2893  if (CMD_ARGC == 1)
2894  command_print(CMD, "0x%08" PRIx32, value);
2895 
2896  return retval;
2897 }
2898 
2899 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
2900 {
2901  struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2902  return CALL_COMMAND_HANDLER(handle_command_parse_bool, &dap->ti_be_32_quirks,
2903  "TI BE-32 quirks mode");
2904 }
2905 
2906 COMMAND_HANDLER(dap_nu_npcx_quirks_command)
2907 {
2908  struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2909  return CALL_COMMAND_HANDLER(handle_command_parse_bool, &dap->nu_npcx_quirks,
2910  "Nuvoton NPCX quirks mode");
2911 }
2912 
2913 const struct command_registration dap_instance_commands[] = {
2914  {
2915  .name = "info",
2916  .handler = handle_dap_info_command,
2917  .mode = COMMAND_EXEC,
2918  .help = "display ROM table for specified MEM-AP (default currently selected AP) "
2919  "or the ADIv6 root ROM table",
2920  .usage = "[ap_num | 'root']",
2921  },
2922  {
2923  .name = "apsel",
2924  .handler = dap_apsel_command,
2925  .mode = COMMAND_ANY,
2926  .help = "Set the currently selected AP (default 0) "
2927  "and display the result",
2928  .usage = "[ap_num]",
2929  },
2930  {
2931  .name = "apcsw",
2932  .handler = dap_apcsw_command,
2933  .mode = COMMAND_ANY,
2934  .help = "Set CSW default bits",
2935  .usage = "[value [mask]]",
2936  },
2937 
2938  {
2939  .name = "apid",
2940  .handler = dap_apid_command,
2941  .mode = COMMAND_EXEC,
2942  .help = "return ID register from AP "
2943  "(default currently selected AP)",
2944  .usage = "[ap_num]",
2945  },
2946  {
2947  .name = "apreg",
2948  .handler = dap_apreg_command,
2949  .mode = COMMAND_EXEC,
2950  .help = "read/write a register from AP "
2951  "(reg is byte address of a word register, like 0 4 8...)",
2952  .usage = "ap_num reg [value]",
2953  },
2954  {
2955  .name = "dpreg",
2956  .handler = dap_dpreg_command,
2957  .mode = COMMAND_EXEC,
2958  .help = "read/write a register from DP "
2959  "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
2960  .usage = "reg [value]",
2961  },
2962  {
2963  .name = "baseaddr",
2964  .handler = dap_baseaddr_command,
2965  .mode = COMMAND_EXEC,
2966  .help = "return debug base address from MEM-AP "
2967  "(default currently selected AP)",
2968  .usage = "[ap_num]",
2969  },
2970  {
2971  .name = "memaccess",
2972  .handler = dap_memaccess_command,
2973  .mode = COMMAND_EXEC,
2974  .help = "set/get number of extra tck for MEM-AP memory "
2975  "bus access [0-255]",
2976  .usage = "[cycles]",
2977  },
2978  {
2979  .name = "ti_be_32_quirks",
2980  .handler = dap_ti_be_32_quirks_command,
2981  .mode = COMMAND_CONFIG,
2982  .help = "set/get quirks mode for TI TMS450/TMS570 processors",
2983  .usage = "[enable]",
2984  },
2985  {
2986  .name = "nu_npcx_quirks",
2987  .handler = dap_nu_npcx_quirks_command,
2988  .mode = COMMAND_CONFIG,
2989  .help = "set/get quirks mode for Nuvoton NPCX controllers",
2990  .usage = "[enable]",
2991  },
2992  COMMAND_REGISTRATION_DONE
2993 };
IS_ALIGNED
#define IS_ALIGNED(x, a)
Definition: align.h:22
arm.h
Holds the interface to ARM cores.
DEVARCH_MEM_AP
#define DEVARCH_MEM_AP
Definition: arm_adi_v5.c:1046
dap_get_config_ap
struct adiv5_ap * dap_get_config_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1206
mem_ap_write
static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address, bool addrinc)
Synchronous write of a block of memory, using a specific access size.
Definition: arm_adi_v5.c:482
dap_info_mem_ap_header
static int dap_info_mem_ap_header(int retval, struct adiv5_ap *ap, target_addr_t dbgbase, uint32_t apid, int depth, void *priv)
Definition: arm_adi_v5.c:2069
mem_ap_read_buf
int mem_ap_read_buf(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:730
dap_info_ap_header
static int dap_info_ap_header(struct adiv5_ap *ap, int depth, void *priv)
Definition: arm_adi_v5.c:2056
dap_queue_read_reg
static int dap_queue_read_reg(enum coresight_access_mode mode, struct adiv5_ap *ap, uint64_t component_base, unsigned int reg, uint32_t *value)
Helper to read CoreSight component's registers, either on the bus behind a MEM-AP or directly in the ...
Definition: arm_adi_v5.c:1335
class_description
static const char * class_description[16]
Definition: arm_adi_v5.c:992
rtp_ap
static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
Definition: arm_adi_v5.c:1999
nvp_config_opts
static const struct jim_nvp nvp_config_opts[]
Definition: arm_adi_v5.c:2336
COMMAND_HANDLER
COMMAND_HANDLER(handle_dap_info_command)
Definition: arm_adi_v5.c:2519
DEVARCH_ID_MASK
#define DEVARCH_ID_MASK
Definition: arm_adi_v5.c:1045
dap_lookup_cs_component
int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type, target_addr_t *addr, int32_t core_id)
Definition: arm_adi_v5.c:2295
rtp_rom_loop
static int rtp_rom_loop(enum coresight_access_mode mode, const struct rtp_ops *ops, struct adiv5_ap *ap, target_addr_t base_address, int depth, unsigned int width, unsigned int max_entries)
Definition: arm_adi_v5.c:1862
mem_ap_read_buf_noincr
int mem_ap_read_buf_noincr(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:742
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static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, target_addr_t address)
Definition: arm_adi_v5.c:91
mem_ap_setup_tar
static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar)
Definition: arm_adi_v5.c:118
adiv5_verify_config
int adiv5_verify_config(struct adiv5_private_config *pc)
Definition: arm_adi_v5.c:2494
DEVARCH_UNKNOWN_V2
#define DEVARCH_UNKNOWN_V2
Definition: arm_adi_v5.c:1048
mem_ap_setup_transfer
static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, target_addr_t tar)
Queue transactions setting up transfer parameters for the currently selected MEM-AP.
Definition: arm_adi_v5.c:222
dap_info_command
int dap_info_command(struct command_invocation *cmd, struct adiv5_ap *ap)
Definition: arm_adi_v5.c:2241
mem_ap_read_u32
int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Asynchronous (queued) read of a word from memory or a system register.
Definition: arm_adi_v5.c:245
ap_type_to_description
static const char * ap_type_to_description(enum ap_type type)
Definition: arm_adi_v5.c:1077
adiv5_mem_ap_spot_init
int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p)
Definition: arm_adi_v5.c:2511
dap_info_cs_component
static int dap_info_cs_component(int retval, struct cs_component_vals *v, int depth, void *priv)
Definition: arm_adi_v5.c:2123
is_ap_in_use
static bool is_ap_in_use(struct adiv5_ap *ap)
Definition: arm_adi_v5.c:1158
mem_ap_write_u32
int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Asynchronous (queued) write of a word to memory or a system register.
Definition: arm_adi_v5.c:297
is_ap_num_valid
bool is_ap_num_valid(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1086
class0x9_devarch
static const struct @62 class0x9_devarch[]
adiv5_jim_spot_configure
static int adiv5_jim_spot_configure(struct jim_getopt_info *goi, struct adiv5_dap **dap_p, uint64_t *ap_num_p, uint32_t *base_p)
Definition: arm_adi_v5.c:2344
description
const char * description
Definition: arm_adi_v5.c:1018
type
enum ap_type type
Definition: arm_adi_v5.c:1063
adiv6_dap_read_baseptr
int adiv6_dap_read_baseptr(struct command_invocation *cmd, struct adiv5_dap *dap, uint64_t *baseptr)
Definition: arm_adi_v5.c:1274
class0x9_devarch_description
static const char * class0x9_devarch_description(uint32_t devarch)
Definition: arm_adi_v5.c:1050
arch_id
uint32_t arch_id
Definition: arm_adi_v5.c:1017
dap_info_rom_table_entry
static int dap_info_rom_table_entry(int retval, int depth, unsigned int offset, uint64_t romentry, void *priv)
Definition: arm_adi_v5.c:2209
adiv5_jim_configure
int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
Definition: arm_adi_v5.c:2489
dap_find_get_ap
int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
Definition: arm_adi_v5.c:1115
adiv5_cfg_param
adiv5_cfg_param
Definition: arm_adi_v5.c:2329
CFG_AP_NUM
@ CFG_AP_NUM
Definition: arm_adi_v5.c:2331
CFG_CTIBASE
@ CFG_CTIBASE
Definition: arm_adi_v5.c:2333
CFG_BASEADDR
@ CFG_BASEADDR
Definition: arm_adi_v5.c:2332
CFG_DAP
@ CFG_DAP
Definition: arm_adi_v5.c:2330
mem_ap_read_tar
static int mem_ap_read_tar(struct adiv5_ap *ap, target_addr_t *tar)
Definition: arm_adi_v5.c:138
mem_ap_write_buf_noincr
int mem_ap_write_buf_noincr(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:748
dap_to_jtag
int dap_to_jtag(struct adiv5_dap *dap)
Put the debug link into JTAG mode, if the target supports it.
Definition: arm_adi_v5.c:978
rtp_ops_rom_table_entry
static int rtp_ops_rom_table_entry(const struct rtp_ops *ops, int retval, int depth, unsigned int offset, uint64_t romentry)
Wrapper around struct rtp_ops::rom_table_entry.
Definition: arm_adi_v5.c:1835
adiv5_jim_configure_ext
int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi, struct adiv5_private_config *pc, enum adiv5_configure_dap_optional optional)
Definition: arm_adi_v5.c:2449
dap_dp_init_or_reconnect
int dap_dp_init_or_reconnect(struct adiv5_dap *dap)
Initialize a DAP or do reconnect if DAP is not accessible.
Definition: arm_adi_v5.c:865
dap_get_debugbase
static int dap_get_debugbase(struct adiv5_ap *ap, target_addr_t *dbgbase, uint32_t *apid)
Definition: arm_adi_v5.c:1238
dap_dp_init
int dap_dp_init(struct adiv5_dap *dap)
Initialize a DAP.
Definition: arm_adi_v5.c:787
ROM_TABLE_MAX_DEPTH
#define ROM_TABLE_MAX_DEPTH
Definition: arm_adi_v5.c:1848
mem_ap_setup_transfer_verify_size_packing
static int mem_ap_setup_transfer_verify_size_packing(struct adiv5_ap *ap, unsigned int size, target_addr_t address, bool addrinc, bool pack, unsigned int *this_size)
Queue transactions setting up transfer parameters for the currently selected MEM-AP.
Definition: arm_adi_v5.c:353
mem_ap_setup_csw
static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
Definition: arm_adi_v5.c:102
mem_ap_read_atomic_u32
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
Definition: arm_adi_v5.c:274
dap_to_swd
int dap_to_swd(struct adiv5_dap *dap)
Put the debug link into SWD mode, if the target supports it.
Definition: arm_adi_v5.c:960
DAP_POWER_DOMAIN_TIMEOUT
#define DAP_POWER_DOMAIN_TIMEOUT
Definition: arm_adi_v5.c:757
dap_get_ap
struct adiv5_ap * dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1197
dap_put_ap
int dap_put_ap(struct adiv5_ap *ap)
Definition: arm_adi_v5.c:1217
mem_ap_init
int mem_ap_init(struct adiv5_ap *ap)
Initialize a DAP.
Definition: arm_adi_v5.c:896
rtp_ops_mem_ap_header
static int rtp_ops_mem_ap_header(const struct rtp_ops *ops, int retval, struct adiv5_ap *ap, uint64_t dbgbase, uint32_t apid, int depth)
Wrapper around struct rtp_ops::mem_ap_header.
Definition: arm_adi_v5.c:1803
coresight_access_mode
coresight_access_mode
Method to access the CoreSight component.
Definition: arm_adi_v5.c:1306
CS_ACCESS_MEM_AP
@ CS_ACCESS_MEM_AP
Definition: arm_adi_v5.c:1308
CS_ACCESS_AP
@ CS_ACCESS_AP
Definition: arm_adi_v5.c:1307
mem_ap_write_buf
int mem_ap_write_buf(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:736
dap_devtype_display
static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
Definition: arm_adi_v5.c:1591
ap_types
static const struct @63 ap_types[]
rtp_ops_ap_header
static int rtp_ops_ap_header(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
Wrapper around struct rtp_ops::ap_header.
Definition: arm_adi_v5.c:1790
mem_ap_read
static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t adr, bool addrinc)
Synchronous read of a block of memory, using a specific access size.
Definition: arm_adi_v5.c:612
ARCH_ID
#define ARCH_ID(architect, archid)
Definition: arm_adi_v5.c:1011
dap_invalidate_cache
void dap_invalidate_cache(struct adiv5_dap *dap)
Invalidate cached DP select and cached TAR and CSW of all APs.
Definition: arm_adi_v5.c:764
dap_lookup_cs_component_cs_component
static int dap_lookup_cs_component_cs_component(int retval, struct cs_component_vals *v, int depth, void *priv)
Definition: arm_adi_v5.c:2265
rtp_ops_cs_component
static int rtp_ops_cs_component(const struct rtp_ops *ops, int retval, struct cs_component_vals *v, int depth)
Wrapper around struct rtp_ops::cs_component.
Definition: arm_adi_v5.c:1819
DEVARCH_ROM_C_0X9
#define DEVARCH_ROM_C_0X9
Definition: arm_adi_v5.c:1047
pidr_to_part_num
static const struct dap_part_nums * pidr_to_part_num(unsigned int designer_id, unsigned int part_num)
Definition: arm_adi_v5.c:1577
mem_ap_update_tar_cache
static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
Definition: arm_adi_v5.c:193
dap_instance_commands
const struct command_registration dap_instance_commands[]
Definition: arm_adi_v5.c:2913
rtp_read_cs_regs
static int rtp_read_cs_regs(enum coresight_access_mode mode, struct adiv5_ap *ap, target_addr_t component_base, struct cs_component_vals *v)
Read the CoreSight registers needed during ROM Table Parsing (RTP).
Definition: arm_adi_v5.c:1355
CORESIGHT_COMPONENT_FOUND
#define CORESIGHT_COMPONENT_FOUND
Value used only during lookup of a CoreSight component in ROM table.
Definition: arm_adi_v5.c:1856
mem_ap_get_tar_increment
static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
Definition: arm_adi_v5.c:165
_dap_get_ap
static struct adiv5_ap * _dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1163
adiv5_jim_mem_ap_spot_configure
int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg, struct jim_getopt_info *goi)
Definition: arm_adi_v5.c:2505
rtp_cs_component
static int rtp_cs_component(enum coresight_access_mode mode, const struct rtp_ops *ops, struct adiv5_ap *ap, target_addr_t dbgbase, bool *is_mem_ap, int depth)
Definition: arm_adi_v5.c:1940
mem_ap_setup_transfer_verify_size_packing_fallback
static int mem_ap_setup_transfer_verify_size_packing_fallback(struct adiv5_ap *ap, unsigned int size, target_addr_t address, bool addrinc, bool pack, unsigned int *this_size)
Queue transactions setting up transfer parameters for the currently selected MEM-AP.
Definition: arm_adi_v5.c:453
mem_ap_write_atomic_u32
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
Definition: arm_adi_v5.c:326
arm_adi_v5.h
This defines formats and data structures used to talk to ADIv5 entities.
dap_dp_poll_register
static int dap_dp_poll_register(struct adiv5_dap *dap, unsigned int reg, uint32_t mask, uint32_t value, int timeout)
Definition: arm_adi_v5.h:674
AP_TYPE_MASK
#define AP_TYPE_MASK
Definition: arm_adi_v5.h:233
CSW_ADDRINC_MASK
#define CSW_ADDRINC_MASK
Definition: arm_adi_v5.h:171
MEM_AP_REG_CSW
#define MEM_AP_REG_CSW(dap)
Definition: arm_adi_v5.h:145
CSW_256BIT
#define CSW_256BIT
Definition: arm_adi_v5.h:170
CSW_ADDRINC_PACKED
#define CSW_ADDRINC_PACKED
Definition: arm_adi_v5.h:174
SSTICKYERR
#define SSTICKYERR
Definition: arm_adi_v5.h:86
CSW_32BIT
#define CSW_32BIT
Definition: arm_adi_v5.h:167
is_64bit_ap
static bool is_64bit_ap(struct adiv5_ap *ap)
Definition: arm_adi_v5.h:511
dap_queue_dp_write
static int dap_queue_dp_write(struct adiv5_dap *dap, unsigned int reg, uint32_t data)
Queue a DP register write.
Definition: arm_adi_v5.h:573
AP_REG_IDR_CLASS_SHIFT
#define AP_REG_IDR_CLASS_SHIFT
Definition: arm_adi_v5.h:217
MEM_AP_REG_CFG
#define MEM_AP_REG_CFG(dap)
Definition: arm_adi_v5.h:155
CDBGPWRUPREQ
#define CDBGPWRUPREQ
Definition: arm_adi_v5.h:93
ap_type
ap_type
Definition: arm_adi_v5.h:487
AP_TYPE_APB_AP
@ AP_TYPE_APB_AP
Definition: arm_adi_v5.h:491
AP_TYPE_AXI_AP
@ AP_TYPE_AXI_AP
Definition: arm_adi_v5.h:492
AP_TYPE_APB4_AP
@ AP_TYPE_APB4_AP
Definition: arm_adi_v5.h:494
AP_TYPE_AHB3_AP
@ AP_TYPE_AHB3_AP
Definition: arm_adi_v5.h:490
AP_TYPE_COM_AP
@ AP_TYPE_COM_AP
Definition: arm_adi_v5.h:489
AP_TYPE_AHB5H_AP
@ AP_TYPE_AHB5H_AP
Definition: arm_adi_v5.h:496
AP_TYPE_JTAG_AP
@ AP_TYPE_JTAG_AP
Definition: arm_adi_v5.h:488
AP_TYPE_AXI5_AP
@ AP_TYPE_AXI5_AP
Definition: arm_adi_v5.h:495
AP_TYPE_AHB5_AP
@ AP_TYPE_AHB5_AP
Definition: arm_adi_v5.h:493
CSW_64BIT
#define CSW_64BIT
Definition: arm_adi_v5.h:168
dap_queue_ap_read
static int dap_queue_ap_read(struct adiv5_ap *ap, unsigned int reg, uint32_t *data)
Queue an AP register read.
Definition: arm_adi_v5.h:590
CSW_AHB_DEFAULT
#define CSW_AHB_DEFAULT
Definition: arm_adi_v5.h:193
MEM_AP_REG_TAR
#define MEM_AP_REG_TAR(dap)
Definition: arm_adi_v5.h:146
MEM_AP_REG_CFG_LD
#define MEM_AP_REG_CFG_LD
Definition: arm_adi_v5.h:208
CSW_16BIT
#define CSW_16BIT
Definition: arm_adi_v5.h:166
ARM_ID
#define ARM_ID
Definition: arm_adi_v5.h:28
dap_instance_by_jim_obj
struct adiv5_dap * dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o)
Definition: arm_dap.c:70
dap_send_sequence
static int dap_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
Send an adi-v5 sequence to the DAP.
Definition: arm_adi_v5.h:536
AP_REG_IDR_CLASS_MASK
#define AP_REG_IDR_CLASS_MASK
Definition: arm_adi_v5.h:216
adiv5_configure_dap_optional
adiv5_configure_dap_optional
Definition: arm_adi_v5.h:792
ADI_CONFIGURE_DAP_COMPULSORY
@ ADI_CONFIGURE_DAP_COMPULSORY
Definition: arm_adi_v5.h:793
CSW_ADDRINC_SINGLE
#define CSW_ADDRINC_SINGLE
Definition: arm_adi_v5.h:173
AP_REG_IDR_CLASS_MEM_AP
#define AP_REG_IDR_CLASS_MEM_AP
Definition: arm_adi_v5.h:225
DP_APSEL_INVALID
#define DP_APSEL_INVALID
Definition: arm_adi_v5.h:110
MEM_AP_REG_CFG_BE
#define MEM_AP_REG_CFG_BE
Definition: arm_adi_v5.h:206
DP_CTRL_STAT
#define DP_CTRL_STAT
Definition: arm_adi_v5.h:50
DP_BASEPTR0_VALID
#define DP_BASEPTR0_VALID
Definition: arm_adi_v5.h:79
DP_APSEL_MAX
#define DP_APSEL_MAX
Definition: arm_adi_v5.h:109
CORUNDETECT
#define CORUNDETECT
Definition: arm_adi_v5.h:82
CDBGPWRUPACK
#define CDBGPWRUPACK
Definition: arm_adi_v5.h:94
CSW_128BIT
#define CSW_128BIT
Definition: arm_adi_v5.h:169
adiv5_get_dap
struct adiv5_dap * adiv5_get_dap(struct arm_dap_object *obj)
Definition: arm_dap.c:66
CSW_8BIT
#define CSW_8BIT
Definition: arm_adi_v5.h:165
dap_queue_dp_read
static int dap_queue_dp_read(struct adiv5_dap *dap, unsigned int reg, uint32_t *data)
Queue a DP register read.
Definition: arm_adi_v5.h:555
SSTICKYORUN
#define SSTICKYORUN
Definition: arm_adi_v5.h:83
CSYSPWRUPACK
#define CSYSPWRUPACK
Definition: arm_adi_v5.h:96
MEM_AP_REG_CFG_LA
#define MEM_AP_REG_CFG_LA
Definition: arm_adi_v5.h:207
MEM_AP_REG_DRW
#define MEM_AP_REG_DRW(dap)
Definition: arm_adi_v5.h:148
DP_BASEPTR1
#define DP_BASEPTR1
Definition: arm_adi_v5.h:49
dap_dp_read_atomic
static int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned int reg, uint32_t *value)
Definition: arm_adi_v5.h:662
MEM_AP_REG_BASE
#define MEM_AP_REG_BASE(dap)
Definition: arm_adi_v5.h:156
CSW_ADDRINC_OFF
#define CSW_ADDRINC_OFF
Definition: arm_adi_v5.h:172
dap_queue_ap_write
static int dap_queue_ap_write(struct adiv5_ap *ap, unsigned int reg, uint32_t data)
Queue an AP register write.
Definition: arm_adi_v5.h:610
JTAG_TO_SWD
@ JTAG_TO_SWD
Definition: arm_adi_v5.h:238
SWD_TO_JTAG
@ SWD_TO_JTAG
Definition: arm_adi_v5.h:240
CSYSPWRUPREQ
#define CSYSPWRUPREQ
Definition: arm_adi_v5.h:95
MEM_AP_REG_BASE64
#define MEM_AP_REG_BASE64(dap)
Definition: arm_adi_v5.h:154
adiv5_dap_name
const char * adiv5_dap_name(struct adiv5_dap *self)
Definition: arm_dap.c:54
DP_BASEPTR0
#define DP_BASEPTR0
Definition: arm_adi_v5.h:48
MEM_AP_REG_BD0
#define MEM_AP_REG_BD0(dap)
Definition: arm_adi_v5.h:149
CSW_SIZE_MASK
#define CSW_SIZE_MASK
Definition: arm_adi_v5.h:164
is_adiv6
static bool is_adiv6(const struct adiv5_dap *dap)
Check if DAP is ADIv6.
Definition: arm_adi_v5.h:523
MEM_AP_REG_TAR64
#define MEM_AP_REG_TAR64(dap)
Definition: arm_adi_v5.h:147
dap_run
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
Definition: arm_adi_v5.h:648
AP_REG_IDR
#define AP_REG_IDR(dap)
Definition: arm_adi_v5.h:161
MEM_AP_REG_CFG_INVALID
#define MEM_AP_REG_CFG_INVALID
Definition: arm_adi_v5.h:209
arm_coresight.h
ARM_CS_CIDR3
#define ARM_CS_CIDR3
Definition: arm_coresight.h:44
ARM_CS_CLASS_0X1_ROM_TABLE
#define ARM_CS_CLASS_0X1_ROM_TABLE
Definition: arm_coresight.h:48
ARM_CS_PIDR2
#define ARM_CS_PIDR2
Definition: arm_coresight.h:21
ARM_CS_C9_DEVID_SYSMEM_MASK
#define ARM_CS_C9_DEVID_SYSMEM_MASK
Definition: arm_coresight.h:76
is_valid_arm_cs_cidr
static bool is_valid_arm_cs_cidr(uint32_t cidr)
Definition: arm_coresight.h:51
ARM_CS_C9_DEVTYPE_MASK
#define ARM_CS_C9_DEVTYPE_MASK
Definition: arm_coresight.h:87
ARM_CS_PIDR3
#define ARM_CS_PIDR3
Definition: arm_coresight.h:22
ARM_CS_PIDR_SIZE
#define ARM_CS_PIDR_SIZE(pidr)
Definition: arm_coresight.h:39
ARM_CS_CLASS_0X9_CS_COMPONENT
#define ARM_CS_CLASS_0X9_CS_COMPONENT
Definition: arm_coresight.h:49
ARM_CS_C9_DEVID
#define ARM_CS_C9_DEVID
Definition: arm_coresight.h:71
ARM_CS_CIDR1
#define ARM_CS_CIDR1
Definition: arm_coresight.h:42
ARM_CS_C9_DEVARCH
#define ARM_CS_C9_DEVARCH
Definition: arm_coresight.h:57
ARM_CS_PIDR0
#define ARM_CS_PIDR0
Definition: arm_coresight.h:19
ARM_CS_C9_DEVTYPE_SUB_SHIFT
#define ARM_CS_C9_DEVTYPE_SUB_SHIFT
Definition: arm_coresight.h:85
ARM_CS_CIDR_CLASS
#define ARM_CS_CIDR_CLASS(cidr)
Definition: arm_coresight.h:47
ARM_CS_C9_DEVARCH_REVISION
#define ARM_CS_C9_DEVARCH_REVISION(devarch)
Definition: arm_coresight.h:66
ARM_CS_ROMENTRY_PRESENT
#define ARM_CS_ROMENTRY_PRESENT
Definition: arm_coresight.h:97
ARM_CS_PIDR4
#define ARM_CS_PIDR4
Definition: arm_coresight.h:23
ARM_CS_ALIGN
#define ARM_CS_ALIGN
Definition: arm_coresight.h:16
ARM_CS_C9_DEVTYPE_MAJOR_SHIFT
#define ARM_CS_C9_DEVTYPE_MAJOR_SHIFT
Definition: arm_coresight.h:83
ARM_CS_C9_DEVTYPE
#define ARM_CS_C9_DEVTYPE
Definition: arm_coresight.h:80
ARM_CS_C9_DEVTYPE_MAJOR_MASK
#define ARM_CS_C9_DEVTYPE_MAJOR_MASK
Definition: arm_coresight.h:82
ARM_CS_C1_MEMTYPE_SYSMEM_MASK
#define ARM_CS_C1_MEMTYPE_SYSMEM_MASK
Definition: arm_coresight.h:93
ARM_CS_C9_DEVID_FORMAT_MASK
#define ARM_CS_C9_DEVID_FORMAT_MASK
Definition: arm_coresight.h:73
ARM_CS_ROMENTRY_OFFSET_MASK
#define ARM_CS_ROMENTRY_OFFSET_MASK
Definition: arm_coresight.h:98
ARM_CS_C9_DEVARCH_ARCHITECT
#define ARM_CS_C9_DEVARCH_ARCHITECT(devarch)
Definition: arm_coresight.h:68
ARM_CS_PIDR_JEDEC
#define ARM_CS_PIDR_JEDEC
Definition: arm_coresight.h:38
ARM_CS_PIDR_PART
#define ARM_CS_PIDR_PART(pidr)
Definition: arm_coresight.h:32
ARM_CS_CIDR0
#define ARM_CS_CIDR0
Definition: arm_coresight.h:41
ARM_CS_C9_DEVTYPE_SUB_MASK
#define ARM_CS_C9_DEVTYPE_SUB_MASK
Definition: arm_coresight.h:84
ARM_CS_C9_DEVID_FORMAT_64BIT
#define ARM_CS_C9_DEVID_FORMAT_64BIT
Definition: arm_coresight.h:75
ARM_CS_CIDR2
#define ARM_CS_CIDR2
Definition: arm_coresight.h:43
ARM_CS_PIDR1
#define ARM_CS_PIDR1
Definition: arm_coresight.h:20
ARM_CS_C9_DEVARCH_PRESENT
#define ARM_CS_C9_DEVARCH_PRESENT
Definition: arm_coresight.h:63
ARM_CS_PIDR_DESIGNER
#define ARM_CS_PIDR_DESIGNER(pidr)
Definition: arm_coresight.h:33
mode
enum arm_mode mode
Definition: armv4_5.c:281
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:375
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
CALL_COMMAND_HANDLER
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:118
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:400
CMD_DATA
#define CMD_DATA
Use this macro to access the invoked command handler's data pointer, rather than accessing the variab...
Definition: command.h:176
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:440
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:251
ERROR_COMMAND_ARGUMENT_INVALID
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:402
COMMAND_CONFIG
@ COMMAND_CONFIG
Definition: command.h:41
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
buffer
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
size
uint32_t size
Size of dw_spi_transaction::buffer.
Definition: dw-spi-helper.h:4
address
uint32_t address
Starting address. Sector aligned.
Definition: dw-spi-helper.h:0
width
unsigned short width
Definition: embeddedice.c:47
priv
static struct esp_usb_jtag * priv
Definition: esp_usb_jtag.c:219
jep106_manufacturer
static const char * jep106_manufacturer(unsigned int manufacturer)
Definition: jep106.h:21
jim_getopt_wide
int jim_getopt_wide(struct jim_getopt_info *goi, jim_wide *puthere)
Remove argv[0] as wide.
Definition: jim-nvp.c:222
jim_nvp_name2value_obj
int jim_nvp_name2value_obj(Jim_Interp *interp, const struct jim_nvp *p, Jim_Obj *o, struct jim_nvp **result)
Definition: jim-nvp.c:66
jim_getopt_obj
int jim_getopt_obj(struct jim_getopt_info *goi, Jim_Obj **puthere)
Remove argv[0] from the list.
Definition: jim-nvp.c:169
LOG_WARNING
#define LOG_WARNING(expr ...)
Definition: log.h:130
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:174
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:133
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:110
ERROR_OK
#define ERROR_OK
Definition: log.h:168
MIN
#define MIN(a, b)
Definition: replacements.h:22
MAX
#define MAX(a, b)
Definition: replacements.h:25
addr
target_addr_t addr
Start address to search for the control block.
Definition: rtt/rtt.c:28
BIT
#define BIT(nr)
Definition: stm32l4x.h:18
adiv5_ap
This represents an ARM Debug Interface (v5) Access Port (AP).
Definition: arm_adi_v5.h:250
adiv5_ap::csw_size_supported_mask
uint32_t csw_size_supported_mask
Save the supported CSW.Size data types for the MEM-AP.
Definition: arm_adi_v5.h:286
adiv5_ap::unaligned_access_bad
bool unaligned_access_bad
Definition: arm_adi_v5.h:316
adiv5_ap::config_ap_never_release
bool config_ap_never_release
Definition: arm_adi_v5.h:328
adiv5_ap::packed_transfers_probed
bool packed_transfers_probed
Definition: arm_adi_v5.h:313
adiv5_ap::tar_valid
bool tar_valid
Definition: arm_adi_v5.h:319
adiv5_ap::packed_transfers_supported
bool packed_transfers_supported
Definition: arm_adi_v5.h:312
adiv5_ap::tar_autoincr_block
uint32_t tar_autoincr_block
Definition: arm_adi_v5.h:309
adiv5_ap::refcount
unsigned int refcount
Definition: arm_adi_v5.h:325
adiv5_ap::csw_size_probed_mask
uint32_t csw_size_probed_mask
Probed CSW.Size data types for the MEM-AP.
Definition: arm_adi_v5.h:293
adiv5_ap::ap_num
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
Definition: arm_adi_v5.h:261
adiv5_ap::dap
struct adiv5_dap * dap
DAP this AP belongs to.
Definition: arm_adi_v5.h:254
adiv5_ap::memaccess_tck
uint32_t memaccess_tck
Configures how many extra tck clocks are added after starting a MEM-AP access before we try to read i...
Definition: arm_adi_v5.h:306
adiv5_ap::cfg_reg
uint32_t cfg_reg
Definition: arm_adi_v5.h:322
adiv5_ap::csw_default
uint32_t csw_default
Default value for (MEM-AP) AP_REG_CSW register.
Definition: arm_adi_v5.h:266
adiv5_ap::tar_value
target_addr_t tar_value
Cache for (MEM-AP) AP_REG_TAR register value This is written to configure the address being read or w...
Definition: arm_adi_v5.h:300
adiv5_ap::csw_value
uint32_t csw_value
Cache for (MEM-AP) AP_REG_CSW register value.
Definition: arm_adi_v5.h:273
adiv5_dap
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
Definition: arm_adi_v5.h:348
adiv5_dap::ti_be_32_quirks
bool ti_be_32_quirks
Definition: arm_adi_v5.h:398
adiv5_dap::select_valid
bool select_valid
Validity of DP SELECT cache.
Definition: arm_adi_v5.h:372
adiv5_dap::select1_valid
bool select1_valid
Definition: arm_adi_v5.h:373
adiv5_dap::ap
struct adiv5_ap ap[DP_APSEL_MAX+1]
Definition: arm_adi_v5.h:364
adiv5_dap::select_dpbanksel_valid
bool select_dpbanksel_valid
Partial DPBANKSEL validity for SWD only.
Definition: arm_adi_v5.h:383
adiv5_dap::dp_ctrl_stat
uint32_t dp_ctrl_stat
Definition: arm_adi_v5.h:362
adiv5_dap::do_reconnect
bool do_reconnect
Signals that an attempt to reestablish communication afresh should be performed before the next acces...
Definition: arm_adi_v5.h:414
adiv5_dap::ops
const struct dap_ops * ops
Definition: arm_adi_v5.h:349
adiv5_dap::last_read
uint32_t * last_read
Holds the pointer to the destination word for the last queued read, for use with posted AP read seque...
Definition: arm_adi_v5.h:392
adiv5_dap::apsel
uint64_t apsel
Definition: arm_adi_v5.h:367
adiv5_dap::tap
struct jtag_tap * tap
Definition: arm_adi_v5.h:360
adiv5_dap::select
uint64_t select
Cache for DP SELECT and SELECT1 (ADIv6) register.
Definition: arm_adi_v5.h:370
adiv5_dap::asize
unsigned int asize
Definition: arm_adi_v5.h:436
adiv5_dap::ignore_syspwrupack
bool ignore_syspwrupack
Flag saying whether to ignore the syspwrupack flag in DAP.
Definition: arm_adi_v5.h:418
adiv5_dap::nu_npcx_quirks
bool nu_npcx_quirks
Definition: arm_adi_v5.h:402
adiv5_mem_ap_spot
Definition: arm_adi_v5.h:802
adiv5_mem_ap_spot::dap
struct adiv5_dap * dap
Definition: arm_adi_v5.h:803
adiv5_mem_ap_spot::ap_num
uint64_t ap_num
Definition: arm_adi_v5.h:804
adiv5_mem_ap_spot::base
uint32_t base
Definition: arm_adi_v5.h:805
adiv5_private_config
Definition: arm_adi_v5.h:785
adiv5_private_config::ap_num
uint64_t ap_num
Definition: arm_adi_v5.h:786
adiv5_private_config::dap
struct adiv5_dap * dap
Definition: arm_adi_v5.h:787
command_invocation
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
command_registration
Definition: command.h:233
command_registration::name
const char * name
Definition: command.h:234
cs_component_vals
Holds registers and coordinates of a CoreSight component.
Definition: arm_adi_v5.c:1312
cs_component_vals::ap
struct adiv5_ap * ap
Definition: arm_adi_v5.c:1313
cs_component_vals::mode
enum coresight_access_mode mode
Definition: arm_adi_v5.c:1320
cs_component_vals::cid
uint32_t cid
Definition: arm_adi_v5.c:1316
cs_component_vals::component_base
target_addr_t component_base
Definition: arm_adi_v5.c:1314
cs_component_vals::devtype_memtype
uint32_t devtype_memtype
Definition: arm_adi_v5.c:1319
cs_component_vals::devarch
uint32_t devarch
Definition: arm_adi_v5.c:1317
cs_component_vals::devid
uint32_t devid
Definition: arm_adi_v5.c:1318
cs_component_vals::pid
uint64_t pid
Definition: arm_adi_v5.c:1315
dap_lookup_data
Definition: arm_adi_v5.c:2256
dap_lookup_data::type
unsigned int type
Definition: arm_adi_v5.c:2259
dap_lookup_data::component_base
uint64_t component_base
Definition: arm_adi_v5.c:2261
dap_lookup_data::ap_num
uint64_t ap_num
Definition: arm_adi_v5.c:2262
dap_lookup_data::idx
unsigned int idx
Definition: arm_adi_v5.c:2258
dap_ops::connect
int(* connect)(struct adiv5_dap *dap)
connect operation for SWD
Definition: arm_adi_v5.h:451
dap_part_nums
Definition: arm_adi_v5.c:1434
dap_part_nums::part_num
uint16_t part_num
Definition: arm_adi_v5.c:1436
dap_part_nums::type
const char * type
Definition: arm_adi_v5.c:1437
dap_part_nums::designer_id
uint16_t designer_id
Definition: arm_adi_v5.c:1435
dap_part_nums::full
const char * full
Definition: arm_adi_v5.c:1438
jim_getopt_info
A TCL -ish GetOpt like code.
Definition: jim-nvp.h:136
jim_getopt_info::interp
Jim_Interp * interp
Definition: jim-nvp.h:137
jim_getopt_info::is_configure
bool is_configure
Definition: jim-nvp.h:140
jim_getopt_info::argc
int argc
Definition: jim-nvp.h:138
jim_getopt_info::argv
Jim_Obj *const * argv
Definition: jim-nvp.h:139
jim_nvp
Name Value Pairs, aka: NVP.
Definition: jim-nvp.h:60
jim_nvp::name
const char * name
Definition: jim-nvp.h:61
jim_nvp::value
int value
Definition: jim-nvp.h:62
reg
Definition: register.h:111
rtp_ops
Actions/operations to be executed while parsing ROM tables.
Definition: arm_adi_v5.c:1738
rtp_ops::priv
void * priv
Private data.
Definition: arm_adi_v5.c:1784
rtp_ops::mem_ap_header
int(* mem_ap_header)(int retval, struct adiv5_ap *ap, uint64_t dbgbase, uint32_t apid, int depth, void *priv)
Executed at the start of a new MEM-AP, typically to print the MEM-AP header.
Definition: arm_adi_v5.c:1757
rtp_ops::rom_table_entry
int(* rom_table_entry)(int retval, int depth, unsigned int offset, uint64_t romentry, void *priv)
Executed for each entry of a ROM table, typically to print the entry and information about validity o...
Definition: arm_adi_v5.c:1779
rtp_ops::cs_component
int(* cs_component)(int retval, struct cs_component_vals *v, int depth, void *priv)
Executed when a CoreSight component is parsed, typically to print information on the component.
Definition: arm_adi_v5.c:1768
rtp_ops::ap_header
int(* ap_header)(struct adiv5_ap *ap, int depth, void *priv)
Executed at the start of a new AP, typically to print the AP header.
Definition: arm_adi_v5.c:1746
target
Definition: target.h:119
target::tap
struct jtag_tap * tap
Definition: target.h:122
target::private_config
void * private_config
Definition: target.h:168
target::dap_configured
bool dap_configured
Definition: target.h:182
target::has_dap
bool has_dap
Definition: target.h:181
target::tap_configured
bool tap_configured
Definition: target.h:183
true
#define true
Definition: system.h:66
ERROR_TARGET_SIZE_NOT_SUPPORTED
#define ERROR_TARGET_SIZE_NOT_SUPPORTED
Definition: target.h:796
ERROR_TARGET_UNALIGNED_ACCESS
#define ERROR_TARGET_UNALIGNED_ACCESS
Definition: target.h:788
ERROR_TARGET_PACKING_NOT_SUPPORTED
#define ERROR_TARGET_PACKING_NOT_SUPPORTED
Definition: target.h:797
ERROR_TARGET_RESOURCE_NOT_AVAILABLE
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:790
time_support.h
TARGET_ADDR_FMT
#define TARGET_ADDR_FMT
Definition: types.h:342
ARRAY_SIZE
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
DIV_ROUND_UP
#define DIV_ROUND_UP(m, n)
Rounds m up to the nearest multiple of n using division.
Definition: types.h:79
target_addr_t
uint64_t target_addr_t
Definition: types.h:335
low
static struct ublast_lowlevel low
Definition: ublast2_access_libusb.c:268
NULL
#define NULL
Definition: usb.h:16
cmd
uint8_t cmd
Definition: vdebug.c:1
offset
uint8_t offset[4]
Definition: vdebug.c:9
count
uint8_t count[4]
Definition: vdebug.c:22