OpenOCD
dsp563xx.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2009-2011 by Mathias Kuester *
5  * mkdorg@users.sourceforge.net *
6  ***************************************************************************/
7 
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11 
12 #include <jim.h>
13 
14 #include "target.h"
15 #include "breakpoints.h"
16 #include "target_type.h"
17 #include "algorithm.h"
18 #include "register.h"
19 #include "dsp563xx.h"
20 #include "dsp563xx_once.h"
21 
22 #define ASM_REG_W_R0 0x60F400
23 #define ASM_REG_W_R1 0x61F400
24 #define ASM_REG_W_R2 0x62F400
25 #define ASM_REG_W_R3 0x63F400
26 #define ASM_REG_W_R4 0x64F400
27 #define ASM_REG_W_R5 0x65F400
28 #define ASM_REG_W_R6 0x66F400
29 #define ASM_REG_W_R7 0x67F400
30 
31 #define ASM_REG_W_N0 0x70F400
32 #define ASM_REG_W_N1 0x71F400
33 #define ASM_REG_W_N2 0x72F400
34 #define ASM_REG_W_N3 0x73F400
35 #define ASM_REG_W_N4 0x74F400
36 #define ASM_REG_W_N5 0x75F400
37 #define ASM_REG_W_N6 0x76F400
38 #define ASM_REG_W_N7 0x77F400
39 
40 #define ASM_REG_W_M0 0x05F420
41 #define ASM_REG_W_M1 0x05F421
42 #define ASM_REG_W_M2 0x05F422
43 #define ASM_REG_W_M3 0x05F423
44 #define ASM_REG_W_M4 0x05F424
45 #define ASM_REG_W_M5 0x05F425
46 #define ASM_REG_W_M6 0x05F426
47 #define ASM_REG_W_M7 0x05F427
48 
49 #define ASM_REG_W_X0 0x44F400
50 #define ASM_REG_W_X1 0x45F400
51 
52 #define ASM_REG_W_Y0 0x46F400
53 #define ASM_REG_W_Y1 0x47F400
54 
55 #define ASM_REG_W_A0 0x50F400
56 #define ASM_REG_W_A1 0x54F400
57 #define ASM_REG_W_A2 0x52F400
58 
59 #define ASM_REG_W_B0 0x51F400
60 #define ASM_REG_W_B1 0x55F400
61 #define ASM_REG_W_B2 0x53F400
62 
63 #define ASM_REG_W_VBA 0x05F430
64 #define ASM_REG_W_OMR 0x05F43A
65 #define ASM_REG_W_EP 0x05F42A
66 #define ASM_REG_W_SC 0x05F431
67 #define ASM_REG_W_SZ 0x05F438
68 #define ASM_REG_W_SR 0x05F439
69 #define ASM_REG_W_SP 0x05F43B
70 #define ASM_REG_W_SSH 0x05F43C
71 #define ASM_REG_W_SSL 0x05F43D
72 #define ASM_REG_W_LA 0x05F43E
73 #define ASM_REG_W_LC 0x05F43F
74 #define ASM_REG_W_PC 0x000000
75 #define ASM_REG_W_IPRC 0xFFFFFF
76 #define ASM_REG_W_IPRP 0xFFFFFE
77 
78 #define ASM_REG_W_BCR 0xFFFFFB
79 #define ASM_REG_W_DCR 0xFFFFFA
80 #define ASM_REG_W_AAR0 0xFFFFF9
81 #define ASM_REG_W_AAR1 0xFFFFF8
82 #define ASM_REG_W_AAR2 0xFFFFF7
83 #define ASM_REG_W_AAR3 0xFFFFF6
84 
85 /*
86  * OBCR Register bit definitions
87  */
88 #define OBCR_B0_AND_B1 ((0x0) << 10)
89 #define OBCR_B0_OR_B1 ((0x1) << 10)
90 #define OBCR_B1_AFTER_B0 ((0x2) << 10)
91 #define OBCR_B0_AFTER_B1 ((0x3) << 10)
92 
93 #define OBCR_BP_DISABLED (0x0)
94 #define OBCR_BP_MEM_P (0x1)
95 #define OBCR_BP_MEM_X (0x2)
96 #define OBCR_BP_MEM_Y (0x3)
97 #define OBCR_BP_ON_READ ((0x2) << 0)
98 #define OBCR_BP_ON_WRITE ((0x1) << 0)
99 #define OBCR_BP_CC_NOT_EQUAL ((0x0) << 2)
100 #define OBCR_BP_CC_EQUAL ((0x1) << 2)
101 #define OBCR_BP_CC_LESS_THAN ((0x2) << 2)
102 #define OBCR_BP_CC_GREATER_THAN ((0x3) << 2)
103 
104 #define OBCR_BP_0(x) ((x)<<2)
105 #define OBCR_BP_1(x) ((x)<<6)
106 
107 
108 enum once_reg_idx {
109  ONCE_REG_IDX_OSCR = 0,
110  ONCE_REG_IDX_OMBC = 1,
111  ONCE_REG_IDX_OBCR = 2,
112  ONCE_REG_IDX_OMLR0 = 3,
113  ONCE_REG_IDX_OMLR1 = 4,
114  ONCE_REG_IDX_OGDBR = 5,
115  ONCE_REG_IDX_OPDBR = 6,
116  ONCE_REG_IDX_OPILR = 7,
117  ONCE_REG_IDX_PDB = 8,
118  ONCE_REG_IDX_OTC = 9,
119  ONCE_REG_IDX_OPABFR = 10,
120  ONCE_REG_IDX_OPABDR = 11,
121  ONCE_REG_IDX_OPABEX = 12,
122  ONCE_REG_IDX_OPABF0 = 13,
123  ONCE_REG_IDX_OPABF1 = 14,
124  ONCE_REG_IDX_OPABF2 = 15,
125  ONCE_REG_IDX_OPABF3 = 16,
126  ONCE_REG_IDX_OPABF4 = 17,
127  ONCE_REG_IDX_OPABF5 = 18,
128  ONCE_REG_IDX_OPABF6 = 19,
129  ONCE_REG_IDX_OPABF7 = 20,
130  ONCE_REG_IDX_OPABF8 = 21,
131  ONCE_REG_IDX_OPABF9 = 22,
132  ONCE_REG_IDX_OPABF10 = 23,
133  ONCE_REG_IDX_OPABF11 = 24,
134 };
135 
136 static struct once_reg once_regs[] = {
137  {ONCE_REG_IDX_OSCR, DSP563XX_ONCE_OSCR, 24, "OSCR", 0},
138  {ONCE_REG_IDX_OMBC, DSP563XX_ONCE_OMBC, 24, "OMBC", 0},
139  {ONCE_REG_IDX_OBCR, DSP563XX_ONCE_OBCR, 24, "OBCR", 0},
140  {ONCE_REG_IDX_OMLR0, DSP563XX_ONCE_OMLR0, 24, "OMLR0", 0},
141  {ONCE_REG_IDX_OMLR1, DSP563XX_ONCE_OMLR1, 24, "OMLR1", 0},
142  {ONCE_REG_IDX_OGDBR, DSP563XX_ONCE_OGDBR, 24, "OGDBR", 0},
143  {ONCE_REG_IDX_OPDBR, DSP563XX_ONCE_OPDBR, 24, "OPDBR", 0},
144  {ONCE_REG_IDX_OPILR, DSP563XX_ONCE_OPILR, 24, "OPILR", 0},
145  {ONCE_REG_IDX_PDB, DSP563XX_ONCE_PDBGOTO, 24, "PDB", 0},
146  {ONCE_REG_IDX_OTC, DSP563XX_ONCE_OTC, 24, "OTC", 0},
147  {ONCE_REG_IDX_OPABFR, DSP563XX_ONCE_OPABFR, 24, "OPABFR", 0},
148  {ONCE_REG_IDX_OPABDR, DSP563XX_ONCE_OPABDR, 24, "OPABDR", 0},
149  {ONCE_REG_IDX_OPABEX, DSP563XX_ONCE_OPABEX, 24, "OPABEX", 0},
150  {ONCE_REG_IDX_OPABF0, DSP563XX_ONCE_OPABF11, 25, "OPABF0", 0},
151  {ONCE_REG_IDX_OPABF1, DSP563XX_ONCE_OPABF11, 25, "OPABF1", 0},
152  {ONCE_REG_IDX_OPABF2, DSP563XX_ONCE_OPABF11, 25, "OPABF2", 0},
153  {ONCE_REG_IDX_OPABF3, DSP563XX_ONCE_OPABF11, 25, "OPABF3", 0},
154  {ONCE_REG_IDX_OPABF4, DSP563XX_ONCE_OPABF11, 25, "OPABF4", 0},
155  {ONCE_REG_IDX_OPABF5, DSP563XX_ONCE_OPABF11, 25, "OPABF5", 0},
156  {ONCE_REG_IDX_OPABF6, DSP563XX_ONCE_OPABF11, 25, "OPABF6", 0},
157  {ONCE_REG_IDX_OPABF7, DSP563XX_ONCE_OPABF11, 25, "OPABF7", 0},
158  {ONCE_REG_IDX_OPABF8, DSP563XX_ONCE_OPABF11, 25, "OPABF8", 0},
159  {ONCE_REG_IDX_OPABF9, DSP563XX_ONCE_OPABF11, 25, "OPABF9", 0},
160  {ONCE_REG_IDX_OPABF10, DSP563XX_ONCE_OPABF11, 25, "OPABF10", 0},
161  {ONCE_REG_IDX_OPABF11, DSP563XX_ONCE_OPABF11, 25, "OPABF11", 0},
162 /* {25,0x1f,24,"NRSEL",0}, */
163 };
164 
165 enum dsp563xx_reg_idx {
166  DSP563XX_REG_IDX_R0 = 0,
167  DSP563XX_REG_IDX_R1 = 1,
168  DSP563XX_REG_IDX_R2 = 2,
169  DSP563XX_REG_IDX_R3 = 3,
170  DSP563XX_REG_IDX_R4 = 4,
171  DSP563XX_REG_IDX_R5 = 5,
172  DSP563XX_REG_IDX_R6 = 6,
173  DSP563XX_REG_IDX_R7 = 7,
174  DSP563XX_REG_IDX_N0 = 8,
175  DSP563XX_REG_IDX_N1 = 9,
176  DSP563XX_REG_IDX_N2 = 10,
177  DSP563XX_REG_IDX_N3 = 11,
178  DSP563XX_REG_IDX_N4 = 12,
179  DSP563XX_REG_IDX_N5 = 13,
180  DSP563XX_REG_IDX_N6 = 14,
181  DSP563XX_REG_IDX_N7 = 15,
182  DSP563XX_REG_IDX_M0 = 16,
183  DSP563XX_REG_IDX_M1 = 17,
184  DSP563XX_REG_IDX_M2 = 18,
185  DSP563XX_REG_IDX_M3 = 19,
186  DSP563XX_REG_IDX_M4 = 20,
187  DSP563XX_REG_IDX_M5 = 21,
188  DSP563XX_REG_IDX_M6 = 22,
189  DSP563XX_REG_IDX_M7 = 23,
190  DSP563XX_REG_IDX_X0 = 24,
191  DSP563XX_REG_IDX_X1 = 25,
192  DSP563XX_REG_IDX_Y0 = 26,
193  DSP563XX_REG_IDX_Y1 = 27,
194  DSP563XX_REG_IDX_A0 = 28,
195  DSP563XX_REG_IDX_A1 = 29,
196  DSP563XX_REG_IDX_A2 = 30,
197  DSP563XX_REG_IDX_B0 = 31,
198  DSP563XX_REG_IDX_B1 = 32,
199  DSP563XX_REG_IDX_B2 = 33,
200  DSP563XX_REG_IDX_SSH = 34,
201  DSP563XX_REG_IDX_SSL = 35,
202  DSP563XX_REG_IDX_SP = 36,
203  DSP563XX_REG_IDX_EP = 37,
204  DSP563XX_REG_IDX_SZ = 38,
205  DSP563XX_REG_IDX_SC = 39,
206  DSP563XX_REG_IDX_PC = 40,
207  DSP563XX_REG_IDX_SR = 41,
208  DSP563XX_REG_IDX_OMR = 42,
209  DSP563XX_REG_IDX_LA = 43,
210  DSP563XX_REG_IDX_LC = 44,
211  DSP563XX_REG_IDX_VBA = 45,
212  DSP563XX_REG_IDX_IPRC = 46,
213  DSP563XX_REG_IDX_IPRP = 47,
214  DSP563XX_REG_IDX_BCR = 48,
215  DSP563XX_REG_IDX_DCR = 49,
216  DSP563XX_REG_IDX_AAR0 = 50,
217  DSP563XX_REG_IDX_AAR1 = 51,
218  DSP563XX_REG_IDX_AAR2 = 52,
219  DSP563XX_REG_IDX_AAR3 = 53,
220 };
221 
222 static const struct {
223  unsigned int id;
224  const char *name;
225  unsigned int bits;
226  /* effective addressing mode encoding */
227  uint8_t eame;
228  uint32_t instr_mask;
229 } dsp563xx_regs[] = {
230  /* *INDENT-OFF* */
231  /* address registers */
232  {DSP563XX_REG_IDX_R0, "r0", 24, 0x10, ASM_REG_W_R0},
233  {DSP563XX_REG_IDX_R1, "r1", 24, 0x11, ASM_REG_W_R1},
234  {DSP563XX_REG_IDX_R2, "r2", 24, 0x12, ASM_REG_W_R2},
235  {DSP563XX_REG_IDX_R3, "r3", 24, 0x13, ASM_REG_W_R3},
236  {DSP563XX_REG_IDX_R4, "r4", 24, 0x14, ASM_REG_W_R4},
237  {DSP563XX_REG_IDX_R5, "r5", 24, 0x15, ASM_REG_W_R5},
238  {DSP563XX_REG_IDX_R6, "r6", 24, 0x16, ASM_REG_W_R6},
239  {DSP563XX_REG_IDX_R7, "r7", 24, 0x17, ASM_REG_W_R7},
240  /* offset registers */
241  {DSP563XX_REG_IDX_N0, "n0", 24, 0x18, ASM_REG_W_N0},
242  {DSP563XX_REG_IDX_N1, "n1", 24, 0x19, ASM_REG_W_N1},
243  {DSP563XX_REG_IDX_N2, "n2", 24, 0x1a, ASM_REG_W_N2},
244  {DSP563XX_REG_IDX_N3, "n3", 24, 0x1b, ASM_REG_W_N3},
245  {DSP563XX_REG_IDX_N4, "n4", 24, 0x1c, ASM_REG_W_N4},
246  {DSP563XX_REG_IDX_N5, "n5", 24, 0x1d, ASM_REG_W_N5},
247  {DSP563XX_REG_IDX_N6, "n6", 24, 0x1e, ASM_REG_W_N6},
248  {DSP563XX_REG_IDX_N7, "n7", 24, 0x1f, ASM_REG_W_N7},
249  /* modifier registers */
250  {DSP563XX_REG_IDX_M0, "m0", 24, 0x20, ASM_REG_W_M0},
251  {DSP563XX_REG_IDX_M1, "m1", 24, 0x21, ASM_REG_W_M1},
252  {DSP563XX_REG_IDX_M2, "m2", 24, 0x22, ASM_REG_W_M2},
253  {DSP563XX_REG_IDX_M3, "m3", 24, 0x23, ASM_REG_W_M3},
254  {DSP563XX_REG_IDX_M4, "m4", 24, 0x24, ASM_REG_W_M4},
255  {DSP563XX_REG_IDX_M5, "m5", 24, 0x25, ASM_REG_W_M5},
256  {DSP563XX_REG_IDX_M6, "m6", 24, 0x26, ASM_REG_W_M6},
257  {DSP563XX_REG_IDX_M7, "m7", 24, 0x27, ASM_REG_W_M7},
258  /* data alu input register */
259  {DSP563XX_REG_IDX_X0, "x0", 24, 0x04, ASM_REG_W_X0},
260  {DSP563XX_REG_IDX_X1, "x1", 24, 0x05, ASM_REG_W_X1},
261  {DSP563XX_REG_IDX_Y0, "y0", 24, 0x06, ASM_REG_W_Y0},
262  {DSP563XX_REG_IDX_Y1, "y1", 24, 0x07, ASM_REG_W_Y1},
263  /* data alu accumulator register */
264  {DSP563XX_REG_IDX_A0, "a0", 24, 0x08, ASM_REG_W_A0},
265  {DSP563XX_REG_IDX_A1, "a1", 24, 0x0c, ASM_REG_W_A1},
266  {DSP563XX_REG_IDX_A2, "a2", 8, 0x0a, ASM_REG_W_A2},
267  {DSP563XX_REG_IDX_B0, "b0", 24, 0x09, ASM_REG_W_B0},
268  {DSP563XX_REG_IDX_B1, "b1", 24, 0x0d, ASM_REG_W_B1},
269  {DSP563XX_REG_IDX_B2, "b2", 8, 0x0b, ASM_REG_W_B2},
270  /* stack */
271  {DSP563XX_REG_IDX_SSH, "ssh", 24, 0x3c, ASM_REG_W_SSH},
272  {DSP563XX_REG_IDX_SSL, "ssl", 24, 0x3d, ASM_REG_W_SSL},
273  {DSP563XX_REG_IDX_SP, "sp", 24, 0x3b, ASM_REG_W_SP},
274  {DSP563XX_REG_IDX_EP, "ep", 24, 0x2a, ASM_REG_W_EP},
275  {DSP563XX_REG_IDX_SZ, "sz", 24, 0x38, ASM_REG_W_SZ},
276  {DSP563XX_REG_IDX_SC, "sc", 24, 0x31, ASM_REG_W_SC},
277  /* system */
278  {DSP563XX_REG_IDX_PC, "pc", 24, 0x00, ASM_REG_W_PC},
279  {DSP563XX_REG_IDX_SR, "sr", 24, 0x39, ASM_REG_W_SR},
280  {DSP563XX_REG_IDX_OMR, "omr", 24, 0x3a, ASM_REG_W_OMR},
281  {DSP563XX_REG_IDX_LA, "la", 24, 0x3e, ASM_REG_W_LA},
282  {DSP563XX_REG_IDX_LC, "lc", 24, 0x3f, ASM_REG_W_LC},
283  /* interrupt */
284  {DSP563XX_REG_IDX_VBA, "vba", 24, 0x30, ASM_REG_W_VBA},
285  {DSP563XX_REG_IDX_IPRC, "iprc", 24, 0x00, ASM_REG_W_IPRC},
286  {DSP563XX_REG_IDX_IPRP, "iprp", 24, 0x00, ASM_REG_W_IPRP},
287  /* port a */
288  {DSP563XX_REG_IDX_BCR, "bcr", 24, 0x00, ASM_REG_W_BCR},
289  {DSP563XX_REG_IDX_DCR, "dcr", 24, 0x00, ASM_REG_W_DCR},
290  {DSP563XX_REG_IDX_AAR0, "aar0", 24, 0x00, ASM_REG_W_AAR0},
291  {DSP563XX_REG_IDX_AAR1, "aar1", 24, 0x00, ASM_REG_W_AAR1},
292  {DSP563XX_REG_IDX_AAR2, "aar2", 24, 0x00, ASM_REG_W_AAR2},
293  {DSP563XX_REG_IDX_AAR3, "aar3", 24, 0x00, ASM_REG_W_AAR3},
294  /* *INDENT-ON* */
295 };
296 
297 enum memory_type {
298  MEM_X = 0,
299  MEM_Y = 1,
300  MEM_P = 2,
301  MEM_L = 3,
302 };
303 
304 enum watchpoint_condition {
305  EQUAL,
306  NOT_EQUAL,
307  GREATER,
308  LESS_THAN
309 };
310 
311 #define INSTR_JUMP 0x0AF080
312 /* Effective Addressing Mode Encoding */
313 #define EAME_R0 0x10
314 /* instruction encoder */
315 /* movep
316  * s - peripheral space X/Y (X=0,Y=1)
317  * w - write/read
318  * d - source/destination register
319  * p - IO short address
320  */
321 #define INSTR_MOVEP_REG_HIO(s, w, d, p) (0x084000 | \
322  ((s & 1) << 16) | ((w & 1) << 15) | ((d & 0x3f) << 8) | (p & 0x3f))
323 
324 /* the gdb register list is send in this order */
325 static const uint8_t gdb_reg_list_idx[] = {
326  DSP563XX_REG_IDX_X1, DSP563XX_REG_IDX_X0, DSP563XX_REG_IDX_Y1, DSP563XX_REG_IDX_Y0,
327  DSP563XX_REG_IDX_A2, DSP563XX_REG_IDX_A1, DSP563XX_REG_IDX_A0, DSP563XX_REG_IDX_B2,
328  DSP563XX_REG_IDX_B1, DSP563XX_REG_IDX_B0, DSP563XX_REG_IDX_PC, DSP563XX_REG_IDX_SR,
329  DSP563XX_REG_IDX_OMR, DSP563XX_REG_IDX_LA, DSP563XX_REG_IDX_LC, DSP563XX_REG_IDX_SSH,
330  DSP563XX_REG_IDX_SSL, DSP563XX_REG_IDX_SP, DSP563XX_REG_IDX_EP, DSP563XX_REG_IDX_SZ,
331  DSP563XX_REG_IDX_SC, DSP563XX_REG_IDX_VBA, DSP563XX_REG_IDX_IPRC, DSP563XX_REG_IDX_IPRP,
332  DSP563XX_REG_IDX_BCR, DSP563XX_REG_IDX_DCR, DSP563XX_REG_IDX_AAR0, DSP563XX_REG_IDX_AAR1,
333  DSP563XX_REG_IDX_AAR2, DSP563XX_REG_IDX_AAR3, DSP563XX_REG_IDX_R0, DSP563XX_REG_IDX_R1,
334  DSP563XX_REG_IDX_R2, DSP563XX_REG_IDX_R3, DSP563XX_REG_IDX_R4, DSP563XX_REG_IDX_R5,
335  DSP563XX_REG_IDX_R6, DSP563XX_REG_IDX_R7, DSP563XX_REG_IDX_N0, DSP563XX_REG_IDX_N1,
336  DSP563XX_REG_IDX_N2, DSP563XX_REG_IDX_N3, DSP563XX_REG_IDX_N4, DSP563XX_REG_IDX_N5,
337  DSP563XX_REG_IDX_N6, DSP563XX_REG_IDX_N7, DSP563XX_REG_IDX_M0, DSP563XX_REG_IDX_M1,
338  DSP563XX_REG_IDX_M2, DSP563XX_REG_IDX_M3, DSP563XX_REG_IDX_M4, DSP563XX_REG_IDX_M5,
339  DSP563XX_REG_IDX_M6, DSP563XX_REG_IDX_M7,
340 };
341 
342 static int dsp563xx_get_gdb_reg_list(struct target *target,
343  struct reg **reg_list[],
344  int *reg_list_size,
345  enum target_register_class reg_class)
346 {
347  int i;
348  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
349 
350  if (target->state != TARGET_HALTED)
351  return ERROR_TARGET_NOT_HALTED;
352 
353  *reg_list_size = DSP563XX_NUMCOREREGS;
354  *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
355 
356  if (!*reg_list)
357  return ERROR_COMMAND_SYNTAX_ERROR;
358 
359  for (i = 0; i < DSP563XX_NUMCOREREGS; i++)
360  (*reg_list)[i] = &dsp563xx->core_cache->reg_list[gdb_reg_list_idx[i]];
361 
362  return ERROR_OK;
363 
364 }
365 
366 static int dsp563xx_read_core_reg(struct target *target, int num)
367 {
368  uint32_t reg_value;
369  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
370 
371  if ((num < 0) || (num >= DSP563XX_NUMCOREREGS))
372  return ERROR_COMMAND_SYNTAX_ERROR;
373 
374  reg_value = dsp563xx->core_regs[num];
375  buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value);
376  dsp563xx->core_cache->reg_list[num].valid = true;
377  dsp563xx->core_cache->reg_list[num].dirty = false;
378 
379  return ERROR_OK;
380 }
381 
382 static int dsp563xx_write_core_reg(struct target *target, int num)
383 {
384  uint32_t reg_value;
385  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
386 
387  if ((num < 0) || (num >= DSP563XX_NUMCOREREGS))
388  return ERROR_COMMAND_SYNTAX_ERROR;
389 
390  reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32);
391  dsp563xx->core_regs[num] = reg_value;
392  dsp563xx->core_cache->reg_list[num].valid = true;
393  dsp563xx->core_cache->reg_list[num].dirty = false;
394 
395  return ERROR_OK;
396 }
397 
398 static int dsp563xx_get_core_reg(struct reg *reg)
399 {
400  struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
401  struct target *target = dsp563xx_reg->target;
402  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
403 
404  LOG_DEBUG("%s", __func__);
405 
406  if (target->state != TARGET_HALTED)
407  return ERROR_TARGET_NOT_HALTED;
408 
409  return dsp563xx->read_core_reg(target, dsp563xx_reg->num);
410 }
411 
412 static int dsp563xx_set_core_reg(struct reg *reg, uint8_t *buf)
413 {
414  LOG_DEBUG("%s", __func__);
415 
416  struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
417  struct target *target = dsp563xx_reg->target;
418  uint32_t value = buf_get_u32(buf, 0, 32);
419 
420  if (target->state != TARGET_HALTED)
421  return ERROR_TARGET_NOT_HALTED;
422 
423  buf_set_u32(reg->value, 0, reg->size, value);
424  reg->dirty = true;
425  reg->valid = true;
426 
427  return ERROR_OK;
428 }
429 
430 static const struct reg_arch_type dsp563xx_reg_type = {
431  .get = dsp563xx_get_core_reg,
432  .set = dsp563xx_set_core_reg,
433 };
434 
435 static void dsp563xx_build_reg_cache(struct target *target)
436 {
437  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
438 
439  struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
440  struct reg_cache *cache = malloc(sizeof(struct reg_cache));
441  struct reg *reg_list = calloc(DSP563XX_NUMCOREREGS, sizeof(struct reg));
442  struct dsp563xx_core_reg *arch_info = malloc(
443  sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS);
444  int i;
445 
446  /* Build the process context cache */
447  cache->name = "dsp563xx registers";
448  cache->next = NULL;
449  cache->reg_list = reg_list;
450  cache->num_regs = DSP563XX_NUMCOREREGS;
451  (*cache_p) = cache;
452  dsp563xx->core_cache = cache;
453 
454  for (i = 0; i < DSP563XX_NUMCOREREGS; i++) {
455  arch_info[i].num = dsp563xx_regs[i].id;
456  arch_info[i].name = dsp563xx_regs[i].name;
457  arch_info[i].size = dsp563xx_regs[i].bits;
458  arch_info[i].eame = dsp563xx_regs[i].eame;
459  arch_info[i].instr_mask = dsp563xx_regs[i].instr_mask;
460  arch_info[i].target = target;
461  arch_info[i].dsp563xx_common = dsp563xx;
462  reg_list[i].name = dsp563xx_regs[i].name;
463  reg_list[i].size = 32; /* dsp563xx_regs[i].bits; */
464  reg_list[i].value = calloc(1, 4);
465  reg_list[i].dirty = false;
466  reg_list[i].valid = false;
467  reg_list[i].exist = true;
468  reg_list[i].type = &dsp563xx_reg_type;
469  reg_list[i].arch_info = &arch_info[i];
470  }
471 }
472 
473 static int dsp563xx_read_register(struct target *target, int num, int force);
474 static int dsp563xx_write_register(struct target *target, int num, int force);
475 
476 static int dsp563xx_reg_read_high_io(struct target *target, uint32_t instr_mask, uint32_t *data)
477 {
478  int err;
479  uint32_t instr;
480  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
481 
482  /* we use r0 to store temporary data */
483  if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
484  dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0);
485 
486  /* move source memory to r0 */
487  instr = INSTR_MOVEP_REG_HIO(MEM_X, 0, EAME_R0, instr_mask);
488  err = dsp563xx_once_execute_sw_ir(target->tap, 0, instr);
489  if (err != ERROR_OK)
490  return err;
491  /* move r0 to debug register */
492  instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, EAME_R0, 0xfffffc);
493  err = dsp563xx_once_execute_sw_ir(target->tap, 1, instr);
494  if (err != ERROR_OK)
495  return err;
496  /* read debug register */
497  err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OGDBR, data);
498  if (err != ERROR_OK)
499  return err;
500  /* r0 is no longer valid on target */
501  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
502 
503  return ERROR_OK;
504 }
505 
506 static int dsp563xx_reg_write_high_io(struct target *target, uint32_t instr_mask, uint32_t data)
507 {
508  int err;
509  uint32_t instr;
510  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
511 
512  /* we use r0 to store temporary data */
513  if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
514  dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0);
515 
516  /* move data to r0 */
517  err = dsp563xx_once_execute_dw_ir(target->tap, 0, 0x60F400, data);
518  if (err != ERROR_OK)
519  return err;
520  /* move r0 to destination memory */
521  instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, EAME_R0, instr_mask);
522  err = dsp563xx_once_execute_sw_ir(target->tap, 1, instr);
523  if (err != ERROR_OK)
524  return err;
525 
526  /* r0 is no longer valid on target */
527  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
528 
529  return ERROR_OK;
530 }
531 
532 static int dsp563xx_reg_read(struct target *target, uint32_t eame, uint32_t *data)
533 {
534  int err;
535  uint32_t instr;
536 
537  instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, eame, 0xfffffc);
538  err = dsp563xx_once_execute_sw_ir(target->tap, 0, instr);
539  if (err != ERROR_OK)
540  return err;
541  /* nop */
542  err = dsp563xx_once_execute_sw_ir(target->tap, 1, 0x000000);
543  if (err != ERROR_OK)
544  return err;
545  /* read debug register */
546  return dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OGDBR, data);
547 }
548 
549 static int dsp563xx_reg_write(struct target *target, uint32_t instr_mask, uint32_t data)
550 {
551  int err;
552 
553  err = dsp563xx_once_execute_dw_ir(target->tap, 0, instr_mask, data);
554  if (err != ERROR_OK)
555  return err;
556  /* nop */
557  return dsp563xx_once_execute_sw_ir(target->tap, 1, 0x000000);
558 }
559 
560 static int dsp563xx_reg_pc_read(struct target *target)
561 {
562  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
563 
564  /* pc was changed, nothing todo */
565  if (dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty)
566  return ERROR_OK;
567 
568  /* conditional branch check */
569  if (once_regs[ONCE_REG_IDX_OPABDR].reg == once_regs[ONCE_REG_IDX_OPABEX].reg) {
570  if ((once_regs[ONCE_REG_IDX_OPABF11].reg & 1) == 0) {
571  LOG_DEBUG("%s conditional branch not supported yet (0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 ")",
572  __func__,
573  (once_regs[ONCE_REG_IDX_OPABF11].reg >> 1),
574  once_regs[ONCE_REG_IDX_OPABDR].reg,
575  once_regs[ONCE_REG_IDX_OPABEX].reg);
576 
577  /* TODO: use disassembly to set correct pc offset
578  * read 2 words from OPABF11 and disasm the instruction
579  */
580  dsp563xx->core_regs[DSP563XX_REG_IDX_PC] =
581  (once_regs[ONCE_REG_IDX_OPABF11].reg >> 1) & 0x00FFFFFF;
582  } else {
583  if (once_regs[ONCE_REG_IDX_OPABEX].reg ==
584  once_regs[ONCE_REG_IDX_OPABFR].reg)
585  dsp563xx->core_regs[DSP563XX_REG_IDX_PC] =
586  once_regs[ONCE_REG_IDX_OPABEX].reg;
587  else
588  dsp563xx->core_regs[DSP563XX_REG_IDX_PC] =
589  once_regs[ONCE_REG_IDX_OPABEX].reg - 1;
590  }
591  } else
592  dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = once_regs[ONCE_REG_IDX_OPABEX].reg;
593 
594  dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_PC);
595 
596  return ERROR_OK;
597 }
598 
599 static int dsp563xx_reg_ssh_read(struct target *target)
600 {
601  int err;
602  uint32_t sp;
603  struct dsp563xx_core_reg *arch_info;
604  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
605 
606  arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info;
607 
608  /* get a valid stack pointer */
609  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0);
610  if (err != ERROR_OK)
611  return err;
612  sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP];
613  err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 0);
614  if (err != ERROR_OK)
615  return err;
616 
617  /* get a valid stack count */
618  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SC, 0);
619  if (err != ERROR_OK)
620  return err;
621 
622  err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SC, 0);
623  if (err != ERROR_OK)
624  return err;
625 
626  /* get a valid extended pointer */
627  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_EP, 0);
628  if (err != ERROR_OK)
629  return err;
630 
631  err = dsp563xx_write_register(target, DSP563XX_REG_IDX_EP, 0);
632  if (err != ERROR_OK)
633  return err;
634 
635  if (!sp)
636  sp = 0x00FFFFFF;
637  else {
638  err = dsp563xx_reg_read(target, arch_info->eame, &sp);
639  if (err != ERROR_OK)
640  return err;
641 
642  err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SC, 1);
643  if (err != ERROR_OK)
644  return err;
645  err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 1);
646  if (err != ERROR_OK)
647  return err;
648  err = dsp563xx_write_register(target, DSP563XX_REG_IDX_EP, 1);
649  if (err != ERROR_OK)
650  return err;
651  }
652 
653  dsp563xx->core_regs[DSP563XX_REG_IDX_SSH] = sp;
654  dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_SSH);
655 
656  return ERROR_OK;
657 }
658 
659 static int dsp563xx_reg_ssh_write(struct target *target)
660 {
661  int err;
662  uint32_t sp;
663  struct dsp563xx_core_reg *arch_info;
664  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
665 
666  arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info;
667 
668  /* get a valid stack pointer */
669  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0);
670  if (err != ERROR_OK)
671  return err;
672  sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP];
673 
674  if (sp) {
675  sp--;
676  /* write new stackpointer */
677  dsp563xx->core_regs[DSP563XX_REG_IDX_SP] = sp;
678  err = dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_SP);
679  if (err != ERROR_OK)
680  return err;
681  err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 1);
682  if (err != ERROR_OK)
683  return err;
684 
685  err = dsp563xx_reg_write(target, arch_info->instr_mask,
686  dsp563xx->core_regs[DSP563XX_REG_IDX_SSH]);
687  if (err != ERROR_OK)
688  return err;
689 
690  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 1);
691  if (err != ERROR_OK)
692  return err;
693  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SSH, 1);
694  if (err != ERROR_OK)
695  return err;
696  }
697 
698  return ERROR_OK;
699 }
700 
701 static int dsp563xx_reg_ssl_read(struct target *target)
702 {
703  int err;
704  uint32_t sp;
705  struct dsp563xx_core_reg *arch_info;
706  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
707 
708  arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].arch_info;
709 
710  /* get a valid stack pointer */
711  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0);
712  if (err != ERROR_OK)
713  return err;
714  sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP];
715 
716  if (!sp)
717  sp = 0x00FFFFFF;
718  else {
719  err = dsp563xx_reg_read(target, arch_info->eame, &sp);
720  if (err != ERROR_OK)
721  return err;
722  }
723 
724  dsp563xx->core_regs[DSP563XX_REG_IDX_SSL] = sp;
725  dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_SSL);
726 
727  return ERROR_OK;
728 }
729 
730 static int dsp563xx_read_register(struct target *target, int num, int force)
731 {
732  int err = ERROR_OK;
733  uint32_t data = 0;
734  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
735  struct dsp563xx_core_reg *arch_info;
736 
737  if (force)
738  dsp563xx->core_cache->reg_list[num].valid = false;
739 
740  if (!dsp563xx->core_cache->reg_list[num].valid) {
741  arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
742 
743  switch (arch_info->num) {
744  case DSP563XX_REG_IDX_SSH:
745  err = dsp563xx_reg_ssh_read(target);
746  break;
747  case DSP563XX_REG_IDX_SSL:
748  err = dsp563xx_reg_ssl_read(target);
749  break;
750  case DSP563XX_REG_IDX_PC:
751  err = dsp563xx_reg_pc_read(target);
752  break;
753  case DSP563XX_REG_IDX_IPRC:
754  case DSP563XX_REG_IDX_IPRP:
755  case DSP563XX_REG_IDX_BCR:
756  case DSP563XX_REG_IDX_DCR:
757  case DSP563XX_REG_IDX_AAR0:
758  case DSP563XX_REG_IDX_AAR1:
759  case DSP563XX_REG_IDX_AAR2:
760  case DSP563XX_REG_IDX_AAR3:
761  err = dsp563xx_reg_read_high_io(target,
762  arch_info->instr_mask, &data);
763  if (err == ERROR_OK) {
764  dsp563xx->core_regs[num] = data;
765  dsp563xx->read_core_reg(target, num);
766  }
767  break;
768  default:
769  err = dsp563xx_reg_read(target, arch_info->eame, &data);
770  if (err == ERROR_OK) {
771  dsp563xx->core_regs[num] = data;
772  dsp563xx->read_core_reg(target, num);
773  }
774  break;
775  }
776  }
777 
778  return err;
779 }
780 
781 static int dsp563xx_write_register(struct target *target, int num, int force)
782 {
783  int err = ERROR_OK;
784  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
785  struct dsp563xx_core_reg *arch_info;
786 
787  if (force)
788  dsp563xx->core_cache->reg_list[num].dirty = true;
789 
790  if (dsp563xx->core_cache->reg_list[num].dirty) {
791  arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
792 
793  dsp563xx->write_core_reg(target, num);
794 
795  switch (arch_info->num) {
796  case DSP563XX_REG_IDX_SSH:
797  err = dsp563xx_reg_ssh_write(target);
798  break;
799  case DSP563XX_REG_IDX_PC:
800  /* pc is updated on resume, no need to write it here */
801  break;
802  case DSP563XX_REG_IDX_IPRC:
803  case DSP563XX_REG_IDX_IPRP:
804  case DSP563XX_REG_IDX_BCR:
805  case DSP563XX_REG_IDX_DCR:
806  case DSP563XX_REG_IDX_AAR0:
807  case DSP563XX_REG_IDX_AAR1:
808  case DSP563XX_REG_IDX_AAR2:
809  case DSP563XX_REG_IDX_AAR3:
810  err = dsp563xx_reg_write_high_io(target,
811  arch_info->instr_mask,
812  dsp563xx->core_regs[num]);
813  break;
814  default:
815  err = dsp563xx_reg_write(target,
816  arch_info->instr_mask,
817  dsp563xx->core_regs[num]);
818 
819  if (err == ERROR_OK && arch_info->num == DSP563XX_REG_IDX_SP) {
820  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].valid = 0;
821  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].valid = 0;
822  }
823  break;
824  }
825  }
826 
827  return err;
828 }
829 
830 static int dsp563xx_save_context(struct target *target)
831 {
832  int i, err = ERROR_OK;
833 
834  for (i = 0; i < DSP563XX_NUMCOREREGS; i++) {
835  err = dsp563xx_read_register(target, i, 0);
836  if (err != ERROR_OK)
837  break;
838  }
839 
840  return err;
841 }
842 
843 static int dsp563xx_restore_context(struct target *target)
844 {
845  int i, err = ERROR_OK;
846 
847  for (i = 0; i < DSP563XX_NUMCOREREGS; i++) {
848  err = dsp563xx_write_register(target, i, 0);
849  if (err != ERROR_OK)
850  break;
851  }
852 
853  return err;
854 }
855 
856 static void dsp563xx_invalidate_x_context(struct target *target,
857  uint32_t addr_start,
858  uint32_t addr_end)
859 {
860  int i;
861  struct dsp563xx_core_reg *arch_info;
862  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
863 
864  if (addr_start > ASM_REG_W_IPRC)
865  return;
866  if (addr_start < ASM_REG_W_AAR3)
867  return;
868 
869  for (i = DSP563XX_REG_IDX_IPRC; i < DSP563XX_NUMCOREREGS; i++) {
870  arch_info = dsp563xx->core_cache->reg_list[i].arch_info;
871 
872  if ((arch_info->instr_mask >= addr_start) &&
873  (arch_info->instr_mask <= addr_end)) {
874  dsp563xx->core_cache->reg_list[i].valid = false;
875  dsp563xx->core_cache->reg_list[i].dirty = false;
876  }
877  }
878 }
879 
880 static int dsp563xx_target_create(struct target *target)
881 {
882  struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common));
883 
884  if (!dsp563xx)
885  return ERROR_COMMAND_SYNTAX_ERROR;
886 
887  dsp563xx->jtag_info.tap = target->tap;
888  target->arch_info = dsp563xx;
889  dsp563xx->read_core_reg = dsp563xx_read_core_reg;
890  dsp563xx->write_core_reg = dsp563xx_write_core_reg;
891 
892  return ERROR_OK;
893 }
894 
895 static int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target)
896 {
897  LOG_DEBUG("%s", __func__);
898 
899  dsp563xx_build_reg_cache(target);
900  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
901 
902  dsp563xx->hardware_breakpoints_cleared = false;
903  dsp563xx->hardware_breakpoint[0].used = BPU_NONE;
904 
905  return ERROR_OK;
906 }
907 
908 static int dsp563xx_examine(struct target *target)
909 {
910  uint32_t chip;
911 
912  if (!target->tap->has_idcode) {
913  LOG_ERROR("no IDCODE present on device");
914  return ERROR_COMMAND_SYNTAX_ERROR;
915  }
916 
917  if (!target_was_examined(target)) {
918  /* examine core and chip derivate number */
919  chip = (target->tap->idcode>>12) & 0x3ff;
920  /* core number 0 means DSP563XX */
921  if (((chip>>5)&0x1f) == 0)
922  chip += 300;
923 
924  LOG_INFO("DSP56%03" PRIu32 " device found", chip);
925 
926  /* Clear all breakpoints */
927  dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, 0);
928  }
929 
930  return ERROR_OK;
931 }
932 
933 static int dsp563xx_arch_state(struct target *target)
934 {
935  LOG_DEBUG("%s", __func__);
936  return ERROR_OK;
937 }
938 
939 #define DSP563XX_SR_SA (1<<17)
940 #define DSP563XX_SR_SC (1<<13)
941 
942 static int dsp563xx_debug_once_init(struct target *target)
943 {
944  return dsp563xx_once_read_register(target->tap, 1, once_regs, DSP563XX_NUMONCEREGS);
945 }
946 
947 static int dsp563xx_debug_init(struct target *target)
948 {
949  int err;
950  uint32_t sr;
951  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
952  struct dsp563xx_core_reg *arch_info;
953 
954  err = dsp563xx_debug_once_init(target);
955  if (err != ERROR_OK)
956  return err;
957 
958  arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].arch_info;
959 
960  /* check 24bit mode */
961  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SR, 0);
962  if (err != ERROR_OK)
963  return err;
964 
965  sr = dsp563xx->core_regs[DSP563XX_REG_IDX_SR];
966 
967  if (sr & (DSP563XX_SR_SA | DSP563XX_SR_SC)) {
968  sr &= ~(DSP563XX_SR_SA | DSP563XX_SR_SC);
969 
970  err = dsp563xx_once_execute_dw_ir(target->tap, 1, arch_info->instr_mask, sr);
971  if (err != ERROR_OK)
972  return err;
973  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = true;
974  }
975 
976  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N0, 0);
977  if (err != ERROR_OK)
978  return err;
979  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N1, 0);
980  if (err != ERROR_OK)
981  return err;
982  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_M0, 0);
983  if (err != ERROR_OK)
984  return err;
985  err = dsp563xx_read_register(target, DSP563XX_REG_IDX_M1, 0);
986  if (err != ERROR_OK)
987  return err;
988 
989  if (dsp563xx->core_regs[DSP563XX_REG_IDX_N0] != 0x000000) {
990  arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].arch_info;
991  err = dsp563xx_reg_write(target, arch_info->instr_mask, 0x000000);
992  if (err != ERROR_OK)
993  return err;
994  }
995  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = true;
996 
997  if (dsp563xx->core_regs[DSP563XX_REG_IDX_N1] != 0x000000) {
998  arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].arch_info;
999  err = dsp563xx_reg_write(target, arch_info->instr_mask, 0x000000);
1000  if (err != ERROR_OK)
1001  return err;
1002  }
1003  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = true;
1004 
1005  if (dsp563xx->core_regs[DSP563XX_REG_IDX_M0] != 0xffffff) {
1006  arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].arch_info;
1007  err = dsp563xx_reg_write(target, arch_info->instr_mask, 0xffffff);
1008  if (err != ERROR_OK)
1009  return err;
1010  }
1011  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = true;
1012 
1013  if (dsp563xx->core_regs[DSP563XX_REG_IDX_M1] != 0xffffff) {
1014  arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].arch_info;
1015  err = dsp563xx_reg_write(target, arch_info->instr_mask, 0xffffff);
1016  if (err != ERROR_OK)
1017  return err;
1018  }
1019  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = true;
1020 
1021  err = dsp563xx_save_context(target);
1022  if (err != ERROR_OK)
1023  return err;
1024 
1025  return ERROR_OK;
1026 }
1027 
1028 static int dsp563xx_jtag_debug_request(struct target *target)
1029 {
1030  return dsp563xx_once_request_debug(target->tap, target->state == TARGET_RESET);
1031 }
1032 
1033 static int dsp563xx_poll(struct target *target)
1034 {
1035  int err;
1036  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1037  uint32_t once_status = 0;
1038  int state;
1039 
1040  state = dsp563xx_once_target_status(target->tap);
1041 
1042  if (state == TARGET_UNKNOWN) {
1043  target->state = state;
1044  LOG_ERROR("jtag status contains invalid mode value - communication failure");
1045  return ERROR_TARGET_FAILURE;
1046  }
1047 
1048  err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OSCR, &once_status);
1049  if (err != ERROR_OK)
1050  return err;
1051 
1052  if ((once_status & DSP563XX_ONCE_OSCR_DEBUG_M) == DSP563XX_ONCE_OSCR_DEBUG_M) {
1053  if (target->state != TARGET_HALTED) {
1054  target->state = TARGET_HALTED;
1055 
1056  err = dsp563xx_debug_init(target);
1057  if (err != ERROR_OK)
1058  return err;
1059 
1060  if (once_status & (DSP563XX_ONCE_OSCR_MBO|DSP563XX_ONCE_OSCR_SWO))
1061  target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
1062  else
1063  target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1064 
1065  LOG_DEBUG("target->state: %s (%" PRIx32 ")", target_state_name(target), once_status);
1066  LOG_INFO("halted: PC: 0x%" PRIx32, dsp563xx->core_regs[DSP563XX_REG_IDX_PC]);
1067  }
1068  }
1069 
1070  if (!dsp563xx->hardware_breakpoints_cleared) {
1071  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, 0);
1072  if (err != ERROR_OK)
1073  return err;
1074 
1075  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMLR0, 0);
1076  if (err != ERROR_OK)
1077  return err;
1078 
1079  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMLR1, 0);
1080  if (err != ERROR_OK)
1081  return err;
1082 
1083  dsp563xx->hardware_breakpoints_cleared = true;
1084  }
1085 
1086  return ERROR_OK;
1087 }
1088 
1089 static int dsp563xx_halt(struct target *target)
1090 {
1091  int err;
1092 
1093  LOG_DEBUG("%s", __func__);
1094 
1095  if (target->state == TARGET_HALTED) {
1096  LOG_DEBUG("target was already halted");
1097  return ERROR_OK;
1098  }
1099 
1100  if (target->state == TARGET_UNKNOWN)
1101  LOG_WARNING("target was in unknown state when halt was requested");
1102 
1103  err = dsp563xx_jtag_debug_request(target);
1104  if (err != ERROR_OK)
1105  return err;
1106 
1107  target->debug_reason = DBG_REASON_DBGRQ;
1108 
1109  return ERROR_OK;
1110 }
1111 
1112 static int dsp563xx_resume(struct target *target,
1113  bool current,
1114  target_addr_t address,
1115  bool handle_breakpoints,
1116  bool debug_execution)
1117 {
1118  int err;
1119  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1120 
1121  /* check if pc was changed and resume want to execute the next address
1122  * if pc was changed from gdb or other interface we will
1123  * jump to this address and don't execute the next address
1124  * this will not affect the resume command with an address argument
1125  * because current is set to zero then
1126  */
1127  if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) {
1128  dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC);
1129  address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC];
1130  current = false;
1131  }
1132 
1133  LOG_DEBUG("%s %08X %08" TARGET_PRIXADDR, __func__, current, address);
1134 
1135  err = dsp563xx_restore_context(target);
1136  if (err != ERROR_OK)
1137  return err;
1138  register_cache_invalidate(dsp563xx->core_cache);
1139 
1140  if (current) {
1141  /* restore pipeline registers and go */
1142  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR,
1143  once_regs[ONCE_REG_IDX_OPILR].reg);
1144  if (err != ERROR_OK)
1145  return err;
1146  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR |
1147  DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO,
1148  once_regs[ONCE_REG_IDX_OPDBR].reg);
1149  if (err != ERROR_OK)
1150  return err;
1151  } else {
1152  /* set to go register and jump */
1153  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, INSTR_JUMP);
1154  if (err != ERROR_OK)
1155  return err;
1156  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_PDBGOTO |
1157  DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, address);
1158  if (err != ERROR_OK)
1159  return err;
1160  }
1161 
1162  target->state = TARGET_RUNNING;
1163 
1164  target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1165 
1166  return ERROR_OK;
1167 }
1168 
1169 static int dsp563xx_step_ex(struct target *target,
1170  bool current,
1171  uint32_t address,
1172  bool handle_breakpoints,
1173  int steps)
1174 {
1175  int err;
1176  uint32_t once_status;
1177  uint32_t dr_in, cnt;
1178  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1179 
1180  if (target->state != TARGET_HALTED) {
1181  LOG_DEBUG("target was not halted");
1182  return ERROR_OK;
1183  }
1184 
1185  /* check if pc was changed and step want to execute the next address
1186  * if pc was changed from gdb or other interface we will
1187  * jump to this address and don't execute the next address
1188  * this will not affect the step command with an address argument
1189  * because current is set to zero then
1190  */
1191  if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) {
1192  dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC);
1193  address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC];
1194  current = false;
1195  }
1196 
1197  LOG_DEBUG("%s %08X %08" PRIX32, __func__, current, address);
1198 
1199  err = dsp563xx_jtag_debug_request(target);
1200  if (err != ERROR_OK)
1201  return err;
1202  err = dsp563xx_restore_context(target);
1203  if (err != ERROR_OK)
1204  return err;
1205 
1206  /* reset trace mode */
1207  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000);
1208  if (err != ERROR_OK)
1209  return err;
1210  /* enable trace mode */
1211  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, DSP563XX_ONCE_OSCR_TME);
1212  if (err != ERROR_OK)
1213  return err;
1214 
1215  cnt = steps;
1216 
1217  /* on JUMP we need one extra cycle */
1218  if (!current)
1219  cnt++;
1220 
1221  /* load step counter with N-1 */
1222  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OTC, cnt);
1223  if (err != ERROR_OK)
1224  return err;
1225 
1226  if (current) {
1227  /* restore pipeline registers and go */
1228  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR,
1229  once_regs[ONCE_REG_IDX_OPILR].reg);
1230  if (err != ERROR_OK)
1231  return err;
1232  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR |
1233  DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO,
1234  once_regs[ONCE_REG_IDX_OPDBR].reg);
1235  if (err != ERROR_OK)
1236  return err;
1237  } else {
1238  /* set to go register and jump */
1239  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, INSTR_JUMP);
1240  if (err != ERROR_OK)
1241  return err;
1242  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_PDBGOTO |
1243  DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO,
1244  address);
1245  if (err != ERROR_OK)
1246  return err;
1247  }
1248 
1249  while (1) {
1250  err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OSCR, &once_status);
1251  if (err != ERROR_OK)
1252  return err;
1253 
1254  if (once_status & DSP563XX_ONCE_OSCR_TO) {
1255  err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABFR, &dr_in);
1256  if (err != ERROR_OK)
1257  return err;
1258  LOG_DEBUG("fetch: %08" PRIX32, dr_in & 0x00ffffff);
1259  err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABDR, &dr_in);
1260  if (err != ERROR_OK)
1261  return err;
1262  LOG_DEBUG("decode: %08" PRIX32, dr_in & 0x00ffffff);
1263  err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABEX, &dr_in);
1264  if (err != ERROR_OK)
1265  return err;
1266  LOG_DEBUG("execute: %08" PRIX32, dr_in & 0x00ffffff);
1267 
1268  /* reset trace mode */
1269  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000);
1270  if (err != ERROR_OK)
1271  return err;
1272 
1273  register_cache_invalidate(dsp563xx->core_cache);
1274  err = dsp563xx_debug_init(target);
1275  if (err != ERROR_OK)
1276  return err;
1277 
1278  break;
1279  }
1280  }
1281 
1282  return ERROR_OK;
1283 }
1284 
1285 static int dsp563xx_step(struct target *target,
1286  bool current,
1287  target_addr_t address,
1288  bool handle_breakpoints)
1289 {
1290  int err;
1291  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1292 
1293  if (target->state != TARGET_HALTED) {
1294  LOG_TARGET_ERROR(target, "not halted");
1295  return ERROR_TARGET_NOT_HALTED;
1296  }
1297 
1298  err = dsp563xx_step_ex(target, current, address, handle_breakpoints, 0);
1299  if (err != ERROR_OK)
1300  return err;
1301 
1302  target->debug_reason = DBG_REASON_SINGLESTEP;
1303  target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1304 
1305  LOG_INFO("halted: PC: 0x%" PRIx32, dsp563xx->core_regs[DSP563XX_REG_IDX_PC]);
1306 
1307  return err;
1308 }
1309 
1310 static int dsp563xx_assert_reset(struct target *target)
1311 {
1312  int retval = 0;
1313  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1314  enum reset_types jtag_reset_config = jtag_get_reset_config();
1315 
1316  if (jtag_reset_config & RESET_HAS_SRST) {
1317  /* default to asserting srst */
1318  if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1319  jtag_add_reset(1, 1);
1320  else
1321  jtag_add_reset(0, 1);
1322  }
1323 
1324  target->state = TARGET_RESET;
1325  jtag_add_sleep(5000);
1326 
1327  /* registers are now invalid */
1328  register_cache_invalidate(dsp563xx->core_cache);
1329 
1330  if (target->reset_halt) {
1331  retval = target_halt(target);
1332  if (retval != ERROR_OK)
1333  return retval;
1334  }
1335 
1336  LOG_DEBUG("%s", __func__);
1337  return ERROR_OK;
1338 }
1339 
1340 static int dsp563xx_deassert_reset(struct target *target)
1341 {
1342  int err;
1343 
1344  /* deassert reset lines */
1345  jtag_add_reset(0, 0);
1346 
1347  err = dsp563xx_poll(target);
1348  if (err != ERROR_OK)
1349  return err;
1350 
1351  if (target->reset_halt) {
1352  if (target->state == TARGET_HALTED) {
1353  /* after a reset the cpu jmp to the
1354  * reset vector and need 2 cycles to fill
1355  * the cache (fetch,decode,execute)
1356  */
1357  err = dsp563xx_step_ex(target, true, 0, true, 1);
1358  if (err != ERROR_OK)
1359  return err;
1360  }
1361  } else
1362  target->state = TARGET_RUNNING;
1363 
1364  LOG_DEBUG("%s", __func__);
1365  return ERROR_OK;
1366 }
1367 
1368 static int dsp563xx_run_algorithm(struct target *target,
1369  int num_mem_params, struct mem_param *mem_params,
1370  int num_reg_params, struct reg_param *reg_params,
1371  target_addr_t entry_point, target_addr_t exit_point,
1372  unsigned int timeout_ms, void *arch_info)
1373 {
1374  int i;
1375  int retval = ERROR_OK;
1376  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1377 
1378  if (target->state != TARGET_HALTED) {
1379  LOG_TARGET_ERROR(target, "not halted (run target algo)");
1380  return ERROR_TARGET_NOT_HALTED;
1381  }
1382 
1383  for (i = 0; i < num_mem_params; i++) {
1384  if (mem_params[i].direction == PARAM_IN)
1385  continue;
1386  retval = target_write_buffer(target, mem_params[i].address,
1387  mem_params[i].size, mem_params[i].value);
1388  if (retval != ERROR_OK)
1389  return retval;
1390  }
1391 
1392  for (i = 0; i < num_reg_params; i++) {
1393  if (reg_params[i].direction == PARAM_IN)
1394  continue;
1395 
1396  struct reg *reg = register_get_by_name(dsp563xx->core_cache,
1397  reg_params[i].reg_name,
1398  false);
1399 
1400  if (!reg) {
1401  LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1402  continue;
1403  }
1404 
1405  if (reg->size != reg_params[i].size) {
1406  LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1407  reg_params[i].reg_name);
1408  continue;
1409  }
1410 
1411  retval = dsp563xx_set_core_reg(reg, reg_params[i].value);
1412  if (retval != ERROR_OK)
1413  return retval;
1414  }
1415 
1416  /* exec */
1417  retval = target_resume(target, false, entry_point, true, true);
1418  if (retval != ERROR_OK)
1419  return retval;
1420 
1421  retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1422  if (retval != ERROR_OK)
1423  return retval;
1424 
1425  for (i = 0; i < num_mem_params; i++) {
1426  if (mem_params[i].direction != PARAM_OUT)
1427  retval = target_read_buffer(target,
1428  mem_params[i].address,
1429  mem_params[i].size,
1430  mem_params[i].value);
1431  if (retval != ERROR_OK)
1432  return retval;
1433  }
1434 
1435  for (i = 0; i < num_reg_params; i++) {
1436  if (reg_params[i].direction != PARAM_OUT) {
1437 
1438  struct reg *reg = register_get_by_name(dsp563xx->core_cache,
1439  reg_params[i].reg_name,
1440  false);
1441  if (!reg) {
1442  LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1443  continue;
1444  }
1445 
1446  if (reg->size != reg_params[i].size) {
1447  LOG_ERROR(
1448  "BUG: register '%s' size doesn't match reg_params[i].size",
1449  reg_params[i].reg_name);
1450  continue;
1451  }
1452 
1453  buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1454  }
1455  }
1456 
1457  return ERROR_OK;
1458 }
1459 
1460 /* global command context from openocd.c */
1461 extern struct command_context *global_cmd_ctx;
1462 
1463 static int dsp563xx_get_default_memory(void)
1464 {
1465  Jim_Interp *interp;
1466  Jim_Obj *memspace;
1467  char *c;
1468 
1469  if (!global_cmd_ctx)
1470  return MEM_P;
1471 
1472  interp = global_cmd_ctx->interp;
1473 
1474  if (!interp)
1475  return MEM_P;
1476 
1477  memspace = Jim_GetGlobalVariableStr(interp, "memspace", JIM_NONE);
1478 
1479  if (!memspace)
1480  return MEM_P;
1481 
1482  c = (char *)Jim_GetString(memspace, NULL);
1483 
1484  if (!c)
1485  return MEM_P;
1486 
1487  switch (c[0]) {
1488  case '1':
1489  return MEM_X;
1490  case '2':
1491  return MEM_Y;
1492  case '3':
1493  return MEM_L;
1494  default:
1495  break;
1496  }
1497 
1498  return MEM_P;
1499 }
1500 
1501 static int dsp563xx_read_memory_core(struct target *target,
1502  int mem_type,
1503  uint32_t address,
1504  uint32_t size,
1505  uint32_t count,
1506  uint8_t *buffer)
1507 {
1508  int err;
1509  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1510  uint32_t i, x;
1511  uint32_t data, move_cmd = 0;
1512  uint8_t *b;
1513 
1514  LOG_DEBUG(
1515  "memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
1516  mem_type,
1517  address,
1518  size,
1519  count);
1520 
1521  if (target->state != TARGET_HALTED) {
1522  LOG_WARNING("target not halted");
1523  return ERROR_TARGET_NOT_HALTED;
1524  }
1525 
1526  switch (mem_type) {
1527  case MEM_X:
1528  /* TODO: mark effected queued registers */
1529  move_cmd = 0x61d800;
1530  break;
1531  case MEM_Y:
1532  move_cmd = 0x69d800;
1533  break;
1534  case MEM_P:
1535  move_cmd = 0x07d891;
1536  break;
1537  default:
1538  return ERROR_COMMAND_SYNTAX_ERROR;
1539  }
1540 
1541  /* we use r0 to store temporary data */
1542  if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
1543  dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0);
1544  /* we use r1 to store temporary data */
1545  if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].valid)
1546  dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1);
1547 
1548  /* r0 is no longer valid on target */
1549  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
1550  /* r1 is no longer valid on target */
1551  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
1552 
1553  x = count;
1554  b = buffer;
1555 
1556  err = dsp563xx_once_execute_dw_ir(target->tap, 1, 0x60F400, address);
1557  if (err != ERROR_OK)
1558  return err;
1559 
1560  for (i = 0; i < x; i++) {
1561  err = dsp563xx_once_execute_sw_ir(target->tap, 0, move_cmd);
1562  if (err != ERROR_OK)
1563  return err;
1564  err = dsp563xx_once_execute_sw_ir(target->tap, 0, 0x08D13C);
1565  if (err != ERROR_OK)
1566  return err;
1567  err = dsp563xx_once_reg_read(target->tap, 0,
1568  DSP563XX_ONCE_OGDBR, (uint32_t *)(void *)b);
1569  if (err != ERROR_OK)
1570  return err;
1571  b += 4;
1572  }
1573 
1574  /* flush the jtag queue */
1575  err = jtag_execute_queue();
1576  if (err != ERROR_OK)
1577  return err;
1578 
1579  /* walk over the buffer and fix target endianness */
1580  b = buffer;
1581 
1582  for (i = 0; i < x; i++) {
1583  data = buf_get_u32(b, 0, 32) & 0x00FFFFFF;
1584 /* LOG_DEBUG("R: %08X", *((uint32_t*)b)); */
1585  target_buffer_set_u32(target, b, data);
1586  b += 4;
1587  }
1588 
1589  return ERROR_OK;
1590 }
1591 
1592 static int dsp563xx_read_memory(struct target *target,
1593  int mem_type,
1594  target_addr_t address,
1595  uint32_t size,
1596  uint32_t count,
1597  uint8_t *buffer)
1598 {
1599  int err;
1600  uint32_t i, i1;
1601  uint8_t *buffer_y, *buffer_x;
1602 
1603  /* if size equals zero we are called from target read memory
1604  * and have to handle the parameter here */
1605  if ((size == 0) && (count != 0)) {
1606  size = count % 4;
1607 
1608  if (size)
1609  LOG_DEBUG("size is not aligned to 4 byte");
1610 
1611  count = (count - size) / 4;
1612  size = 4;
1613  }
1614 
1615  /* we only support 4 byte aligned data */
1616  if ((size != 4) || (!count))
1617  return ERROR_COMMAND_SYNTAX_ERROR;
1618 
1619  if (mem_type != MEM_L)
1620  return dsp563xx_read_memory_core(target, mem_type, address, size, count, buffer);
1621 
1622  buffer_y = malloc(size * count);
1623  if (!buffer_y)
1624  return ERROR_COMMAND_SYNTAX_ERROR;
1625 
1626  buffer_x = malloc(size * count);
1627  if (!buffer_x) {
1628  free(buffer_y);
1629  return ERROR_COMMAND_SYNTAX_ERROR;
1630  }
1631 
1632  err = dsp563xx_read_memory_core(target, MEM_Y, address, size, count / 2, buffer_y);
1633 
1634  if (err != ERROR_OK) {
1635  free(buffer_y);
1636  free(buffer_x);
1637  return err;
1638  }
1639 
1640  err = dsp563xx_read_memory_core(target, MEM_X, address, size, count / 2, buffer_x);
1641 
1642  if (err != ERROR_OK) {
1643  free(buffer_y);
1644  free(buffer_x);
1645  return err;
1646  }
1647 
1648  for (i = 0, i1 = 0; i < count; i += 2, i1++) {
1649  buf_set_u32(buffer + i*sizeof(uint32_t), 0, 32,
1650  buf_get_u32(buffer_y + i1 * sizeof(uint32_t), 0, 32));
1651  buf_set_u32(buffer + (i + 1) * sizeof(uint32_t), 0, 32,
1652  buf_get_u32(buffer_x + i1 * sizeof(uint32_t), 0, 32));
1653  }
1654 
1655  free(buffer_y);
1656  free(buffer_x);
1657 
1658  return ERROR_OK;
1659 }
1660 
1661 static int dsp563xx_read_memory_default(struct target *target,
1662  target_addr_t address,
1663  uint32_t size,
1664  uint32_t count,
1665  uint8_t *buffer)
1666 {
1667 
1668  return dsp563xx_read_memory(target,
1669  dsp563xx_get_default_memory(), address, size, count, buffer);
1670 }
1671 
1672 static int dsp563xx_read_buffer_default(struct target *target,
1673  target_addr_t address,
1674  uint32_t size,
1675  uint8_t *buffer)
1676 {
1677 
1678  return dsp563xx_read_memory(target, dsp563xx_get_default_memory(), address, size, 0,
1679  buffer);
1680 }
1681 
1682 static int dsp563xx_write_memory_core(struct target *target,
1683  int mem_type,
1684  target_addr_t address,
1685  uint32_t size,
1686  uint32_t count,
1687  const uint8_t *buffer)
1688 {
1689  int err;
1690  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1691  uint32_t i, x;
1692  uint32_t data, move_cmd = 0;
1693  const uint8_t *b;
1694 
1695  LOG_DEBUG(
1696  "memtype: %d address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
1697  mem_type,
1698  address,
1699  size,
1700  count);
1701 
1702  if (target->state != TARGET_HALTED) {
1703  LOG_TARGET_ERROR(target, "not halted");
1704  return ERROR_TARGET_NOT_HALTED;
1705  }
1706 
1707  switch (mem_type) {
1708  case MEM_X:
1709  /* invalidate affected x registers */
1710  dsp563xx_invalidate_x_context(target, address, address + count - 1);
1711  move_cmd = 0x615800;
1712  break;
1713  case MEM_Y:
1714  move_cmd = 0x695800;
1715  break;
1716  case MEM_P:
1717  move_cmd = 0x075891;
1718  break;
1719  default:
1720  return ERROR_COMMAND_SYNTAX_ERROR;
1721  }
1722 
1723  /* we use r0 to store temporary data */
1724  if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
1725  dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0);
1726  /* we use r1 to store temporary data */
1727  if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].valid)
1728  dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1);
1729 
1730  /* r0 is no longer valid on target */
1731  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
1732  /* r1 is no longer valid on target */
1733  dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
1734 
1735  x = count;
1736  b = buffer;
1737 
1738  err = dsp563xx_once_execute_dw_ir(target->tap, 1, 0x60F400, address);
1739  if (err != ERROR_OK)
1740  return err;
1741 
1742  for (i = 0; i < x; i++) {
1743  data = target_buffer_get_u32(target, b);
1744 
1745 /* LOG_DEBUG("W: %08X", data); */
1746 
1747  data &= 0x00ffffff;
1748 
1749  err = dsp563xx_once_execute_dw_ir(target->tap, 0, 0x61F400, data);
1750  if (err != ERROR_OK)
1751  return err;
1752  err = dsp563xx_once_execute_sw_ir(target->tap, 0, move_cmd);
1753  if (err != ERROR_OK)
1754  return err;
1755  b += 4;
1756  }
1757 
1758  /* flush the jtag queue */
1759  err = jtag_execute_queue();
1760  if (err != ERROR_OK)
1761  return err;
1762 
1763  return ERROR_OK;
1764 }
1765 
1766 static int dsp563xx_write_memory(struct target *target,
1767  int mem_type,
1768  target_addr_t address,
1769  uint32_t size,
1770  uint32_t count,
1771  const uint8_t *buffer)
1772 {
1773  int err;
1774  uint32_t i, i1;
1775  uint8_t *buffer_y, *buffer_x;
1776 
1777  /* if size equals zero we are called from target write memory
1778  * and have to handle the parameter here */
1779  if ((size == 0) && (count != 0)) {
1780  size = count % 4;
1781 
1782  if (size)
1783  LOG_DEBUG("size is not aligned to 4 byte");
1784 
1785  count = (count - size) / 4;
1786  size = 4;
1787  }
1788 
1789  /* we only support 4 byte aligned data */
1790  if ((size != 4) || (!count))
1791  return ERROR_COMMAND_SYNTAX_ERROR;
1792 
1793  if (mem_type != MEM_L)
1794  return dsp563xx_write_memory_core(target, mem_type, address, size, count, buffer);
1795 
1796  buffer_y = malloc(size * count);
1797  if (!buffer_y)
1798  return ERROR_COMMAND_SYNTAX_ERROR;
1799 
1800  buffer_x = malloc(size * count);
1801  if (!buffer_x) {
1802  free(buffer_y);
1803  return ERROR_COMMAND_SYNTAX_ERROR;
1804  }
1805 
1806  for (i = 0, i1 = 0; i < count; i += 2, i1++) {
1807  buf_set_u32(buffer_y + i1 * sizeof(uint32_t), 0, 32,
1808  buf_get_u32(buffer + i * sizeof(uint32_t), 0, 32));
1809  buf_set_u32(buffer_x + i1 * sizeof(uint32_t), 0, 32,
1810  buf_get_u32(buffer + (i + 1) * sizeof(uint32_t), 0, 32));
1811  }
1812 
1813  err = dsp563xx_write_memory_core(target, MEM_Y, address, size, count / 2, buffer_y);
1814 
1815  if (err != ERROR_OK) {
1816  free(buffer_y);
1817  free(buffer_x);
1818  return err;
1819  }
1820 
1821  err = dsp563xx_write_memory_core(target, MEM_X, address, size, count / 2, buffer_x);
1822 
1823  if (err != ERROR_OK) {
1824  free(buffer_y);
1825  free(buffer_x);
1826  return err;
1827  }
1828 
1829  free(buffer_y);
1830  free(buffer_x);
1831 
1832  return ERROR_OK;
1833 }
1834 
1835 static int dsp563xx_write_memory_default(struct target *target,
1836  target_addr_t address,
1837  uint32_t size,
1838  uint32_t count,
1839  const uint8_t *buffer)
1840 {
1841  return dsp563xx_write_memory(target,
1842  dsp563xx_get_default_memory(), address, size, count, buffer);
1843 }
1844 
1845 static int dsp563xx_write_buffer_default(struct target *target,
1846  target_addr_t address,
1847  uint32_t size,
1848  const uint8_t *buffer)
1849 {
1850  return dsp563xx_write_memory(target, dsp563xx_get_default_memory(), address, size, 0,
1851  buffer);
1852 }
1853 
1854 /*
1855  * Exit with error here, because we support watchpoints over a custom command.
1856  * This is because the DSP has separate X,Y,P memspace which is not compatible to the
1857  * traditional watchpoint logic.
1858  */
1859 static int dsp563xx_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1860 {
1861  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1862 }
1863 
1864 /*
1865  * @see dsp563xx_add_watchpoint
1866  */
1867 static int dsp563xx_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1868 {
1869  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1870 }
1871 
1872 static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t address, uint32_t mem_type,
1873  enum watchpoint_rw rw, enum watchpoint_condition cond)
1874 {
1875  int err = ERROR_OK;
1876  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1877 
1878  bool was_running = false;
1879  /* Only set breakpoint when halted */
1880  if (target->state != TARGET_HALTED) {
1881  dsp563xx_halt(target);
1882  was_running = true;
1883  }
1884 
1885  if (dsp563xx->hardware_breakpoint[0].used) {
1886  LOG_ERROR("Cannot add watchpoint. Hardware resource already used.");
1887  err = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1888  }
1889 
1890  uint32_t obcr_value = 0;
1891  if (err == ERROR_OK) {
1892  obcr_value |= OBCR_B0_OR_B1;
1893  switch (mem_type) {
1894  case MEM_X:
1895  obcr_value |= OBCR_BP_MEM_X;
1896  break;
1897  case MEM_Y:
1898  obcr_value |= OBCR_BP_MEM_Y;
1899  break;
1900  case MEM_P:
1901  obcr_value |= OBCR_BP_MEM_P;
1902  break;
1903  default:
1904  LOG_ERROR("Unknown mem_type parameter (%" PRIu32 ")", mem_type);
1905  err = ERROR_TARGET_INVALID;
1906  }
1907  }
1908 
1909  if (err == ERROR_OK) {
1910  switch (rw) {
1911  case WPT_READ:
1912  obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ);
1913  break;
1914  case WPT_WRITE:
1915  obcr_value |= OBCR_BP_0(OBCR_BP_ON_WRITE);
1916  break;
1917  case WPT_ACCESS:
1918  obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ | OBCR_BP_ON_WRITE);
1919  break;
1920  default:
1921  LOG_ERROR("Unsupported write mode (%d)", rw);
1922  err = ERROR_TARGET_INVALID;
1923  }
1924  }
1925 
1926  if (err == ERROR_OK) {
1927  switch (cond) {
1928  case EQUAL:
1929  obcr_value |= OBCR_BP_0(OBCR_BP_CC_EQUAL);
1930  break;
1931  case NOT_EQUAL:
1932  obcr_value |= OBCR_BP_0(OBCR_BP_CC_NOT_EQUAL);
1933  break;
1934  case LESS_THAN:
1935  obcr_value |= OBCR_BP_0(OBCR_BP_CC_LESS_THAN);
1936  break;
1937  case GREATER:
1938  obcr_value |= OBCR_BP_0(OBCR_BP_CC_GREATER_THAN);
1939  break;
1940  default:
1941  LOG_ERROR("Unsupported condition code (%d)", cond);
1942  err = ERROR_TARGET_INVALID;
1943  }
1944  }
1945 
1946  if (err == ERROR_OK)
1947  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMLR0, address);
1948 
1949  if (err == ERROR_OK)
1950  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMLR1, 0x0);
1951 
1952  if (err == ERROR_OK)
1953  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, obcr_value);
1954 
1955  if (err == ERROR_OK) {
1956  /* You should write the memory breakpoint counter to 0 */
1957  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMBC, 0);
1958  }
1959 
1960  if (err == ERROR_OK) {
1961  /* You should write the memory breakpoint counter to 0 */
1962  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OTC, 0);
1963  }
1964 
1965  if (err == ERROR_OK)
1966  dsp563xx->hardware_breakpoint[0].used = BPU_WATCHPOINT;
1967 
1968  if (err == ERROR_OK && was_running) {
1969  /* Resume from current PC */
1970  err = dsp563xx_resume(target, true, 0x0, false, false);
1971  }
1972 
1973  return err;
1974 }
1975 
1976 static int dsp563xx_remove_custom_watchpoint(struct target *target)
1977 {
1978  int err = ERROR_OK;
1979  struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1980 
1981  if (dsp563xx->hardware_breakpoint[0].used != BPU_WATCHPOINT) {
1982  LOG_ERROR("Cannot remove watchpoint, as no watchpoint is currently configured!");
1983  err = ERROR_TARGET_INVALID;
1984  }
1985 
1986  if (err == ERROR_OK) {
1987  /* Clear watchpoint by clearing OBCR. */
1988  err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, 0);
1989  }
1990 
1991  if (err == ERROR_OK)
1992  dsp563xx->hardware_breakpoint[0].used = BPU_NONE;
1993 
1994  return err;
1995 }
1996 
1997 COMMAND_HANDLER(dsp563xx_add_watchpoint_command)
1998 {
1999  int err = ERROR_OK;
2000  struct target *target = get_current_target(CMD_CTX);
2001 
2002  uint32_t mem_type = 0;
2003  switch (CMD_NAME[2]) {
2004  case 'x':
2005  mem_type = MEM_X;
2006  break;
2007  case 'y':
2008  mem_type = MEM_Y;
2009  break;
2010  case 'p':
2011  mem_type = MEM_P;
2012  break;
2013  default:
2014  return ERROR_COMMAND_SYNTAX_ERROR;
2015  }
2016 
2017  if (CMD_ARGC < 2)
2018  return ERROR_COMMAND_SYNTAX_ERROR;
2019 
2020  uint32_t address = 0;
2021  if (CMD_ARGC > 2)
2022  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
2023 
2024  enum watchpoint_condition cond;
2025  switch (CMD_ARGV[0][0]) {
2026  case '>':
2027  cond = GREATER;
2028  break;
2029  case '<':
2030  cond = LESS_THAN;
2031  break;
2032  case '=':
2033  cond = EQUAL;
2034  break;
2035  case '!':
2036  cond = NOT_EQUAL;
2037  break;
2038  default:
2039  return ERROR_COMMAND_SYNTAX_ERROR;
2040  }
2041 
2042  enum watchpoint_rw rw;
2043  switch (CMD_ARGV[1][0]) {
2044  case 'r':
2045  rw = WPT_READ;
2046  break;
2047  case 'w':
2048  rw = WPT_WRITE;
2049  break;
2050  case 'a':
2051  rw = WPT_ACCESS;
2052  break;
2053  default:
2054  return ERROR_COMMAND_SYNTAX_ERROR;
2055  }
2056 
2057  err = dsp563xx_add_custom_watchpoint(target, address, mem_type, rw, cond);
2058 
2059  return err;
2060 }
2061 
2062 /* Adding a breakpoint using the once breakpoint logic.
2063  * Note that this mechanism is a true hw breakpoint and is share between the watchpoint logic.
2064  * This means, you can only have one breakpoint/watchpoint at any time.
2065  */
2066 static int dsp563xx_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
2067 {
2068  return dsp563xx_add_custom_watchpoint(target, breakpoint->address, MEM_P, WPT_READ, EQUAL);
2069 }
2070 
2071 static int dsp563xx_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
2072 {
2073  return dsp563xx_remove_custom_watchpoint(target);
2074 }
2075 
2076 COMMAND_HANDLER(dsp563xx_remove_watchpoint_command)
2077 {
2078  struct target *target = get_current_target(CMD_CTX);
2079 
2080  return dsp563xx_remove_custom_watchpoint(target);
2081 }
2082 
2083 COMMAND_HANDLER(dsp563xx_mem_command)
2084 {
2085  struct target *target = get_current_target(CMD_CTX);
2086  int err = ERROR_OK;
2087  int read_mem;
2088  uint32_t address = 0;
2089  uint32_t count = 1, i;
2090  uint32_t pattern = 0;
2091  uint32_t mem_type;
2092  uint8_t *buffer, *b;
2093 
2094  switch (CMD_NAME[1]) {
2095  case 'w':
2096  read_mem = 0;
2097  break;
2098  case 'd':
2099  read_mem = 1;
2100  break;
2101  default:
2102  return ERROR_COMMAND_SYNTAX_ERROR;
2103  }
2104 
2105  switch (CMD_NAME[3]) {
2106  case 'x':
2107  mem_type = MEM_X;
2108  break;
2109  case 'y':
2110  mem_type = MEM_Y;
2111  break;
2112  case 'p':
2113  mem_type = MEM_P;
2114  break;
2115  default:
2116  return ERROR_COMMAND_SYNTAX_ERROR;
2117  }
2118 
2119  if (CMD_ARGC > 0)
2120  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2121 
2122  if (read_mem == 0) {
2123  if (CMD_ARGC < 2)
2124  return ERROR_COMMAND_SYNTAX_ERROR;
2125  if (CMD_ARGC > 1)
2126  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], pattern);
2127  if (CMD_ARGC > 2)
2128  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
2129  }
2130 
2131  if (read_mem == 1) {
2132  if (CMD_ARGC < 1)
2133  return ERROR_COMMAND_SYNTAX_ERROR;
2134  if (CMD_ARGC > 1)
2135  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], count);
2136  }
2137 
2138  buffer = calloc(count, 4);
2139 
2140  if (read_mem == 1) {
2141  err = dsp563xx_read_memory(target, mem_type, address, sizeof(uint32_t),
2142  count, buffer);
2143  if (err == ERROR_OK)
2144  target_handle_md_output(CMD, target, address, sizeof(uint32_t),
2145  count, buffer, true);
2146 
2147  } else {
2148  b = buffer;
2149 
2150  for (i = 0; i < count; i++) {
2151  target_buffer_set_u32(target, b, pattern);
2152  b += 4;
2153  }
2154 
2155  err = dsp563xx_write_memory(target,
2156  mem_type,
2157  address,
2158  sizeof(uint32_t),
2159  count,
2160  buffer);
2161  }
2162 
2163  free(buffer);
2164 
2165  return err;
2166 }
2167 
2168 static const struct command_registration dsp563xx_command_handlers[] = {
2169  {
2170  .name = "mwwx",
2171  .handler = dsp563xx_mem_command,
2172  .mode = COMMAND_EXEC,
2173  .help = "write x memory words",
2174  .usage = "address value [count]",
2175  },
2176  {
2177  .name = "mwwy",
2178  .handler = dsp563xx_mem_command,
2179  .mode = COMMAND_EXEC,
2180  .help = "write y memory words",
2181  .usage = "address value [count]",
2182  },
2183  {
2184  .name = "mwwp",
2185  .handler = dsp563xx_mem_command,
2186  .mode = COMMAND_EXEC,
2187  .help = "write p memory words",
2188  .usage = "address value [count]",
2189  },
2190  {
2191  .name = "mdwx",
2192  .handler = dsp563xx_mem_command,
2193  .mode = COMMAND_EXEC,
2194  .help = "display x memory words",
2195  .usage = "address [count]",
2196  },
2197  {
2198  .name = "mdwy",
2199  .handler = dsp563xx_mem_command,
2200  .mode = COMMAND_EXEC,
2201  .help = "display y memory words",
2202  .usage = "address [count]",
2203  },
2204  {
2205  .name = "mdwp",
2206  .handler = dsp563xx_mem_command,
2207  .mode = COMMAND_EXEC,
2208  .help = "display p memory words",
2209  .usage = "address [count]",
2210  },
2211  /*
2212  * Watchpoint commands
2213  */
2214  {
2215  .name = "wpp",
2216  .handler = dsp563xx_add_watchpoint_command,
2217  .mode = COMMAND_EXEC,
2218  .help = "Create p memspace watchpoint",
2219  .usage = "(>|<|=|!) (r|w|a) address",
2220  },
2221  {
2222  .name = "wpx",
2223  .handler = dsp563xx_add_watchpoint_command,
2224  .mode = COMMAND_EXEC,
2225  .help = "Create x memspace watchpoint",
2226  .usage = "(>|<|=|!) (r|w|a) address",
2227  },
2228  {
2229  .name = "wpy",
2230  .handler = dsp563xx_add_watchpoint_command,
2231  .mode = COMMAND_EXEC,
2232  .help = "Create y memspace watchpoint",
2233  .usage = "(>|<|=|!) (r|w|a) address",
2234  },
2235  {
2236  .name = "rwpc",
2237  .handler = dsp563xx_remove_watchpoint_command,
2238  .mode = COMMAND_EXEC,
2239  .help = "remove watchpoint custom",
2240  .usage = "",
2241  },
2242  COMMAND_REGISTRATION_DONE
2243 };
2244 
2246 struct target_type dsp563xx_target = {
2247  .name = "dsp563xx",
2248 
2249  .poll = dsp563xx_poll,
2250  .arch_state = dsp563xx_arch_state,
2251 
2252  .get_gdb_reg_list = dsp563xx_get_gdb_reg_list,
2253 
2254  .halt = dsp563xx_halt,
2255  .resume = dsp563xx_resume,
2256  .step = dsp563xx_step,
2257 
2258  .assert_reset = dsp563xx_assert_reset,
2259  .deassert_reset = dsp563xx_deassert_reset,
2260 
2261  .read_memory = dsp563xx_read_memory_default,
2262  .write_memory = dsp563xx_write_memory_default,
2263 
2264  .read_buffer = dsp563xx_read_buffer_default,
2265  .write_buffer = dsp563xx_write_buffer_default,
2266 
2267  .run_algorithm = dsp563xx_run_algorithm,
2268 
2269  .add_breakpoint = dsp563xx_add_breakpoint,
2270  .remove_breakpoint = dsp563xx_remove_breakpoint,
2271  .add_watchpoint = dsp563xx_add_watchpoint,
2272  .remove_watchpoint = dsp563xx_remove_watchpoint,
2273 
2274  .commands = dsp563xx_command_handlers,
2275  .target_create = dsp563xx_target_create,
2276  .init_target = dsp563xx_init_target,
2277  .examine = dsp563xx_examine,
2278 };
PARAM_OUT
@ PARAM_OUT
Definition: algorithm.h:16
PARAM_IN
@ PARAM_IN
Definition: algorithm.h:15
buf_get_u32
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:104
buf_set_u32
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
watchpoint_rw
watchpoint_rw
Definition: breakpoints.h:22
WPT_ACCESS
@ WPT_ACCESS
Definition: breakpoints.h:23
WPT_READ
@ WPT_READ
Definition: breakpoints.h:23
WPT_WRITE
@ WPT_WRITE
Definition: breakpoints.h:23
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:146
CMD_NAME
#define CMD_NAME
Use this macro to access the name of the command being handled, rather than accessing the variable di...
Definition: command.h:171
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:161
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:405
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:156
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:445
CMD_CTX
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:151
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:256
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
ASM_REG_W_PC
#define ASM_REG_W_PC
Definition: dsp563xx.c:74
ASM_REG_W_Y0
#define ASM_REG_W_Y0
Definition: dsp563xx.c:52
ASM_REG_W_M7
#define ASM_REG_W_M7
Definition: dsp563xx.c:47
ASM_REG_W_IPRC
#define ASM_REG_W_IPRC
Definition: dsp563xx.c:75
dsp563xx_reg_type
static const struct reg_arch_type dsp563xx_reg_type
Definition: dsp563xx.c:430
dsp563xx_deassert_reset
static int dsp563xx_deassert_reset(struct target *target)
Definition: dsp563xx.c:1340
ASM_REG_W_N3
#define ASM_REG_W_N3
Definition: dsp563xx.c:34
dsp563xx_write_memory
static int dsp563xx_write_memory(struct target *target, int mem_type, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: dsp563xx.c:1766
dsp563xx_add_custom_watchpoint
static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t address, uint32_t mem_type, enum watchpoint_rw rw, enum watchpoint_condition cond)
Definition: dsp563xx.c:1872
OBCR_BP_MEM_Y
#define OBCR_BP_MEM_Y
Definition: dsp563xx.c:96
INSTR_JUMP
#define INSTR_JUMP
Definition: dsp563xx.c:311
ASM_REG_W_M5
#define ASM_REG_W_M5
Definition: dsp563xx.c:45
OBCR_BP_CC_NOT_EQUAL
#define OBCR_BP_CC_NOT_EQUAL
Definition: dsp563xx.c:99
dsp563xx_remove_watchpoint
static int dsp563xx_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: dsp563xx.c:1867
dsp563xx_reg_read
static int dsp563xx_reg_read(struct target *target, uint32_t eame, uint32_t *data)
Definition: dsp563xx.c:532
global_cmd_ctx
struct command_context * global_cmd_ctx
Definition: openocd.c:234
dsp563xx_read_memory
static int dsp563xx_read_memory(struct target *target, int mem_type, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: dsp563xx.c:1592
dsp563xx_debug_once_init
static int dsp563xx_debug_once_init(struct target *target)
Definition: dsp563xx.c:942
dsp563xx_reg_read_high_io
static int dsp563xx_reg_read_high_io(struct target *target, uint32_t instr_mask, uint32_t *data)
Definition: dsp563xx.c:476
once_regs
static struct once_reg once_regs[]
Definition: dsp563xx.c:136
dsp563xx_remove_breakpoint
static int dsp563xx_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: dsp563xx.c:2071
dsp563xx_arch_state
static int dsp563xx_arch_state(struct target *target)
Definition: dsp563xx.c:933
OBCR_B0_OR_B1
#define OBCR_B0_OR_B1
Definition: dsp563xx.c:89
OBCR_BP_MEM_P
#define OBCR_BP_MEM_P
Definition: dsp563xx.c:94
dsp563xx_reg_ssh_read
static int dsp563xx_reg_ssh_read(struct target *target)
Definition: dsp563xx.c:599
dsp563xx_add_breakpoint
static int dsp563xx_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: dsp563xx.c:2066
dsp563xx_regs
static const struct @90 dsp563xx_regs[]
once_reg_idx
once_reg_idx
Definition: dsp563xx.c:108
ONCE_REG_IDX_OTC
@ ONCE_REG_IDX_OTC
Definition: dsp563xx.c:118
ONCE_REG_IDX_OSCR
@ ONCE_REG_IDX_OSCR
Definition: dsp563xx.c:109
ONCE_REG_IDX_OMLR0
@ ONCE_REG_IDX_OMLR0
Definition: dsp563xx.c:112
ONCE_REG_IDX_OPABF9
@ ONCE_REG_IDX_OPABF9
Definition: dsp563xx.c:131
ONCE_REG_IDX_OPABF8
@ ONCE_REG_IDX_OPABF8
Definition: dsp563xx.c:130
ONCE_REG_IDX_OPILR
@ ONCE_REG_IDX_OPILR
Definition: dsp563xx.c:116
ONCE_REG_IDX_OPABF0
@ ONCE_REG_IDX_OPABF0
Definition: dsp563xx.c:122
ONCE_REG_IDX_OPABF1
@ ONCE_REG_IDX_OPABF1
Definition: dsp563xx.c:123
ONCE_REG_IDX_OPABF7
@ ONCE_REG_IDX_OPABF7
Definition: dsp563xx.c:129
ONCE_REG_IDX_OPABF6
@ ONCE_REG_IDX_OPABF6
Definition: dsp563xx.c:128
ONCE_REG_IDX_OPABF11
@ ONCE_REG_IDX_OPABF11
Definition: dsp563xx.c:133
ONCE_REG_IDX_OMBC
@ ONCE_REG_IDX_OMBC
Definition: dsp563xx.c:110
ONCE_REG_IDX_OPABF3
@ ONCE_REG_IDX_OPABF3
Definition: dsp563xx.c:125
ONCE_REG_IDX_OPABEX
@ ONCE_REG_IDX_OPABEX
Definition: dsp563xx.c:121
ONCE_REG_IDX_OPDBR
@ ONCE_REG_IDX_OPDBR
Definition: dsp563xx.c:115
ONCE_REG_IDX_OPABF5
@ ONCE_REG_IDX_OPABF5
Definition: dsp563xx.c:127
ONCE_REG_IDX_OPABF2
@ ONCE_REG_IDX_OPABF2
Definition: dsp563xx.c:124
ONCE_REG_IDX_OPABDR
@ ONCE_REG_IDX_OPABDR
Definition: dsp563xx.c:120
ONCE_REG_IDX_OGDBR
@ ONCE_REG_IDX_OGDBR
Definition: dsp563xx.c:114
ONCE_REG_IDX_OMLR1
@ ONCE_REG_IDX_OMLR1
Definition: dsp563xx.c:113
ONCE_REG_IDX_PDB
@ ONCE_REG_IDX_PDB
Definition: dsp563xx.c:117
ONCE_REG_IDX_OPABF10
@ ONCE_REG_IDX_OPABF10
Definition: dsp563xx.c:132
ONCE_REG_IDX_OPABFR
@ ONCE_REG_IDX_OPABFR
Definition: dsp563xx.c:119
ONCE_REG_IDX_OPABF4
@ ONCE_REG_IDX_OPABF4
Definition: dsp563xx.c:126
ONCE_REG_IDX_OBCR
@ ONCE_REG_IDX_OBCR
Definition: dsp563xx.c:111
ASM_REG_W_A2
#define ASM_REG_W_A2
Definition: dsp563xx.c:57
dsp563xx_examine
static int dsp563xx_examine(struct target *target)
Definition: dsp563xx.c:908
dsp563xx_write_memory_default
static int dsp563xx_write_memory_default(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: dsp563xx.c:1835
ASM_REG_W_M0
#define ASM_REG_W_M0
Definition: dsp563xx.c:40
dsp563xx_reg_idx
dsp563xx_reg_idx
Definition: dsp563xx.c:165
DSP563XX_REG_IDX_R0
@ DSP563XX_REG_IDX_R0
Definition: dsp563xx.c:166
DSP563XX_REG_IDX_AAR2
@ DSP563XX_REG_IDX_AAR2
Definition: dsp563xx.c:218
DSP563XX_REG_IDX_B0
@ DSP563XX_REG_IDX_B0
Definition: dsp563xx.c:197
DSP563XX_REG_IDX_R5
@ DSP563XX_REG_IDX_R5
Definition: dsp563xx.c:171
DSP563XX_REG_IDX_SP
@ DSP563XX_REG_IDX_SP
Definition: dsp563xx.c:202
DSP563XX_REG_IDX_BCR
@ DSP563XX_REG_IDX_BCR
Definition: dsp563xx.c:214
DSP563XX_REG_IDX_Y1
@ DSP563XX_REG_IDX_Y1
Definition: dsp563xx.c:193
DSP563XX_REG_IDX_M7
@ DSP563XX_REG_IDX_M7
Definition: dsp563xx.c:189
DSP563XX_REG_IDX_A0
@ DSP563XX_REG_IDX_A0
Definition: dsp563xx.c:194
DSP563XX_REG_IDX_SSL
@ DSP563XX_REG_IDX_SSL
Definition: dsp563xx.c:201
DSP563XX_REG_IDX_LA
@ DSP563XX_REG_IDX_LA
Definition: dsp563xx.c:209
DSP563XX_REG_IDX_OMR
@ DSP563XX_REG_IDX_OMR
Definition: dsp563xx.c:208
DSP563XX_REG_IDX_M0
@ DSP563XX_REG_IDX_M0
Definition: dsp563xx.c:182
DSP563XX_REG_IDX_N3
@ DSP563XX_REG_IDX_N3
Definition: dsp563xx.c:177
DSP563XX_REG_IDX_X1
@ DSP563XX_REG_IDX_X1
Definition: dsp563xx.c:191
DSP563XX_REG_IDX_R6
@ DSP563XX_REG_IDX_R6
Definition: dsp563xx.c:172
DSP563XX_REG_IDX_N0
@ DSP563XX_REG_IDX_N0
Definition: dsp563xx.c:174
DSP563XX_REG_IDX_N1
@ DSP563XX_REG_IDX_N1
Definition: dsp563xx.c:175
DSP563XX_REG_IDX_N6
@ DSP563XX_REG_IDX_N6
Definition: dsp563xx.c:180
DSP563XX_REG_IDX_B2
@ DSP563XX_REG_IDX_B2
Definition: dsp563xx.c:199
DSP563XX_REG_IDX_R4
@ DSP563XX_REG_IDX_R4
Definition: dsp563xx.c:170
DSP563XX_REG_IDX_M3
@ DSP563XX_REG_IDX_M3
Definition: dsp563xx.c:185
DSP563XX_REG_IDX_AAR1
@ DSP563XX_REG_IDX_AAR1
Definition: dsp563xx.c:217
DSP563XX_REG_IDX_AAR0
@ DSP563XX_REG_IDX_AAR0
Definition: dsp563xx.c:216
DSP563XX_REG_IDX_A2
@ DSP563XX_REG_IDX_A2
Definition: dsp563xx.c:196
DSP563XX_REG_IDX_N2
@ DSP563XX_REG_IDX_N2
Definition: dsp563xx.c:176
DSP563XX_REG_IDX_EP
@ DSP563XX_REG_IDX_EP
Definition: dsp563xx.c:203
DSP563XX_REG_IDX_R3
@ DSP563XX_REG_IDX_R3
Definition: dsp563xx.c:169
DSP563XX_REG_IDX_SR
@ DSP563XX_REG_IDX_SR
Definition: dsp563xx.c:207
DSP563XX_REG_IDX_M2
@ DSP563XX_REG_IDX_M2
Definition: dsp563xx.c:184
DSP563XX_REG_IDX_N5
@ DSP563XX_REG_IDX_N5
Definition: dsp563xx.c:179
DSP563XX_REG_IDX_DCR
@ DSP563XX_REG_IDX_DCR
Definition: dsp563xx.c:215
DSP563XX_REG_IDX_M6
@ DSP563XX_REG_IDX_M6
Definition: dsp563xx.c:188
DSP563XX_REG_IDX_N7
@ DSP563XX_REG_IDX_N7
Definition: dsp563xx.c:181
DSP563XX_REG_IDX_SZ
@ DSP563XX_REG_IDX_SZ
Definition: dsp563xx.c:204
DSP563XX_REG_IDX_M1
@ DSP563XX_REG_IDX_M1
Definition: dsp563xx.c:183
DSP563XX_REG_IDX_B1
@ DSP563XX_REG_IDX_B1
Definition: dsp563xx.c:198
DSP563XX_REG_IDX_LC
@ DSP563XX_REG_IDX_LC
Definition: dsp563xx.c:210
DSP563XX_REG_IDX_Y0
@ DSP563XX_REG_IDX_Y0
Definition: dsp563xx.c:192
DSP563XX_REG_IDX_R1
@ DSP563XX_REG_IDX_R1
Definition: dsp563xx.c:167
DSP563XX_REG_IDX_SC
@ DSP563XX_REG_IDX_SC
Definition: dsp563xx.c:205
DSP563XX_REG_IDX_R7
@ DSP563XX_REG_IDX_R7
Definition: dsp563xx.c:173
DSP563XX_REG_IDX_M5
@ DSP563XX_REG_IDX_M5
Definition: dsp563xx.c:187
DSP563XX_REG_IDX_A1
@ DSP563XX_REG_IDX_A1
Definition: dsp563xx.c:195
DSP563XX_REG_IDX_N4
@ DSP563XX_REG_IDX_N4
Definition: dsp563xx.c:178
DSP563XX_REG_IDX_X0
@ DSP563XX_REG_IDX_X0
Definition: dsp563xx.c:190
DSP563XX_REG_IDX_VBA
@ DSP563XX_REG_IDX_VBA
Definition: dsp563xx.c:211
DSP563XX_REG_IDX_IPRC
@ DSP563XX_REG_IDX_IPRC
Definition: dsp563xx.c:212
DSP563XX_REG_IDX_M4
@ DSP563XX_REG_IDX_M4
Definition: dsp563xx.c:186
DSP563XX_REG_IDX_R2
@ DSP563XX_REG_IDX_R2
Definition: dsp563xx.c:168
DSP563XX_REG_IDX_AAR3
@ DSP563XX_REG_IDX_AAR3
Definition: dsp563xx.c:219
DSP563XX_REG_IDX_PC
@ DSP563XX_REG_IDX_PC
Definition: dsp563xx.c:206
DSP563XX_REG_IDX_IPRP
@ DSP563XX_REG_IDX_IPRP
Definition: dsp563xx.c:213
DSP563XX_REG_IDX_SSH
@ DSP563XX_REG_IDX_SSH
Definition: dsp563xx.c:200
DSP563XX_SR_SC
#define DSP563XX_SR_SC
Definition: dsp563xx.c:940
dsp563xx_jtag_debug_request
static int dsp563xx_jtag_debug_request(struct target *target)
Definition: dsp563xx.c:1028
COMMAND_HANDLER
COMMAND_HANDLER(dsp563xx_add_watchpoint_command)
Definition: dsp563xx.c:1997
dsp563xx_read_core_reg
static int dsp563xx_read_core_reg(struct target *target, int num)
Definition: dsp563xx.c:366
dsp563xx_remove_custom_watchpoint
static int dsp563xx_remove_custom_watchpoint(struct target *target)
Definition: dsp563xx.c:1976
ASM_REG_W_X0
#define ASM_REG_W_X0
Definition: dsp563xx.c:49
OBCR_BP_MEM_X
#define OBCR_BP_MEM_X
Definition: dsp563xx.c:95
ASM_REG_W_N2
#define ASM_REG_W_N2
Definition: dsp563xx.c:33
dsp563xx_write_core_reg
static int dsp563xx_write_core_reg(struct target *target, int num)
Definition: dsp563xx.c:382
OBCR_BP_ON_WRITE
#define OBCR_BP_ON_WRITE
Definition: dsp563xx.c:98
dsp563xx_write_memory_core
static int dsp563xx_write_memory_core(struct target *target, int mem_type, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: dsp563xx.c:1682
instr_mask
uint32_t instr_mask
Definition: dsp563xx.c:228
ASM_REG_W_EP
#define ASM_REG_W_EP
Definition: dsp563xx.c:65
ASM_REG_W_AAR3
#define ASM_REG_W_AAR3
Definition: dsp563xx.c:83
ASM_REG_W_SP
#define ASM_REG_W_SP
Definition: dsp563xx.c:69
memory_type
memory_type
Definition: dsp563xx.c:297
MEM_Y
@ MEM_Y
Definition: dsp563xx.c:299
MEM_P
@ MEM_P
Definition: dsp563xx.c:300
MEM_X
@ MEM_X
Definition: dsp563xx.c:298
MEM_L
@ MEM_L
Definition: dsp563xx.c:301
ASM_REG_W_SSH
#define ASM_REG_W_SSH
Definition: dsp563xx.c:70
ASM_REG_W_AAR1
#define ASM_REG_W_AAR1
Definition: dsp563xx.c:81
ASM_REG_W_DCR
#define ASM_REG_W_DCR
Definition: dsp563xx.c:79
ASM_REG_W_IPRP
#define ASM_REG_W_IPRP
Definition: dsp563xx.c:76
ASM_REG_W_N5
#define ASM_REG_W_N5
Definition: dsp563xx.c:36
dsp563xx_init_target
static int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target)
Definition: dsp563xx.c:895
ASM_REG_W_X1
#define ASM_REG_W_X1
Definition: dsp563xx.c:50
dsp563xx_read_memory_core
static int dsp563xx_read_memory_core(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: dsp563xx.c:1501
ASM_REG_W_R3
#define ASM_REG_W_R3
Definition: dsp563xx.c:25
dsp563xx_reg_write_high_io
static int dsp563xx_reg_write_high_io(struct target *target, uint32_t instr_mask, uint32_t data)
Definition: dsp563xx.c:506
ASM_REG_W_AAR2
#define ASM_REG_W_AAR2
Definition: dsp563xx.c:82
ASM_REG_W_R1
#define ASM_REG_W_R1
Definition: dsp563xx.c:23
ASM_REG_W_AAR0
#define ASM_REG_W_AAR0
Definition: dsp563xx.c:80
dsp563xx_halt
static int dsp563xx_halt(struct target *target)
Definition: dsp563xx.c:1089
ASM_REG_W_SR
#define ASM_REG_W_SR
Definition: dsp563xx.c:68
ASM_REG_W_N7
#define ASM_REG_W_N7
Definition: dsp563xx.c:38
ASM_REG_W_R4
#define ASM_REG_W_R4
Definition: dsp563xx.c:26
ASM_REG_W_N4
#define ASM_REG_W_N4
Definition: dsp563xx.c:35
watchpoint_condition
watchpoint_condition
Definition: dsp563xx.c:304
GREATER
@ GREATER
Definition: dsp563xx.c:307
LESS_THAN
@ LESS_THAN
Definition: dsp563xx.c:308
EQUAL
@ EQUAL
Definition: dsp563xx.c:305
NOT_EQUAL
@ NOT_EQUAL
Definition: dsp563xx.c:306
OBCR_BP_0
#define OBCR_BP_0(x)
Definition: dsp563xx.c:104
ASM_REG_W_Y1
#define ASM_REG_W_Y1
Definition: dsp563xx.c:53
dsp563xx_build_reg_cache
static void dsp563xx_build_reg_cache(struct target *target)
Definition: dsp563xx.c:435
OBCR_BP_CC_GREATER_THAN
#define OBCR_BP_CC_GREATER_THAN
Definition: dsp563xx.c:102
dsp563xx_get_default_memory
static int dsp563xx_get_default_memory(void)
Definition: dsp563xx.c:1463
dsp563xx_write_buffer_default
static int dsp563xx_write_buffer_default(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: dsp563xx.c:1845
ASM_REG_W_A0
#define ASM_REG_W_A0
Definition: dsp563xx.c:55
gdb_reg_list_idx
static const uint8_t gdb_reg_list_idx[]
Definition: dsp563xx.c:325
eame
uint8_t eame
Definition: dsp563xx.c:227
EAME_R0
#define EAME_R0
Definition: dsp563xx.c:313
dsp563xx_read_memory_default
static int dsp563xx_read_memory_default(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: dsp563xx.c:1661
dsp563xx_reg_write
static int dsp563xx_reg_write(struct target *target, uint32_t instr_mask, uint32_t data)
Definition: dsp563xx.c:549
ASM_REG_W_M2
#define ASM_REG_W_M2
Definition: dsp563xx.c:42
ASM_REG_W_M4
#define ASM_REG_W_M4
Definition: dsp563xx.c:44
dsp563xx_step_ex
static int dsp563xx_step_ex(struct target *target, bool current, uint32_t address, bool handle_breakpoints, int steps)
Definition: dsp563xx.c:1169
ASM_REG_W_R5
#define ASM_REG_W_R5
Definition: dsp563xx.c:27
ASM_REG_W_OMR
#define ASM_REG_W_OMR
Definition: dsp563xx.c:64
dsp563xx_invalidate_x_context
static void dsp563xx_invalidate_x_context(struct target *target, uint32_t addr_start, uint32_t addr_end)
Definition: dsp563xx.c:856
dsp563xx_write_register
static int dsp563xx_write_register(struct target *target, int num, int force)
Definition: dsp563xx.c:781
dsp563xx_poll
static int dsp563xx_poll(struct target *target)
Definition: dsp563xx.c:1033
dsp563xx_reg_ssh_write
static int dsp563xx_reg_ssh_write(struct target *target)
Definition: dsp563xx.c:659
ASM_REG_W_B1
#define ASM_REG_W_B1
Definition: dsp563xx.c:60
dsp563xx_get_gdb_reg_list
static int dsp563xx_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: dsp563xx.c:342
bits
unsigned int bits
Definition: dsp563xx.c:225
dsp563xx_debug_init
static int dsp563xx_debug_init(struct target *target)
Definition: dsp563xx.c:947
ASM_REG_W_N0
#define ASM_REG_W_N0
Definition: dsp563xx.c:31
dsp563xx_set_core_reg
static int dsp563xx_set_core_reg(struct reg *reg, uint8_t *buf)
Definition: dsp563xx.c:412
ASM_REG_W_BCR
#define ASM_REG_W_BCR
Definition: dsp563xx.c:78
ASM_REG_W_VBA
#define ASM_REG_W_VBA
Definition: dsp563xx.c:63
dsp563xx_reg_ssl_read
static int dsp563xx_reg_ssl_read(struct target *target)
Definition: dsp563xx.c:701
dsp563xx_run_algorithm
static int dsp563xx_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Definition: dsp563xx.c:1368
OBCR_BP_CC_LESS_THAN
#define OBCR_BP_CC_LESS_THAN
Definition: dsp563xx.c:101
ASM_REG_W_R7
#define ASM_REG_W_R7
Definition: dsp563xx.c:29
dsp563xx_command_handlers
static const struct command_registration dsp563xx_command_handlers[]
Definition: dsp563xx.c:2168
id
unsigned int id
Definition: dsp563xx.c:223
ASM_REG_W_R0
#define ASM_REG_W_R0
Definition: dsp563xx.c:22
dsp563xx_step
static int dsp563xx_step(struct target *target, bool current, target_addr_t address, bool handle_breakpoints)
Definition: dsp563xx.c:1285
ASM_REG_W_LC
#define ASM_REG_W_LC
Definition: dsp563xx.c:73
ASM_REG_W_A1
#define ASM_REG_W_A1
Definition: dsp563xx.c:56
dsp563xx_save_context
static int dsp563xx_save_context(struct target *target)
Definition: dsp563xx.c:830
dsp563xx_get_core_reg
static int dsp563xx_get_core_reg(struct reg *reg)
Definition: dsp563xx.c:398
dsp563xx_restore_context
static int dsp563xx_restore_context(struct target *target)
Definition: dsp563xx.c:843
ASM_REG_W_M6
#define ASM_REG_W_M6
Definition: dsp563xx.c:46
dsp563xx_read_buffer_default
static int dsp563xx_read_buffer_default(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Definition: dsp563xx.c:1672
OBCR_BP_CC_EQUAL
#define OBCR_BP_CC_EQUAL
Definition: dsp563xx.c:100
ASM_REG_W_SC
#define ASM_REG_W_SC
Definition: dsp563xx.c:66
ASM_REG_W_N6
#define ASM_REG_W_N6
Definition: dsp563xx.c:37
ASM_REG_W_B2
#define ASM_REG_W_B2
Definition: dsp563xx.c:61
ASM_REG_W_LA
#define ASM_REG_W_LA
Definition: dsp563xx.c:72
dsp563xx_read_register
static int dsp563xx_read_register(struct target *target, int num, int force)
Definition: dsp563xx.c:730
ASM_REG_W_R6
#define ASM_REG_W_R6
Definition: dsp563xx.c:28
dsp563xx_target
struct target_type dsp563xx_target
Holds methods for DSP563XX targets.
Definition: dsp563xx.c:2246
ASM_REG_W_M1
#define ASM_REG_W_M1
Definition: dsp563xx.c:41
ASM_REG_W_SSL
#define ASM_REG_W_SSL
Definition: dsp563xx.c:71
ASM_REG_W_M3
#define ASM_REG_W_M3
Definition: dsp563xx.c:43
dsp563xx_reg_pc_read
static int dsp563xx_reg_pc_read(struct target *target)
Definition: dsp563xx.c:560
DSP563XX_SR_SA
#define DSP563XX_SR_SA
Definition: dsp563xx.c:939
ASM_REG_W_B0
#define ASM_REG_W_B0
Definition: dsp563xx.c:59
OBCR_BP_ON_READ
#define OBCR_BP_ON_READ
Definition: dsp563xx.c:97
dsp563xx_assert_reset
static int dsp563xx_assert_reset(struct target *target)
Definition: dsp563xx.c:1310
dsp563xx_add_watchpoint
static int dsp563xx_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: dsp563xx.c:1859
ASM_REG_W_R2
#define ASM_REG_W_R2
Definition: dsp563xx.c:24
dsp563xx_target_create
static int dsp563xx_target_create(struct target *target)
Definition: dsp563xx.c:880
dsp563xx_resume
static int dsp563xx_resume(struct target *target, bool current, target_addr_t address, bool handle_breakpoints, bool debug_execution)
Definition: dsp563xx.c:1112
ASM_REG_W_N1
#define ASM_REG_W_N1
Definition: dsp563xx.c:32
INSTR_MOVEP_REG_HIO
#define INSTR_MOVEP_REG_HIO(s, w, d, p)
Definition: dsp563xx.c:321
ASM_REG_W_SZ
#define ASM_REG_W_SZ
Definition: dsp563xx.c:67
DSP563XX_NUMONCEREGS
#define DSP563XX_NUMONCEREGS
Definition: dsp563xx.h:15
BPU_NONE
@ BPU_NONE
Definition: dsp563xx.h:22
BPU_WATCHPOINT
@ BPU_WATCHPOINT
Definition: dsp563xx.h:24
DSP563XX_NUMCOREREGS
#define DSP563XX_NUMCOREREGS
Definition: dsp563xx.h:14
target_to_dsp563xx
static struct dsp563xx_common * target_to_dsp563xx(struct target *target)
Definition: dsp563xx.h:57
dsp563xx_once_execute_sw_ir
int dsp563xx_once_execute_sw_ir(struct jtag_tap *tap, int flush, uint32_t opcode)
single word instruction
Definition: dsp563xx_once.c:240
dsp563xx_once_reg_write
int dsp563xx_once_reg_write(struct jtag_tap *tap, int flush, uint8_t reg, uint32_t data)
once write register
Definition: dsp563xx_once.c:224
dsp563xx_once_execute_dw_ir
int dsp563xx_once_execute_dw_ir(struct jtag_tap *tap, int flush, uint32_t opcode, uint32_t operand)
double word instruction
Definition: dsp563xx_once.c:256
dsp563xx_once_target_status
int dsp563xx_once_target_status(struct jtag_tap *tap)
Definition: dsp563xx_once.c:92
dsp563xx_once_reg_read
int dsp563xx_once_reg_read(struct jtag_tap *tap, int flush, uint8_t reg, uint32_t *data)
once read register
Definition: dsp563xx_once.c:207
dsp563xx_once_read_register
int dsp563xx_once_read_register(struct jtag_tap *tap, int flush, struct once_reg *regs, int len)
once read registers
Definition: dsp563xx_once.c:173
dsp563xx_once_request_debug
int dsp563xx_once_request_debug(struct jtag_tap *tap, int reset_state)
Definition: dsp563xx_once.c:115
dsp563xx_once.h
DSP563XX_ONCE_PDBGOTO
#define DSP563XX_ONCE_PDBGOTO
Definition: dsp563xx_once.h:43
DSP563XX_ONCE_OBCR
#define DSP563XX_ONCE_OBCR
Definition: dsp563xx_once.h:37
DSP563XX_ONCE_OSCR_DEBUG_M
#define DSP563XX_ONCE_OSCR_DEBUG_M
Definition: dsp563xx_once.h:33
DSP563XX_ONCE_OSCR_MBO
#define DSP563XX_ONCE_OSCR_MBO
Definition: dsp563xx_once.h:25
DSP563XX_ONCE_OPABFR
#define DSP563XX_ONCE_OPABFR
Definition: dsp563xx_once.h:46
DSP563XX_ONCE_OPABF11
#define DSP563XX_ONCE_OPABF11
Definition: dsp563xx_once.h:49
DSP563XX_ONCE_OSCR_TME
#define DSP563XX_ONCE_OSCR_TME
Definition: dsp563xx_once.h:28
DSP563XX_ONCE_OPDBR
#define DSP563XX_ONCE_OPDBR
Definition: dsp563xx_once.h:41
DSP563XX_ONCE_OCR_EX
#define DSP563XX_ONCE_OCR_EX
Definition: dsp563xx_once.h:17
DSP563XX_ONCE_OPABEX
#define DSP563XX_ONCE_OPABEX
Definition: dsp563xx_once.h:48
DSP563XX_ONCE_OGDBR
#define DSP563XX_ONCE_OGDBR
Definition: dsp563xx_once.h:40
DSP563XX_ONCE_OSCR_TO
#define DSP563XX_ONCE_OSCR_TO
Definition: dsp563xx_once.h:24
DSP563XX_ONCE_OTC
#define DSP563XX_ONCE_OTC
Definition: dsp563xx_once.h:44
DSP563XX_ONCE_OPILR
#define DSP563XX_ONCE_OPILR
Definition: dsp563xx_once.h:42
DSP563XX_ONCE_OMLR0
#define DSP563XX_ONCE_OMLR0
Definition: dsp563xx_once.h:38
DSP563XX_ONCE_OCR_GO
#define DSP563XX_ONCE_OCR_GO
Definition: dsp563xx_once.h:18
DSP563XX_ONCE_OMLR1
#define DSP563XX_ONCE_OMLR1
Definition: dsp563xx_once.h:39
DSP563XX_ONCE_OPABDR
#define DSP563XX_ONCE_OPABDR
Definition: dsp563xx_once.h:47
DSP563XX_ONCE_OSCR
#define DSP563XX_ONCE_OSCR
Definition: dsp563xx_once.h:35
DSP563XX_ONCE_OSCR_SWO
#define DSP563XX_ONCE_OSCR_SWO
Definition: dsp563xx_once.h:26
DSP563XX_ONCE_OMBC
#define DSP563XX_ONCE_OMBC
Definition: dsp563xx_once.h:36
pattern
uint8_t pattern
Fill pattern.
Definition: dw-spi-helper.h:8
buffer
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
size
uint32_t size
Size of dw_spi_transaction::buffer.
Definition: dw-spi-helper.h:4
address
uint32_t address
Starting address. Sector aligned.
Definition: dw-spi-helper.h:0
direction
static uint16_t direction
Definition: ftdi.c:163
jtag_add_reset
void jtag_add_reset(int req_tlr_or_trst, int req_srst)
A reset of the TAP state machine can be requested.
Definition: jtag/core.c:769
jtag_execute_queue
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
Definition: jtag/core.c:1048
jtag_reset_config
static enum reset_types jtag_reset_config
Definition: jtag/core.c:89
jtag_add_sleep
void jtag_add_sleep(uint32_t us)
Definition: jtag/core.c:881
jtag_get_reset_config
enum reset_types jtag_get_reset_config(void)
Definition: jtag/core.c:1745
reset_types
reset_types
Definition: jtag.h:215
RESET_HAS_SRST
@ RESET_HAS_SRST
Definition: jtag.h:218
RESET_SRST_PULLS_TRST
@ RESET_SRST_PULLS_TRST
Definition: jtag.h:220
LOG_WARNING
#define LOG_WARNING(expr ...)
Definition: log.h:144
LOG_TARGET_ERROR
#define LOG_TARGET_ERROR(target, fmt_str,...)
Definition: log.h:176
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:147
LOG_INFO
#define LOG_INFO(expr ...)
Definition: log.h:141
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:124
ERROR_OK
#define ERROR_OK
Definition: log.h:182
sp
#define sp
Definition: mips32.c:222
register_get_by_name
struct reg * register_get_by_name(struct reg_cache *first, const char *name, bool search_all)
Definition: register.c:50
register_get_last_cache_p
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
Definition: register.c:72
register_cache_invalidate
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
Definition: register.c:94
target
struct target * target
Definition: rtt/rtt.c:26
mem_type
mem_type
Definition: stm8.c:137
breakpoint::address
target_addr_t address
Definition: breakpoints.h:27
command_context
Definition: command.h:52
command_context::interp
Jim_Interp * interp
Definition: command.h:53
command_registration
Definition: command.h:238
command_registration::name
const char * name
Definition: command.h:239
dsp563xx_common
Definition: dsp563xx.h:31
dsp563xx_common::core_regs
uint32_t core_regs[DSP563XX_NUMCOREREGS]
Definition: dsp563xx.h:34
dsp563xx_common::read_core_reg
int(* read_core_reg)(struct target *target, int num)
Definition: dsp563xx.h:38
dsp563xx_common::hardware_breakpoints_cleared
bool hardware_breakpoints_cleared
Definition: dsp563xx.h:44
dsp563xx_common::jtag_info
struct mcu_jtag jtag_info
Definition: dsp563xx.h:32
dsp563xx_common::hardware_breakpoint
struct hardware_breakpoint hardware_breakpoint[1]
Definition: dsp563xx.h:41
dsp563xx_common::write_core_reg
int(* write_core_reg)(struct target *target, int num)
Definition: dsp563xx.h:39
dsp563xx_common::core_cache
struct reg_cache * core_cache
Definition: dsp563xx.h:33
dsp563xx_core_reg
Definition: dsp563xx.h:47
dsp563xx_core_reg::instr_mask
uint32_t instr_mask
Definition: dsp563xx.h:52
dsp563xx_core_reg::size
uint32_t size
Definition: dsp563xx.h:50
dsp563xx_core_reg::dsp563xx_common
struct dsp563xx_common * dsp563xx_common
Definition: dsp563xx.h:54
dsp563xx_core_reg::target
struct target * target
Definition: dsp563xx.h:53
dsp563xx_core_reg::num
uint32_t num
Definition: dsp563xx.h:48
dsp563xx_core_reg::eame
uint8_t eame
Definition: dsp563xx.h:51
dsp563xx_core_reg::name
const char * name
Definition: dsp563xx.h:49
hardware_breakpoint::used
enum breakpoint_usage used
Definition: dsp563xx.h:28
jtag_tap::has_idcode
bool has_idcode
not all devices have idcode, we'll discover this during chain examination
Definition: jtag.h:118
jtag_tap::idcode
uint32_t idcode
device identification code
Definition: jtag.h:115
mcu_jtag::tap
struct jtag_tap * tap
Definition: avrt.h:14
mem_param
Definition: algorithm.h:20
once_reg
Definition: dsp563xx_once.h:52
once_reg::name
const char * name
Definition: dsp563xx_once.h:56
once_reg::reg
uint32_t reg
Definition: dsp563xx_once.h:57
reg_arch_type
Definition: register.h:151
reg_arch_type::get
int(* get)(struct reg *reg)
Definition: register.h:152
reg_cache
Definition: register.h:144
reg_cache::name
const char * name
Definition: register.h:145
reg_cache::num_regs
unsigned int num_regs
Definition: register.h:148
reg_cache::reg_list
struct reg * reg_list
Definition: register.h:147
reg_cache::next
struct reg_cache * next
Definition: register.h:146
reg_param
Definition: algorithm.h:27
reg_param::size
uint32_t size
Definition: algorithm.h:29
reg_param::reg_name
const char * reg_name
Definition: algorithm.h:28
reg
Definition: register.h:111
reg::valid
bool valid
Definition: register.h:126
reg::exist
bool exist
Definition: register.h:128
reg::size
uint32_t size
Definition: register.h:132
reg::value
uint8_t * value
Definition: register.h:122
reg::arch_info
void * arch_info
Definition: register.h:140
reg::dirty
bool dirty
Definition: register.h:124
reg::type
const struct reg_arch_type * type
Definition: register.h:141
reg::name
const char * name
Definition: register.h:113
target_type
This holds methods shared between all instances of a given target type.
Definition: target_type.h:26
target_type::name
const char * name
Name of this type of target.
Definition: target_type.h:31
target
Definition: target.h:119
target::tap
struct jtag_tap * tap
Definition: target.h:122
target::debug_reason
enum target_debug_reason debug_reason
Definition: target.h:164
target::state
enum target_state state
Definition: target.h:167
target::reg_cache
struct reg_cache * reg_cache
Definition: target.h:168
target::arch_info
void * arch_info
Definition: target.h:174
target::reset_halt
bool reset_halt
Definition: target.h:154
target_call_event_callbacks
int target_call_event_callbacks(struct target *target, enum target_event event)
Definition: target.c:1791
target_halt
int target_halt(struct target *target)
Definition: target.c:516
target_buffer_set_u32
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
Definition: target.c:361
target_write_buffer
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2368
target_read_buffer
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Definition: target.c:2433
target_state_name
const char * target_state_name(const struct target *t)
Return the name of this targets current state.
Definition: target.c:269
target_resume
int target_resume(struct target *target, bool current, target_addr_t address, bool handle_breakpoints, bool debug_execution)
Make the target (re)start executing using its saved execution context (possibly with some modificatio...
Definition: target.c:565
target_wait_state
int target_wait_state(struct target *target, enum target_state state, unsigned int ms)
Definition: target.c:3173
get_current_target
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:467
target_buffer_get_u32
uint32_t target_buffer_get_u32(struct target *target, const uint8_t *buffer)
Definition: target.c:325
target_handle_md_output
void target_handle_md_output(struct command_invocation *cmd, struct target *target, target_addr_t address, unsigned int size, unsigned int count, const uint8_t *buffer, bool include_address)
Definition: target.c:3303
DBG_REASON_DBGRQ
@ DBG_REASON_DBGRQ
Definition: target.h:72
DBG_REASON_SINGLESTEP
@ DBG_REASON_SINGLESTEP
Definition: target.h:76
target_register_class
target_register_class
Definition: target.h:113
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:814
target_was_examined
static bool target_was_examined(const struct target *target)
Definition: target.h:440
ERROR_TARGET_INVALID
#define ERROR_TARGET_INVALID
Definition: target.h:811
TARGET_EVENT_DEBUG_RESUMED
@ TARGET_EVENT_DEBUG_RESUMED
Definition: target.h:282
TARGET_EVENT_HALTED
@ TARGET_EVENT_HALTED
Definition: target.h:262
TARGET_EVENT_DEBUG_HALTED
@ TARGET_EVENT_DEBUG_HALTED
Definition: target.h:281
TARGET_RESET
@ TARGET_RESET
Definition: target.h:59
TARGET_UNKNOWN
@ TARGET_UNKNOWN
Definition: target.h:56
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:58
TARGET_RUNNING
@ TARGET_RUNNING
Definition: target.h:57
ERROR_TARGET_RESOURCE_NOT_AVAILABLE
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:818
ERROR_TARGET_FAILURE
#define ERROR_TARGET_FAILURE
Definition: target.h:815
target_type.h
target_addr_t
uint64_t target_addr_t
Definition: types.h:279
TARGET_PRIXADDR
#define TARGET_PRIXADDR
Definition: types.h:285
TARGET_PRIxADDR
#define TARGET_PRIxADDR
Definition: types.h:284
NULL
#define NULL
Definition: usb.h:16
state
uint8_t state[4]
Definition: vdebug.c:21
count
uint8_t count[4]
Definition: vdebug.c:22
read_mem
static int read_mem(struct target *t, uint32_t size, uint32_t addr, uint8_t *buf)
Definition: x86_32_common.c:320