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armv7a.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2009 by David Brownell *
5  * *
6  * Copyright (C) ST-Ericsson SA 2011 michel.jaouen@stericsson.com *
7  ***************************************************************************/
8 
9 #ifdef HAVE_CONFIG_H
10 #include "config.h"
11 #endif
12 
13 #include <helper/replacements.h>
14 
15 #include "armv7a.h"
16 #include "armv7a_mmu.h"
17 #include "arm_disassembler.h"
18 
19 #include "register.h"
20 #include <helper/binarybuffer.h>
21 #include <helper/command.h>
22 
23 #include <stdlib.h>
24 #include <string.h>
25 #include <unistd.h>
26 
27 #include "arm_opcodes.h"
28 #include "target.h"
29 #include "target_type.h"
30 #include "smp.h"
31 
33 {
34  uint32_t dfsr, ifsr, dfar, ifar;
35  struct armv7a_common *armv7a = target_to_armv7a(target);
36  struct arm_dpm *dpm = armv7a->arm.dpm;
37  int retval;
38 
39  retval = dpm->prepare(dpm);
40  if (retval != ERROR_OK)
41  return;
42 
43  /* ARMV4_5_MRC(cpnum, op1, r0, crn, crm, op2) */
44 
45  /* c5/c0 - {data, instruction} fault status registers */
46  retval = dpm->instr_read_data_r0(dpm,
47  ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
48  &dfsr);
49  if (retval != ERROR_OK)
50  goto done;
51 
52  retval = dpm->instr_read_data_r0(dpm,
53  ARMV4_5_MRC(15, 0, 0, 5, 0, 1),
54  &ifsr);
55  if (retval != ERROR_OK)
56  goto done;
57 
58  /* c6/c0 - {data, instruction} fault address registers */
59  retval = dpm->instr_read_data_r0(dpm,
60  ARMV4_5_MRC(15, 0, 0, 6, 0, 0),
61  &dfar);
62  if (retval != ERROR_OK)
63  goto done;
64 
65  retval = dpm->instr_read_data_r0(dpm,
66  ARMV4_5_MRC(15, 0, 0, 6, 0, 2),
67  &ifar);
68  if (retval != ERROR_OK)
69  goto done;
70 
71  LOG_TARGET_USER(target, "Data fault registers DFSR: %8.8" PRIx32
72  ", DFAR: %8.8" PRIx32, dfsr, dfar);
73  LOG_TARGET_USER(target, "Instruction fault registers IFSR: %8.8" PRIx32
74  ", IFAR: %8.8" PRIx32, ifsr, ifar);
75 
76 done:
77  dpm->finish(dpm);
78 }
79 
80 
81 /* retrieve main id register */
82 static int armv7a_read_midr(struct target *target)
83 {
84  int retval = ERROR_FAIL;
85  struct armv7a_common *armv7a = target_to_armv7a(target);
86  struct arm_dpm *dpm = armv7a->arm.dpm;
87  uint32_t midr;
88  retval = dpm->prepare(dpm);
89  if (retval != ERROR_OK)
90  goto done;
91  /* MRC p15,0,<Rd>,c0,c0,0; read main id register*/
92 
93  retval = dpm->instr_read_data_r0(dpm,
94  ARMV4_5_MRC(15, 0, 0, 0, 0, 0),
95  &midr);
96  if (retval != ERROR_OK)
97  goto done;
98 
99  armv7a->rev = (midr & 0xf);
100  armv7a->partnum = (midr >> 4) & 0xfff;
101  armv7a->arch = (midr >> 16) & 0xf;
102  armv7a->variant = (midr >> 20) & 0xf;
103  armv7a->implementor = (midr >> 24) & 0xff;
105  "rev %" PRIx32 ", partnum %" PRIx32 ", arch %" PRIx32
106  ", variant %" PRIx32 ", implementor %" PRIx32,
107  armv7a->rev,
108  armv7a->partnum,
109  armv7a->arch,
110  armv7a->variant,
111  armv7a->implementor);
112 
113 done:
114  dpm->finish(dpm);
115  return retval;
116 }
117 
119 {
120  struct armv7a_common *armv7a = target_to_armv7a(target);
121  struct arm_dpm *dpm = armv7a->arm.dpm;
122  uint32_t ttbcr, ttbcr_n;
123  int ttbidx;
124  int retval;
125 
126  retval = dpm->prepare(dpm);
127  if (retval != ERROR_OK)
128  goto done;
129 
130  /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
131  retval = dpm->instr_read_data_r0(dpm,
132  ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
133  &ttbcr);
134  if (retval != ERROR_OK)
135  goto done;
136 
137  LOG_TARGET_DEBUG(target, "ttbcr %" PRIx32, ttbcr);
138 
139  ttbcr_n = ttbcr & 0x7;
140  armv7a->armv7a_mmu.ttbcr = ttbcr;
141  armv7a->armv7a_mmu.cached = 1;
142 
143  for (ttbidx = 0; ttbidx < 2; ttbidx++) {
144  /* MRC p15,0,<Rt>,c2,c0,ttbidx */
145  retval = dpm->instr_read_data_r0(dpm,
146  ARMV4_5_MRC(15, 0, 0, 2, 0, ttbidx),
147  &armv7a->armv7a_mmu.ttbr[ttbidx]);
148  if (retval != ERROR_OK)
149  goto done;
150  }
151 
152  /*
153  * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
154  * document # ARM DDI 0406C
155  */
156  armv7a->armv7a_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n;
157  armv7a->armv7a_mmu.ttbr_range[1] = 0xffffffff;
158  armv7a->armv7a_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
159  armv7a->armv7a_mmu.ttbr_mask[1] = 0xffffffff << 14;
160  armv7a->armv7a_mmu.cached = 1;
161 
162  retval = armv7a_read_midr(target);
163  if (retval != ERROR_OK)
164  goto done;
165 
166  /* FIXME: why this special case based on part number? */
167  if ((armv7a->partnum & 0xf) == 0) {
168  /* ARM DDI 0344H , ARM DDI 0407F */
169  armv7a->armv7a_mmu.ttbr_mask[0] = 7 << (32 - ttbcr_n);
170  }
171 
172  LOG_TARGET_DEBUG(target, "ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
173  (ttbcr_n != 0) ? "used" : "not used",
174  armv7a->armv7a_mmu.ttbr_mask[0],
175  armv7a->armv7a_mmu.ttbr_mask[1]);
176 
177 done:
178  dpm->finish(dpm);
179  return retval;
180 }
181 
183  struct armv7a_cache_common *armv7a_cache)
184 {
185  struct armv7a_l2x_cache *l2x_cache = armv7a_cache->outer_cache;
186 
187  int cl;
188 
189  if (armv7a_cache->info == -1) {
190  command_print(cmd, "cache not yet identified");
191  return ERROR_OK;
192  }
193 
194  for (cl = 0; cl < armv7a_cache->loc; cl++) {
195  struct armv7a_arch_cache *arch = &(armv7a_cache->arch[cl]);
196 
197  if (arch->ctype & 1) {
199  "L%d I-Cache: linelen %" PRIu32
200  ", associativity %" PRIu32
201  ", nsets %" PRIu32
202  ", cachesize %" PRIu32 " KBytes",
203  cl+1,
204  arch->i_size.linelen,
205  arch->i_size.associativity,
206  arch->i_size.nsets,
207  arch->i_size.cachesize);
208  }
209 
210  if (arch->ctype >= 2) {
212  "L%d D-Cache: linelen %" PRIu32
213  ", associativity %" PRIu32
214  ", nsets %" PRIu32
215  ", cachesize %" PRIu32 " KBytes",
216  cl+1,
217  arch->d_u_size.linelen,
218  arch->d_u_size.associativity,
219  arch->d_u_size.nsets,
220  arch->d_u_size.cachesize);
221  }
222  }
223 
224  if (l2x_cache)
225  command_print(cmd, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRIu32 " ways",
226  l2x_cache->base, l2x_cache->way);
227 
228  return ERROR_OK;
229 }
230 
231 /* retrieve core id cluster id */
232 static int armv7a_read_mpidr(struct target *target)
233 {
234  int retval = ERROR_FAIL;
235  struct armv7a_common *armv7a = target_to_armv7a(target);
236  struct arm_dpm *dpm = armv7a->arm.dpm;
237  uint32_t mpidr;
238  retval = dpm->prepare(dpm);
239  if (retval != ERROR_OK)
240  goto done;
241  /* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/
242 
243  retval = dpm->instr_read_data_r0(dpm,
244  ARMV4_5_MRC(15, 0, 0, 0, 0, 5),
245  &mpidr);
246  if (retval != ERROR_OK)
247  goto done;
248 
249  /* Is register in Multiprocessing Extensions register format? */
250  if (mpidr & MPIDR_MP_EXT) {
251  LOG_TARGET_DEBUG(target, "%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
252  armv7a->multi_processor_system = (mpidr >> 30) & 1;
253  armv7a->multi_threading_processor = (mpidr >> 24) & 1;
254  armv7a->level2_id = (mpidr >> 16) & 0xf;
255  armv7a->cluster_id = (mpidr >> 8) & 0xf;
256  armv7a->cpu_id = mpidr & 0xf;
257  LOG_TARGET_INFO(target, "MPIDR level2 %x, cluster %x, core %x, %s, %s",
258  armv7a->level2_id,
259  armv7a->cluster_id,
260  armv7a->cpu_id,
261  armv7a->multi_processor_system == 0 ? "multi core" : "mono core",
262  armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT");
263 
264  } else
265  LOG_TARGET_DEBUG(target, "MPIDR not in multiprocessor format");
266 
267 done:
268  dpm->finish(dpm);
269  return retval;
270 
271 
272 }
273 
274 static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
275 {
276  int retval = ERROR_OK;
277 
278  /* select cache level */
279  retval = dpm->instr_write_data_r0(dpm,
280  ARMV4_5_MCR(15, 2, 0, 0, 0, 0),
281  (cl << 1) | (ct == 1 ? 1 : 0));
282  if (retval != ERROR_OK)
283  goto done;
284 
285  retval = dpm->instr_read_data_r0(dpm,
286  ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
287  cache_reg);
288  done:
289  return retval;
290 }
291 
292 static struct armv7a_cachesize decode_cache_reg(uint32_t cache_reg)
293 {
294  struct armv7a_cachesize size;
295  int i = 0;
296 
297  size.linelen = 16 << (cache_reg & 0x7);
298  size.associativity = ((cache_reg >> 3) & 0x3ff) + 1;
299  size.nsets = ((cache_reg >> 13) & 0x7fff) + 1;
300  size.cachesize = size.linelen * size.associativity * size.nsets / 1024;
301 
302  /* compute info for set way operation on cache */
303  size.index_shift = (cache_reg & 0x7) + 4;
304  size.index = (cache_reg >> 13) & 0x7fff;
305  size.way = ((cache_reg >> 3) & 0x3ff);
306 
307  while (((size.way << i) & 0x80000000) == 0)
308  i++;
309  size.way_shift = i;
310 
311  return size;
312 }
313 
315 {
316  /* read cache descriptor */
317  int retval = ERROR_FAIL;
318  struct armv7a_common *armv7a = target_to_armv7a(target);
319  struct arm_dpm *dpm = armv7a->arm.dpm;
320  uint32_t csselr, clidr, ctr;
321  uint32_t cache_reg;
322  int cl, ctype;
323  struct armv7a_cache_common *cache =
324  &(armv7a->armv7a_mmu.armv7a_cache);
325 
326  retval = dpm->prepare(dpm);
327  if (retval != ERROR_OK)
328  goto done;
329 
330  /* retrieve CTR
331  * mrc p15, 0, r0, c0, c0, 1 @ read ctr */
332  retval = dpm->instr_read_data_r0(dpm,
333  ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
334  &ctr);
335  if (retval != ERROR_OK)
336  goto done;
337 
338  cache->iminline = 4UL << (ctr & 0xf);
339  cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
340  LOG_TARGET_DEBUG(target, "ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
341  ctr, cache->iminline, cache->dminline);
342 
343  /* retrieve CLIDR
344  * mrc p15, 1, r0, c0, c0, 1 @ read clidr */
345  retval = dpm->instr_read_data_r0(dpm,
346  ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
347  &clidr);
348  if (retval != ERROR_OK)
349  goto done;
350 
351  cache->loc = (clidr & 0x7000000) >> 24;
352  LOG_TARGET_DEBUG(target, "Number of cache levels to PoC %" PRId32, cache->loc);
353 
354  /* retrieve selected cache for later restore
355  * MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
356  retval = dpm->instr_read_data_r0(dpm,
357  ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
358  &csselr);
359  if (retval != ERROR_OK)
360  goto done;
361 
362  /* retrieve all available inner caches */
363  for (cl = 0; cl < cache->loc; clidr >>= 3, cl++) {
364 
365  /* isolate cache type at current level */
366  ctype = clidr & 7;
367 
368  /* skip reserved values */
369  if (ctype > CACHE_LEVEL_HAS_UNIFIED_CACHE)
370  continue;
371 
372  /* separate d or unified d/i cache at this level ? */
374  /* retrieve d-cache info */
375  retval = get_cache_info(dpm, cl, 0, &cache_reg);
376  if (retval != ERROR_OK)
377  goto done;
378  cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
379 
380  LOG_TARGET_DEBUG(target, "data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
381  cache->arch[cl].d_u_size.index,
382  cache->arch[cl].d_u_size.index_shift,
383  cache->arch[cl].d_u_size.way,
384  cache->arch[cl].d_u_size.way_shift);
385 
386  LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
387  cache->arch[cl].d_u_size.linelen,
388  cache->arch[cl].d_u_size.cachesize,
389  cache->arch[cl].d_u_size.associativity);
390  }
391 
392  /* separate i-cache at this level ? */
393  if (ctype & CACHE_LEVEL_HAS_I_CACHE) {
394  /* retrieve i-cache info */
395  retval = get_cache_info(dpm, cl, 1, &cache_reg);
396  if (retval != ERROR_OK)
397  goto done;
398  cache->arch[cl].i_size = decode_cache_reg(cache_reg);
399 
400  LOG_TARGET_DEBUG(target, "instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
401  cache->arch[cl].i_size.index,
402  cache->arch[cl].i_size.index_shift,
403  cache->arch[cl].i_size.way,
404  cache->arch[cl].i_size.way_shift);
405 
406  LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
407  cache->arch[cl].i_size.linelen,
408  cache->arch[cl].i_size.cachesize,
409  cache->arch[cl].i_size.associativity);
410  }
411 
412  cache->arch[cl].ctype = ctype;
413  }
414 
415  /* restore selected cache */
416  dpm->instr_write_data_r0(dpm,
417  ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
418  csselr);
419 
420  if (retval != ERROR_OK)
421  goto done;
422 
423  /* if no l2 cache initialize l1 data cache flush function function */
427  }
428 
429  armv7a->armv7a_mmu.armv7a_cache.info = 1;
430 done:
431  dpm->finish(dpm);
433  return retval;
434 
435 }
436 
437 static int armv7a_setup_semihosting(struct target *target, int enable)
438 {
439  struct armv7a_common *armv7a = target_to_armv7a(target);
440  uint32_t vcr;
441  int ret;
442 
443  ret = mem_ap_read_atomic_u32(armv7a->debug_ap,
444  armv7a->debug_base + CPUDBG_VCR,
445  &vcr);
446  if (ret < 0) {
447  LOG_TARGET_ERROR(target, "Failed to read VCR register");
448  return ret;
449  }
450 
451  if (enable)
452  vcr |= DBG_VCR_SVC_MASK;
453  else
454  vcr &= ~DBG_VCR_SVC_MASK;
455 
456  ret = mem_ap_write_atomic_u32(armv7a->debug_ap,
457  armv7a->debug_base + CPUDBG_VCR,
458  vcr);
459  if (ret < 0)
460  LOG_TARGET_ERROR(target, "Failed to write VCR register");
461 
462  return ret;
463 }
464 
465 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
466 {
467  struct arm *arm = &armv7a->arm;
468  arm->arch_info = armv7a;
469  target->arch_info = &armv7a->arm;
471  /* target is useful in all function arm v4 5 compatible */
472  armv7a->arm.target = target;
475  armv7a->armv7a_mmu.armv7a_cache.info = -1;
478  return ERROR_OK;
479 }
480 
482 {
483  static const char *state[] = {
484  "disabled", "enabled"
485  };
486 
487  struct armv7a_common *armv7a = target_to_armv7a(target);
488  struct arm *arm = &armv7a->arm;
489 
490  if (armv7a->common_magic != ARMV7_COMMON_MAGIC) {
491  LOG_TARGET_ERROR(target, "BUG: called for a non-ARMv7A target");
493  }
494 
496 
497  if (armv7a->is_armv7r) {
498  LOG_TARGET_USER(target, "D-Cache: %s, I-Cache: %s",
501  } else {
502  LOG_TARGET_USER(target, "MMU: %s, D-Cache: %s, I-Cache: %s",
503  state[armv7a->armv7a_mmu.mmu_enabled],
506  }
507 
508  if (arm->core_mode == ARM_MODE_ABT)
510 
511  return ERROR_OK;
512 }
513 
515  {
517  },
519 };
int arm_arch_state(struct target *target)
Definition: armv4_5.c:796
#define ARM_COMMON_MAGIC
Definition: arm.h:166
@ ARM_MODE_ABT
Definition: arm.h:88
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
Definition: arm_adi_v5.c:274
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
Definition: arm_adi_v5.c:326
Macros used to generate various ARM or Thumb opcodes.
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:186
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:209
int armv7a_handle_cache_info_command(struct command_invocation *cmd, struct armv7a_cache_common *armv7a_cache)
Definition: armv7a.c:182
int armv7a_read_ttbcr(struct target *target)
Definition: armv7a.c:118
int armv7a_arch_state(struct target *target)
Definition: armv7a.c:481
static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
Definition: armv7a.c:274
static struct armv7a_cachesize decode_cache_reg(uint32_t cache_reg)
Definition: armv7a.c:292
const struct command_registration armv7a_command_handlers[]
Definition: armv7a.c:514
static void armv7a_show_fault_registers(struct target *target)
Definition: armv7a.c:32
static int armv7a_read_mpidr(struct target *target)
Definition: armv7a.c:232
int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
Definition: armv7a.c:465
static int armv7a_read_midr(struct target *target)
Definition: armv7a.c:82
static int armv7a_setup_semihosting(struct target *target, int enable)
Definition: armv7a.c:437
int armv7a_identify_cache(struct target *target)
Definition: armv7a.c:314
#define ARMV7_COMMON_MAGIC
Definition: armv7a.h:22
#define CPUDBG_VCR
Definition: armv7a.h:154
#define DBG_VCR_SVC_MASK
Definition: armv7a.h:177
static struct armv7a_common * target_to_armv7a(struct target *target)
Definition: armv7a.h:120
#define MPIDR_MP_EXT
Definition: armv7a.h:180
int armv7a_cache_flush_all_data(struct target *target)
Definition: armv7a_cache.c:121
const struct command_registration arm7a_cache_command_handlers[]
Definition: armv7a_cache.c:556
#define CACHE_LEVEL_HAS_UNIFIED_CACHE
Definition: armv7a_cache.h:29
#define CACHE_LEVEL_HAS_I_CACHE
Definition: armv7a_cache.h:31
#define CACHE_LEVEL_HAS_D_CACHE
Definition: armv7a_cache.h:30
Support functions to access arbitrary bits in a byte array.
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:375
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:400
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:251
uint32_t size
Size of dw_spi_transaction::buffer.
Definition: dw-spi-helper.h:4
#define LOG_TARGET_INFO(target, fmt_str,...)
Definition: log.h:153
#define LOG_TARGET_USER(target, fmt_str,...)
Definition: log.h:156
#define ERROR_FAIL
Definition: log.h:174
#define LOG_TARGET_ERROR(target, fmt_str,...)
Definition: log.h:162
#define LOG_TARGET_DEBUG(target, fmt_str,...)
Definition: log.h:150
#define ERROR_OK
Definition: log.h:168
struct target * target
Definition: rtt/rtt.c:26
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:72
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
Definition: arm_dpm.h:57
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
Definition: arm_dpm.h:54
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
Definition: arm_dpm.h:98
Represents a generic ARM core, with standard application registers.
Definition: arm.h:175
void * arch_info
Definition: arm.h:251
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
Definition: arm.h:196
int(* setup_semihosting)(struct target *target, int enable)
Definition: arm.h:207
struct arm_dpm * dpm
Handle for the debug module, if one is present.
Definition: arm.h:213
unsigned int common_magic
Definition: arm.h:176
struct target * target
Backpointer to the target.
Definition: arm.h:210
struct armv7a_cachesize i_size
Definition: armv7a.h:56
struct armv7a_cachesize d_u_size
Definition: armv7a.h:55
int(* flush_all_data_cache)(struct target *target)
Definition: armv7a.h:70
struct armv7a_l2x_cache * outer_cache
Definition: armv7a.h:69
uint32_t dminline
Definition: armv7a.h:63
struct armv7a_arch_cache arch[6]
Definition: armv7a.h:65
uint32_t iminline
Definition: armv7a.h:64
int d_u_cache_enabled
Definition: armv7a.h:67
uint32_t linelen
Definition: armv7a.h:41
uint32_t way
Definition: armv7a.h:48
uint32_t index
Definition: armv7a.h:46
uint32_t index_shift
Definition: armv7a.h:47
uint32_t way_shift
Definition: armv7a.h:49
uint32_t nsets
Definition: armv7a.h:43
uint32_t associativity
Definition: armv7a.h:42
uint32_t cachesize
Definition: armv7a.h:44
bool is_armv7r
Definition: armv7a.h:103
uint32_t arch
Definition: armv7a.h:106
uint8_t cpu_id
Definition: armv7a.h:102
uint8_t multi_threading_processor
Definition: armv7a.h:99
uint8_t multi_processor_system
Definition: armv7a.h:98
uint8_t level2_id
Definition: armv7a.h:100
target_addr_t debug_base
Definition: armv7a.h:95
uint32_t rev
Definition: armv7a.h:104
uint32_t variant
Definition: armv7a.h:107
struct arm arm
Definition: armv7a.h:90
struct armv7a_mmu_common armv7a_mmu
Definition: armv7a.h:111
struct adiv5_ap * debug_ap
Definition: armv7a.h:96
uint8_t cluster_id
Definition: armv7a.h:101
uint32_t partnum
Definition: armv7a.h:105
uint32_t implementor
Definition: armv7a.h:108
unsigned int common_magic
Definition: armv7a.h:88
uint32_t base
Definition: armv7a.h:35
uint32_t way
Definition: armv7a.h:36
uint32_t ttbr_range[2]
Definition: armv7a.h:79
struct armv7a_cache_common armv7a_cache
Definition: armv7a.h:83
int32_t cached
Definition: armv7a.h:75
uint32_t ttbr[2]
Definition: armv7a.h:77
uint32_t ttbr_mask[2]
Definition: armv7a.h:78
uint32_t ttbcr
Definition: armv7a.h:76
uint32_t mmu_enabled
Definition: armv7a.h:84
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
Definition: command.h:247
Definition: target.h:119
void * arch_info
Definition: target.h:167
static const char * target_name(const struct target *target)
Returns the instance-specific name of the specified target.
Definition: target.h:236
#define NULL
Definition: usb.h:16
uint8_t cmd
Definition: vdebug.c:1
uint8_t state[4]
Definition: vdebug.c:21