OpenOCD
stm32l4x.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2015 by Uwe Bonnes *
5  * bon@elektron.ikp.physik.tu-darmstadt.de *
6  * *
7  * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
8  * tarek.bouchkati@gmail.com *
9  ***************************************************************************/
10 
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14 
15 #include "imp.h"
16 #include <helper/align.h>
17 #include <helper/binarybuffer.h>
18 #include <helper/bits.h>
19 #include <target/algorithm.h>
20 #include <target/arm_adi_v5.h>
21 #include <target/cortex_m.h>
22 #include "stm32l4x.h"
23 
24 /* STM32L4xxx series for reference.
25  *
26  * RM0351 (STM32L4x5/STM32L4x6)
27  * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
28  *
29  * RM0394 (STM32L43x/44x/45x/46x)
30  * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
31  *
32  * RM0432 (STM32L4R/4Sxx)
33  * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
34  *
35  * STM32L476RG Datasheet (for erase timing)
36  * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
37  *
38  * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
39  * an option byte is available to map all sectors to the first bank.
40  * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
41  * handlers do!
42  *
43  * RM0394 devices have a single bank only.
44  *
45  * RM0432 devices have single and dual bank operating modes.
46  * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
47  * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
48  * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
49  *
50  * Bank mode is controlled by two different bits in option bytes register.
51  * - for STM32L4R/Sxx
52  * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
53  * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
54  * - for STM32L4P5/Q5x
55  * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
56  * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
57  */
58 
59 /* STM32WBxxx series for reference.
60  *
61  * RM0493 (STM32WBA52x)
62  * http://www.st.com/resource/en/reference_manual/dm00821869.pdf
63  *
64  * RM0434 (STM32WB55/WB35x)
65  * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
66  *
67  * RM0471 (STM32WB50/WB30x)
68  * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
69  *
70  * RM0473 (STM32WB15x)
71  * http://www.st.com/resource/en/reference_manual/dm00649196.pdf
72  *
73  * RM0478 (STM32WB10x)
74  * http://www.st.com/resource/en/reference_manual/dm00689203.pdf
75  */
76 
77 /* STM32WLxxx series for reference.
78  *
79  * RM0461 (STM32WLEx)
80  * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
81  *
82  * RM0453 (STM32WL5x)
83  * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
84  */
85 
86 /* STM32C0xxx series for reference.
87  *
88  * RM0490 (STM32C0x1)
89  * http://www.st.com/resource/en/reference_manual/dm00781702.pdf
90  */
91 
92 /* STM32G0xxx series for reference.
93  *
94  * RM0444 (STM32G0x1)
95  * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
96  *
97  * RM0454 (STM32G0x0)
98  * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
99  */
100 
101 /* STM32G4xxx series for reference.
102  *
103  * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
104  * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
105  *
106  * Cat. 2 devices have single bank only, page size is 2kByte.
107  *
108  * Cat. 3 devices have single and dual bank operating modes,
109  * Page size is 2kByte (dual mode) or 4kByte (single mode).
110  *
111  * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
112  * Both banks are treated as a single OpenOCD bank.
113  *
114  * Cat. 4 devices have single bank only, page size is 2kByte.
115  */
116 
117 /* STM32L5xxx series for reference.
118  *
119  * RM0428 (STM32L552xx/STM32L562xx)
120  * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
121  */
122 
123 /* STM32U0xxx series for reference.
124  *
125  * RM0503 (STM32U0xx)
126  * https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
127  */
128 
129 /* STM32U5xxx series for reference.
130  *
131  * RM0456 (STM32U5xx)
132  * http://www.st.com/resource/en/reference_manual/dm00477635.pdf
133  */
134 
135 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
136 
137 #define FLASH_ERASE_TIMEOUT 250
138 #define FLASH_WRITE_TIMEOUT 50
139 
140 
141 /* relevant STM32L4 flags ****************************************************/
142 #define F_NONE 0
143 /* this flag indicates if the device flash is with dual bank architecture */
144 #define F_HAS_DUAL_BANK BIT(0)
145 /* this flags is used for dual bank devices only, it indicates if the
146  * 4 WRPxx are usable if the device is configured in single-bank mode */
147 #define F_USE_ALL_WRPXX BIT(1)
148 /* this flag indicates if the device embeds a TrustZone security feature */
149 #define F_HAS_TZ BIT(2)
150 /* this flag indicates if the device has the same flash registers as STM32L5 */
151 #define F_HAS_L5_FLASH_REGS BIT(3)
152 /* this flag indicates that programming should be done in quad-word
153  * the default programming word size is double-word */
154 #define F_QUAD_WORD_PROG BIT(4)
155 /* the registers WRPxyR have UNLOCK bit - writing zero locks the write
156  * protection region permanently! */
157 #define F_WRP_HAS_LOCK BIT(5)
158 /* end of STM32L4 flags ******************************************************/
159 
160 
167  /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
168  * so it uses the C2CR for flash operations and CR for checking locks and locking */
169  STM32_FLASH_CR_WLK_INDEX, /* FLASH_CR_WITH_LOCK */
176 };
177 
179  RDP_LEVEL_0 = 0xAA,
180  RDP_LEVEL_0_5 = 0x55, /* for devices with TrustZone enabled */
181  RDP_LEVEL_1 = 0x00,
182  RDP_LEVEL_2 = 0xCC
183 };
184 
186  [STM32_FLASH_ACR_INDEX] = 0x000,
187  [STM32_FLASH_KEYR_INDEX] = 0x008,
188  [STM32_FLASH_OPTKEYR_INDEX] = 0x00C,
189  [STM32_FLASH_SR_INDEX] = 0x010,
190  [STM32_FLASH_CR_INDEX] = 0x014,
191  [STM32_FLASH_OPTR_INDEX] = 0x020,
192  [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
193  [STM32_FLASH_WRP1BR_INDEX] = 0x030,
194  [STM32_FLASH_WRP2AR_INDEX] = 0x04C,
195  [STM32_FLASH_WRP2BR_INDEX] = 0x050,
196 };
197 
199  [STM32_FLASH_ACR_INDEX] = 0x000,
200  [STM32_FLASH_KEYR_INDEX] = 0x008,
201  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
202  [STM32_FLASH_SR_INDEX] = 0x060,
203  [STM32_FLASH_CR_INDEX] = 0x064,
204  [STM32_FLASH_CR_WLK_INDEX] = 0x014,
205  [STM32_FLASH_OPTR_INDEX] = 0x020,
206  [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
207  [STM32_FLASH_WRP1BR_INDEX] = 0x030,
208 };
209 
211  [STM32_FLASH_ACR_INDEX] = 0x000,
212  [STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
213  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
214  [STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */
215  [STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */
216  [STM32_FLASH_OPTR_INDEX] = 0x040,
217  [STM32_FLASH_WRP1AR_INDEX] = 0x058,
218  [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
219  [STM32_FLASH_WRP2AR_INDEX] = 0x068,
220  [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
221 };
222 
224  [STM32_FLASH_ACR_INDEX] = 0x000,
225  [STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */
226  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
227  [STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */
228  [STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */
229  [STM32_FLASH_OPTR_INDEX] = 0x040,
230  [STM32_FLASH_WRP1AR_INDEX] = 0x058,
231  [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
232  [STM32_FLASH_WRP2AR_INDEX] = 0x068,
233  [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
234 };
235 
236 struct stm32l4_rev {
237  const uint16_t rev;
238  const char *str;
239 };
240 
242  uint16_t id;
243  const char *device_str;
244  const struct stm32l4_rev *revs;
245  const size_t num_revs;
246  const uint16_t max_flash_size_kb;
247  const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
248  const uint32_t flash_regs_base;
249  const uint32_t fsize_addr;
250  const uint32_t otp_base;
251  const uint32_t otp_size;
252 };
253 
255  bool probed;
256  uint32_t idcode;
257  unsigned int bank1_sectors;
260  uint32_t user_bank_size;
261  uint32_t data_width;
262  uint32_t cr_bker_mask;
263  uint32_t sr_bsy_mask;
264  uint32_t wrpxxr_mask;
266  uint32_t flash_regs_base;
267  const uint32_t *flash_regs;
269  enum stm32l4_rdp rdp;
270  bool tzen;
271  uint32_t optr;
272 };
273 
278 };
279 
280 struct stm32l4_wrp {
282  uint32_t value;
283  bool used;
284  int first;
285  int last;
286  int offset;
287 };
288 
289 /* human readable list of families this drivers supports (sorted alphabetically) */
290 static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U0/U5/WB/WL";
291 
292 static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
293  { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
294 };
295 
296 static const struct stm32l4_rev stm32l43_l44xx_revs[] = {
297  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
298 };
299 
300 
301 static const struct stm32l4_rev stm32c01xx_revs[] = {
302  { 0x1000, "A" }, { 0x1001, "Z" },
303 };
304 
305 static const struct stm32l4_rev stm32c03xx_revs[] = {
306  { 0x1000, "A" }, { 0x1001, "Z" },
307 };
308 
309 static const struct stm32l4_rev stm32c05xx_revs[] = {
310  { 0x1000, "A" },
311 };
312 
313 static const struct stm32l4_rev stm32c071xx_revs[] = {
314  { 0x1001, "Z" },
315 };
316 
317 static const struct stm32l4_rev stm32c09xx_revs[] = {
318  { 0x1000, "A" },
319 };
320 
321 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
322  { 0x1000, "A" },
323 };
324 
325 static const struct stm32l4_rev stm32_g07_g08xx_revs[] = {
326  { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
327 };
328 
329 static const struct stm32l4_rev stm32l49_l4axx_revs[] = {
330  { 0x1000, "A" }, { 0x2000, "B" },
331 };
332 
333 static const struct stm32l4_rev stm32l45_l46xx_revs[] = {
334  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
335 };
336 
337 static const struct stm32l4_rev stm32l41_l42xx_revs[] = {
338  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
339 };
340 
341 static const struct stm32l4_rev stm32g03_g04xx_revs[] = {
342  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
343 };
344 
345 static const struct stm32l4_rev stm32g0b_g0cxx_revs[] = {
346  { 0x1000, "A" },
347 };
348 
349 static const struct stm32l4_rev stm32u0xx_revs[] = {
350  { 0x1000, "A" },
351 };
352 
353 static const struct stm32l4_rev stm32g43_g44xx_revs[] = {
354  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
355 };
356 
357 static const struct stm32l4_rev stm32g47_g48xx_revs[] = {
358  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
359 };
360 
361 static const struct stm32l4_rev stm32l4r_l4sxx_revs[] = {
362  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
363  { 0x101F, "V" },
364 };
365 
366 static const struct stm32l4_rev stm32l4p_l4qxx_revs[] = {
367  { 0x1001, "Z" },
368 };
369 
370 static const struct stm32l4_rev stm32l55_l56xx_revs[] = {
371  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
372 };
373 
374 static const struct stm32l4_rev stm32g49_g4axx_revs[] = {
375  { 0x1000, "A" },
376 };
377 
378 static const struct stm32l4_rev stm32u53_u54xx_revs[] = {
379  { 0x1000, "A" }, { 0x1001, "Z" },
380 };
381 
382 static const struct stm32l4_rev stm32u57_u58xx_revs[] = {
383  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
384  { 0x2001, "X" }, { 0x3000, "C" }, { 0x3001, "W" }, { 0x3007, "U" },
385 };
386 
387 static const struct stm32l4_rev stm32u59_u5axx_revs[] = {
388  { 0x3001, "X" }, { 0x3002, "W" },
389 };
390 
391 static const struct stm32l4_rev stm32u5f_u5gxx_revs[] = {
392  { 0x1000, "A" }, { 0x1001, "Z" },
393 };
394 
395 static const struct stm32l4_rev stm32wba5x_revs[] = {
396  { 0x1000, "A" },
397 };
398 
399 static const struct stm32l4_rev stm32wb1xx_revs[] = {
400  { 0x1000, "A" }, { 0x2000, "B" },
401 };
402 
403 static const struct stm32l4_rev stm32wb5xx_revs[] = {
404  { 0x2001, "2.1" },
405 };
406 
407 static const struct stm32l4_rev stm32wb3xx_revs[] = {
408  { 0x1000, "A" },
409 };
410 
411 static const struct stm32l4_rev stm32wle_wl5xx_revs[] = {
412  { 0x1000, "1.0" },
413 };
414 
415 static const struct stm32l4_part_info stm32l4_parts[] = {
416  {
418  .revs = stm32l47_l48xx_revs,
419  .num_revs = ARRAY_SIZE(stm32l47_l48xx_revs),
420  .device_str = "STM32L47/L48xx",
421  .max_flash_size_kb = 1024,
422  .flags = F_HAS_DUAL_BANK,
423  .flash_regs_base = 0x40022000,
424  .fsize_addr = 0x1FFF75E0,
425  .otp_base = 0x1FFF7000,
426  .otp_size = 1024,
427  },
428  {
429  .id = DEVID_STM32L43_L44XX,
430  .revs = stm32l43_l44xx_revs,
431  .num_revs = ARRAY_SIZE(stm32l43_l44xx_revs),
432  .device_str = "STM32L43/L44xx",
433  .max_flash_size_kb = 256,
434  .flags = F_NONE,
435  .flash_regs_base = 0x40022000,
436  .fsize_addr = 0x1FFF75E0,
437  .otp_base = 0x1FFF7000,
438  .otp_size = 1024,
439  },
440  {
441  .id = DEVID_STM32C01XX,
442  .revs = stm32c01xx_revs,
443  .num_revs = ARRAY_SIZE(stm32c01xx_revs),
444  .device_str = "STM32C01xx",
445  .max_flash_size_kb = 32,
446  .flags = F_NONE,
447  .flash_regs_base = 0x40022000,
448  .fsize_addr = 0x1FFF75A0,
449  .otp_base = 0x1FFF7000,
450  .otp_size = 1024,
451  },
452  {
453  .id = DEVID_STM32C03XX,
454  .revs = stm32c03xx_revs,
455  .num_revs = ARRAY_SIZE(stm32c03xx_revs),
456  .device_str = "STM32C03xx",
457  .max_flash_size_kb = 32,
458  .flags = F_NONE,
459  .flash_regs_base = 0x40022000,
460  .fsize_addr = 0x1FFF75A0,
461  .otp_base = 0x1FFF7000,
462  .otp_size = 1024,
463  },
464  {
465  .id = DEVID_STM32C05XX,
466  .revs = stm32c05xx_revs,
467  .num_revs = ARRAY_SIZE(stm32c05xx_revs),
468  .device_str = "STM32C05xx",
469  .max_flash_size_kb = 64,
470  .flags = F_NONE,
471  .flash_regs_base = 0x40022000,
472  .fsize_addr = 0x1FFF75A0,
473  .otp_base = 0x1FFF7000,
474  .otp_size = 1024,
475  },
476  {
477  .id = DEVID_STM32C071XX,
478  .revs = stm32c071xx_revs,
479  .num_revs = ARRAY_SIZE(stm32c071xx_revs),
480  .device_str = "STM32C071xx",
481  .max_flash_size_kb = 128,
482  .flags = F_NONE,
483  .flash_regs_base = 0x40022000,
484  .fsize_addr = 0x1FFF75A0,
485  .otp_base = 0x1FFF7000,
486  .otp_size = 1024,
487  },
488  {
489  .id = DEVID_STM32C09XX,
490  .revs = stm32c09xx_revs,
491  .num_revs = ARRAY_SIZE(stm32c09xx_revs),
492  .device_str = "STM32C09xx",
493  .max_flash_size_kb = 256,
494  .flags = F_NONE,
495  .flash_regs_base = 0x40022000,
496  .fsize_addr = 0x1FFF75A0,
497  .otp_base = 0x1FFF7000,
498  .otp_size = 1024,
499  },
500  {
501  .id = DEVID_STM32U53_U54XX,
502  .revs = stm32u53_u54xx_revs,
503  .num_revs = ARRAY_SIZE(stm32u53_u54xx_revs),
504  .device_str = "STM32U535/U545",
505  .max_flash_size_kb = 512,
508  .flash_regs_base = 0x40022000,
509  .fsize_addr = 0x0BFA07A0,
510  .otp_base = 0x0BFA0000,
511  .otp_size = 512,
512  },
513  {
514  .id = DEVID_STM32G05_G06XX,
515  .revs = stm32g05_g06xx_revs,
516  .num_revs = ARRAY_SIZE(stm32g05_g06xx_revs),
517  .device_str = "STM32G05/G06xx",
518  .max_flash_size_kb = 64,
519  .flags = F_NONE,
520  .flash_regs_base = 0x40022000,
521  .fsize_addr = 0x1FFF75E0,
522  .otp_base = 0x1FFF7000,
523  .otp_size = 1024,
524  },
525  {
526  .id = DEVID_STM32G07_G08XX,
527  .revs = stm32_g07_g08xx_revs,
528  .num_revs = ARRAY_SIZE(stm32_g07_g08xx_revs),
529  .device_str = "STM32G07/G08xx",
530  .max_flash_size_kb = 128,
531  .flags = F_NONE,
532  .flash_regs_base = 0x40022000,
533  .fsize_addr = 0x1FFF75E0,
534  .otp_base = 0x1FFF7000,
535  .otp_size = 1024,
536  },
537  {
538  .id = DEVID_STM32L49_L4AXX,
539  .revs = stm32l49_l4axx_revs,
540  .num_revs = ARRAY_SIZE(stm32l49_l4axx_revs),
541  .device_str = "STM32L49/L4Axx",
542  .max_flash_size_kb = 1024,
543  .flags = F_HAS_DUAL_BANK,
544  .flash_regs_base = 0x40022000,
545  .fsize_addr = 0x1FFF75E0,
546  .otp_base = 0x1FFF7000,
547  .otp_size = 1024,
548  },
549  {
550  .id = DEVID_STM32L45_L46XX,
551  .revs = stm32l45_l46xx_revs,
552  .num_revs = ARRAY_SIZE(stm32l45_l46xx_revs),
553  .device_str = "STM32L45/L46xx",
554  .max_flash_size_kb = 512,
555  .flags = F_NONE,
556  .flash_regs_base = 0x40022000,
557  .fsize_addr = 0x1FFF75E0,
558  .otp_base = 0x1FFF7000,
559  .otp_size = 1024,
560  },
561  {
562  .id = DEVID_STM32L41_L42XX,
563  .revs = stm32l41_l42xx_revs,
564  .num_revs = ARRAY_SIZE(stm32l41_l42xx_revs),
565  .device_str = "STM32L41/L42xx",
566  .max_flash_size_kb = 128,
567  .flags = F_NONE,
568  .flash_regs_base = 0x40022000,
569  .fsize_addr = 0x1FFF75E0,
570  .otp_base = 0x1FFF7000,
571  .otp_size = 1024,
572  },
573  {
574  .id = DEVID_STM32G03_G04XX,
575  .revs = stm32g03_g04xx_revs,
576  .num_revs = ARRAY_SIZE(stm32g03_g04xx_revs),
577  .device_str = "STM32G03x/G04xx",
578  .max_flash_size_kb = 64,
579  .flags = F_NONE,
580  .flash_regs_base = 0x40022000,
581  .fsize_addr = 0x1FFF75E0,
582  .otp_base = 0x1FFF7000,
583  .otp_size = 1024,
584  },
585  {
586  .id = DEVID_STM32G0B_G0CXX,
587  .revs = stm32g0b_g0cxx_revs,
588  .num_revs = ARRAY_SIZE(stm32g0b_g0cxx_revs),
589  .device_str = "STM32G0B/G0Cx",
590  .max_flash_size_kb = 512,
591  .flags = F_HAS_DUAL_BANK,
592  .flash_regs_base = 0x40022000,
593  .fsize_addr = 0x1FFF75E0,
594  .otp_base = 0x1FFF7000,
595  .otp_size = 1024,
596  },
597  {
598  .id = DEVID_STM32G43_G44XX,
599  .revs = stm32g43_g44xx_revs,
600  .num_revs = ARRAY_SIZE(stm32g43_g44xx_revs),
601  .device_str = "STM32G43/G44xx",
602  .max_flash_size_kb = 128,
603  .flags = F_NONE,
604  .flash_regs_base = 0x40022000,
605  .fsize_addr = 0x1FFF75E0,
606  .otp_base = 0x1FFF7000,
607  .otp_size = 1024,
608  },
609  {
610  .id = DEVID_STM32G47_G48XX,
611  .revs = stm32g47_g48xx_revs,
612  .num_revs = ARRAY_SIZE(stm32g47_g48xx_revs),
613  .device_str = "STM32G47/G48xx",
614  .max_flash_size_kb = 512,
615  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
616  .flash_regs_base = 0x40022000,
617  .fsize_addr = 0x1FFF75E0,
618  .otp_base = 0x1FFF7000,
619  .otp_size = 1024,
620  },
621  {
622  .id = DEVID_STM32L4R_L4SXX,
623  .revs = stm32l4r_l4sxx_revs,
624  .num_revs = ARRAY_SIZE(stm32l4r_l4sxx_revs),
625  .device_str = "STM32L4R/L4Sxx",
626  .max_flash_size_kb = 2048,
627  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
628  .flash_regs_base = 0x40022000,
629  .fsize_addr = 0x1FFF75E0,
630  .otp_base = 0x1FFF7000,
631  .otp_size = 1024,
632  },
633  {
634  .id = DEVID_STM32L4P_L4QXX,
635  .revs = stm32l4p_l4qxx_revs,
636  .num_revs = ARRAY_SIZE(stm32l4p_l4qxx_revs),
637  .device_str = "STM32L4P/L4Qxx",
638  .max_flash_size_kb = 1024,
639  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
640  .flash_regs_base = 0x40022000,
641  .fsize_addr = 0x1FFF75E0,
642  .otp_base = 0x1FFF7000,
643  .otp_size = 1024,
644  },
645  {
646  .id = DEVID_STM32L55_L56XX,
647  .revs = stm32l55_l56xx_revs,
648  .num_revs = ARRAY_SIZE(stm32l55_l56xx_revs),
649  .device_str = "STM32L55/L56xx",
650  .max_flash_size_kb = 512,
652  .flash_regs_base = 0x40022000,
653  .fsize_addr = 0x0BFA05E0,
654  .otp_base = 0x0BFA0000,
655  .otp_size = 512,
656  },
657  {
658  .id = DEVID_STM32G49_G4AXX,
659  .revs = stm32g49_g4axx_revs,
660  .num_revs = ARRAY_SIZE(stm32g49_g4axx_revs),
661  .device_str = "STM32G49/G4Axx",
662  .max_flash_size_kb = 512,
663  .flags = F_NONE,
664  .flash_regs_base = 0x40022000,
665  .fsize_addr = 0x1FFF75E0,
666  .otp_base = 0x1FFF7000,
667  .otp_size = 1024,
668  },
669  {
670  .id = DEVID_STM32U031XX,
671  .revs = stm32u0xx_revs,
672  .num_revs = ARRAY_SIZE(stm32u0xx_revs),
673  .device_str = "STM32U031xx",
674  .max_flash_size_kb = 64,
675  .flags = F_NONE,
676  .flash_regs_base = 0x40022000,
677  .fsize_addr = 0x1FFF3EA0,
678  .otp_base = 0x1FFF6800,
679  .otp_size = 1024,
680  },
681  {
683  .revs = stm32u0xx_revs,
684  .num_revs = ARRAY_SIZE(stm32u0xx_revs),
685  .device_str = "STM32U073/U083xx",
686  .max_flash_size_kb = 256,
687  .flags = F_NONE,
688  .flash_regs_base = 0x40022000,
689  .fsize_addr = 0x1FFF6EA0,
690  .otp_base = 0x1FFF6800,
691  .otp_size = 1024,
692  },
693  {
694  .id = DEVID_STM32U59_U5AXX,
695  .revs = stm32u59_u5axx_revs,
696  .num_revs = ARRAY_SIZE(stm32u59_u5axx_revs),
697  .device_str = "STM32U59/U5Axx",
698  .max_flash_size_kb = 4096,
701  .flash_regs_base = 0x40022000,
702  .fsize_addr = 0x0BFA07A0,
703  .otp_base = 0x0BFA0000,
704  .otp_size = 512,
705  },
706  {
707  .id = DEVID_STM32U57_U58XX,
708  .revs = stm32u57_u58xx_revs,
709  .num_revs = ARRAY_SIZE(stm32u57_u58xx_revs),
710  .device_str = "STM32U57/U58xx",
711  .max_flash_size_kb = 2048,
714  .flash_regs_base = 0x40022000,
715  .fsize_addr = 0x0BFA07A0,
716  .otp_base = 0x0BFA0000,
717  .otp_size = 512,
718  },
719  {
720  .id = DEVID_STM32U5F_U5GXX,
721  .revs = stm32u5f_u5gxx_revs,
722  .num_revs = ARRAY_SIZE(stm32u5f_u5gxx_revs),
723  .device_str = "STM32U5F/U5Gxx",
724  .max_flash_size_kb = 4096,
727  .flash_regs_base = 0x40022000,
728  .fsize_addr = 0x0BFA07A0,
729  .otp_base = 0x0BFA0000,
730  .otp_size = 512,
731  },
732  {
733  .id = DEVID_STM32WBA5X,
734  .revs = stm32wba5x_revs,
735  .num_revs = ARRAY_SIZE(stm32wba5x_revs),
736  .device_str = "STM32WBA5x",
737  .max_flash_size_kb = 1024,
739  .flash_regs_base = 0x40022000,
740  .fsize_addr = 0x0FF907A0,
741  .otp_base = 0x0FF90000,
742  .otp_size = 512,
743  },
744  {
745  .id = DEVID_STM32WB1XX,
746  .revs = stm32wb1xx_revs,
747  .num_revs = ARRAY_SIZE(stm32wb1xx_revs),
748  .device_str = "STM32WB1x",
749  .max_flash_size_kb = 320,
750  .flags = F_NONE,
751  .flash_regs_base = 0x58004000,
752  .fsize_addr = 0x1FFF75E0,
753  .otp_base = 0x1FFF7000,
754  .otp_size = 1024,
755  },
756  {
757  .id = DEVID_STM32WB5XX,
758  .revs = stm32wb5xx_revs,
759  .num_revs = ARRAY_SIZE(stm32wb5xx_revs),
760  .device_str = "STM32WB5x",
761  .max_flash_size_kb = 1024,
762  .flags = F_NONE,
763  .flash_regs_base = 0x58004000,
764  .fsize_addr = 0x1FFF75E0,
765  .otp_base = 0x1FFF7000,
766  .otp_size = 1024,
767  },
768  {
769  .id = DEVID_STM32WB3XX,
770  .revs = stm32wb3xx_revs,
771  .num_revs = ARRAY_SIZE(stm32wb3xx_revs),
772  .device_str = "STM32WB3x",
773  .max_flash_size_kb = 512,
774  .flags = F_NONE,
775  .flash_regs_base = 0x58004000,
776  .fsize_addr = 0x1FFF75E0,
777  .otp_base = 0x1FFF7000,
778  .otp_size = 1024,
779  },
780  {
781  .id = DEVID_STM32WLE_WL5XX,
782  .revs = stm32wle_wl5xx_revs,
783  .num_revs = ARRAY_SIZE(stm32wle_wl5xx_revs),
784  .device_str = "STM32WLE/WL5x",
785  .max_flash_size_kb = 256,
786  .flags = F_NONE,
787  .flash_regs_base = 0x58004000,
788  .fsize_addr = 0x1FFF75E0,
789  .otp_base = 0x1FFF7000,
790  .otp_size = 1024,
791  },
792 };
793 
794 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
795 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
796 {
797  struct stm32l4_flash_bank *stm32l4_info;
798 
799  if (CMD_ARGC < 6)
801 
802  /* fix-up bank base address: 0 is used for normal flash memory */
803  if (bank->base == 0)
804  bank->base = STM32_FLASH_BANK_BASE;
805 
806  stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank));
807  if (!stm32l4_info)
808  return ERROR_FAIL; /* Checkme: What better error to use?*/
809  bank->driver_priv = stm32l4_info;
810 
811  stm32l4_info->probed = false;
812  stm32l4_info->otp_enabled = false;
813  stm32l4_info->user_bank_size = bank->size;
814 
815  return ERROR_OK;
816 }
817 
818 /* bitmap helper extension */
819 struct range {
820  unsigned int start;
821  unsigned int end;
822 };
823 
824 static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits,
825  struct range *ranges, unsigned int *ranges_count)
826 {
827  *ranges_count = 0;
828  bool last_bit = 0, cur_bit;
829  for (unsigned int i = 0; i < nbits; i++) {
830  cur_bit = test_bit(i, bitmap);
831 
832  if (cur_bit && !last_bit) {
833  (*ranges_count)++;
834  ranges[*ranges_count - 1].start = i;
835  ranges[*ranges_count - 1].end = i;
836  } else if (cur_bit && last_bit) {
837  /* update (increment) the end this range */
838  ranges[*ranges_count - 1].end = i;
839  }
840 
841  last_bit = cur_bit;
842  }
843 }
844 
845 static inline int range_print_one(struct range *range, char *str)
846 {
847  if (range->start == range->end)
848  return sprintf(str, "[%d]", range->start);
849 
850  return sprintf(str, "[%d,%d]", range->start, range->end);
851 }
852 
853 static char *range_print_alloc(struct range *ranges, unsigned int ranges_count)
854 {
855  /* each range will be printed like the following: [start,end]
856  * start and end, both are unsigned int, an unsigned int takes 10 characters max
857  * plus 3 characters for '[', ',' and ']'
858  * thus means each range can take maximum 23 character
859  * after each range we add a ' ' as separator and finally we need the '\0'
860  * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
861  char *str = calloc(1, ranges_count * (24 * sizeof(char)) + 1);
862  char *ptr = str;
863 
864  for (unsigned int i = 0; i < ranges_count; i++) {
865  ptr += range_print_one(&(ranges[i]), ptr);
866 
867  if (i < ranges_count - 1)
868  *(ptr++) = ' ';
869  }
870 
871  return str;
872 }
873 
874 /* end of bitmap helper extension */
875 
876 static inline bool stm32l4_is_otp(struct flash_bank *bank)
877 {
878  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
879  return bank->base == stm32l4_info->part_info->otp_base;
880 }
881 
882 static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
883 {
884  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
885 
886  if (!stm32l4_is_otp(bank))
887  return ERROR_FAIL;
888 
889  char *op_str = enable ? "enabled" : "disabled";
890 
891  LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
892  bank->bank_number,
893  stm32l4_info->otp_enabled == enable ? "already " : "",
894  op_str);
895 
896  stm32l4_info->otp_enabled = enable;
897 
898  return ERROR_OK;
899 }
900 
901 static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank)
902 {
903  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
904  return stm32l4_info->otp_enabled;
905 }
906 
908 {
909  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
910 
911  bool tzen = false;
912 
913  if (stm32l4_info->part_info->flags & F_HAS_TZ)
914  tzen = (stm32l4_info->optr & FLASH_TZEN) != 0;
915 
916  uint32_t rdp = stm32l4_info->optr & FLASH_RDP_MASK;
917 
918  /* for devices without TrustZone:
919  * RDP level 0 and 2 values are to 0xAA and 0xCC
920  * Any other value corresponds to RDP level 1
921  * for devices with TrusZone:
922  * RDP level 0 and 2 values are 0xAA and 0xCC
923  * RDP level 0.5 value is 0x55 only if TZEN = 1
924  * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
925  */
926 
927  if (rdp != RDP_LEVEL_0 && rdp != RDP_LEVEL_2) {
928  if (!tzen || (tzen && rdp != RDP_LEVEL_0_5))
929  rdp = RDP_LEVEL_1;
930  }
931 
932  stm32l4_info->tzen = tzen;
933  stm32l4_info->rdp = rdp;
934 }
935 
936 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
937 {
938  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
939  return stm32l4_info->flash_regs_base + reg_offset;
940 }
941 
942 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
943  enum stm32l4_flash_reg_index reg_index)
944 {
945  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
946  return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
947 }
948 
949 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
950 {
951  return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
952 }
953 
955  enum stm32l4_flash_reg_index reg_index, uint32_t *value)
956 {
957  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
958  return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
959 }
960 
961 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
962 {
963  return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
964 }
965 
967  enum stm32l4_flash_reg_index reg_index, uint32_t value)
968 {
969  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
970  return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
971 }
972 
974 {
975  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
976  uint32_t status;
977  int retval = ERROR_OK;
978 
979  /* wait for busy to clear */
980  for (;;) {
982  if (retval != ERROR_OK)
983  return retval;
984  LOG_DEBUG("status: 0x%" PRIx32 "", status);
985  if ((status & stm32l4_info->sr_bsy_mask) == 0)
986  break;
987  if (timeout-- <= 0) {
988  LOG_ERROR("timed out waiting for flash");
989  return ERROR_FAIL;
990  }
991  alive_sleep(1);
992  }
993 
994  if (status & FLASH_WRPERR) {
995  LOG_ERROR("stm32x device protected");
996  retval = ERROR_FAIL;
997  }
998 
999  /* Clear but report errors */
1000  if (status & FLASH_ERROR) {
1001  if (retval == ERROR_OK)
1002  retval = ERROR_FAIL;
1003  /* If this operation fails, we ignore it and report the original
1004  * retval
1005  */
1007  }
1008 
1009  return retval;
1010 }
1011 
1013 static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
1014 {
1015  /* This function should be used only with device with TrustZone, do just a security check */
1016  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1017  assert(stm32l4_info->part_info->flags & F_HAS_TZ);
1018 
1019  /* based on RM0438 Rev6 for STM32L5x devices:
1020  * to modify a page block-based security attribution, it is recommended to
1021  * 1- check that no flash operation is ongoing on the related page
1022  * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
1023  * this step is not need in case of JTAG direct access
1024  */
1026  if (retval != ERROR_OK)
1027  return retval;
1028 
1029  /* write SECBBxRy registers */
1030  LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
1031 
1032  const uint8_t secbb_regs[] = {
1033  FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
1034  FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
1035  };
1036 
1037 
1038  unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
1039 
1040  /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
1041  * then consider only the first half of secbb_regs
1042  */
1043  if (!stm32l4_info->dual_bank_mode)
1044  num_secbb_regs /= 2;
1045 
1046  for (unsigned int i = 0; i < num_secbb_regs; i++) {
1047  retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
1048  if (retval != ERROR_OK)
1049  return retval;
1050  }
1051 
1052  return ERROR_OK;
1053 }
1054 
1056 {
1057  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1058  return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
1060 }
1061 
1063 {
1064  const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
1065  uint32_t ctrl;
1066 
1067  /* first check if not already unlocked
1068  * otherwise writing on STM32_FLASH_KEYR will fail
1069  */
1070  int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1071  if (retval != ERROR_OK)
1072  return retval;
1073 
1074  if ((ctrl & FLASH_LOCK) == 0)
1075  return ERROR_OK;
1076 
1077  /* unlock flash registers */
1079  if (retval != ERROR_OK)
1080  return retval;
1081 
1083  if (retval != ERROR_OK)
1084  return retval;
1085 
1086  retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1087  if (retval != ERROR_OK)
1088  return retval;
1089 
1090  if (ctrl & FLASH_LOCK) {
1091  LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
1092  return ERROR_TARGET_FAILURE;
1093  }
1094 
1095  return ERROR_OK;
1096 }
1097 
1099 {
1100  const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
1101  uint32_t ctrl;
1102 
1103  int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1104  if (retval != ERROR_OK)
1105  return retval;
1106 
1107  if ((ctrl & FLASH_OPTLOCK) == 0)
1108  return ERROR_OK;
1109 
1110  /* unlock option registers */
1112  if (retval != ERROR_OK)
1113  return retval;
1114 
1116  if (retval != ERROR_OK)
1117  return retval;
1118 
1119  retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1120  if (retval != ERROR_OK)
1121  return retval;
1122 
1123  if (ctrl & FLASH_OPTLOCK) {
1124  LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
1125  return ERROR_TARGET_FAILURE;
1126  }
1127 
1128  return ERROR_OK;
1129 }
1130 
1132 {
1133  int retval, retval2;
1134 
1135  retval = stm32l4_unlock_reg(bank);
1136  if (retval != ERROR_OK)
1137  goto err_lock;
1138 
1139  retval = stm32l4_unlock_option_reg(bank);
1140  if (retval != ERROR_OK)
1141  goto err_lock;
1142 
1143  /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1144  * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1145  * "Note: If the read protection is set while the debugger is still
1146  * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1147  */
1148 
1149  /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
1150  /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
1151  * then just ignore the returned value */
1153 
1154  /* Need to re-probe after change */
1155  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1156  stm32l4_info->probed = false;
1157 
1158 err_lock:
1161 
1162  if (retval != ERROR_OK)
1163  return retval;
1164 
1165  return retval2;
1166 }
1167 
1168 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
1169  uint32_t value, uint32_t mask)
1170 {
1171  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1172  uint32_t optiondata;
1173  int retval, retval2;
1174 
1175  retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
1176  if (retval != ERROR_OK)
1177  return retval;
1178 
1179  /* for STM32L5 and similar devices, use always non-secure
1180  * registers for option bytes programming */
1181  const uint32_t *saved_flash_regs = stm32l4_info->flash_regs;
1182  if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
1183  stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1184 
1185  retval = stm32l4_unlock_reg(bank);
1186  if (retval != ERROR_OK)
1187  goto err_lock;
1188 
1189  retval = stm32l4_unlock_option_reg(bank);
1190  if (retval != ERROR_OK)
1191  goto err_lock;
1192 
1193  optiondata = (optiondata & ~mask) | (value & mask);
1194 
1195  retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
1196  if (retval != ERROR_OK)
1197  goto err_lock;
1198 
1200  if (retval != ERROR_OK)
1201  goto err_lock;
1202 
1204 
1205 err_lock:
1208  stm32l4_info->flash_regs = saved_flash_regs;
1209 
1210  if (retval != ERROR_OK)
1211  return retval;
1212 
1213  return retval2;
1214 }
1215 
1216 static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy,
1217  enum stm32l4_flash_reg_index reg_idx, int offset)
1218 {
1219  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1220  int ret;
1221 
1222  wrpxy->reg_idx = reg_idx;
1223  wrpxy->offset = offset;
1224 
1225  ret = stm32l4_read_flash_reg_by_index(bank, wrpxy->reg_idx , &wrpxy->value);
1226  if (ret != ERROR_OK)
1227  return ret;
1228 
1229  wrpxy->first = (wrpxy->value & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1230  wrpxy->last = ((wrpxy->value >> 16) & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1231  wrpxy->used = wrpxy->first <= wrpxy->last;
1232 
1233  return ERROR_OK;
1234 }
1235 
1236 static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id,
1237  struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
1238 {
1239  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1240  int ret;
1241 
1242  *n_wrp = 0;
1243 
1244  /* for single bank devices there is 2 WRP regions.
1245  * for dual bank devices there is 2 WRP regions per bank,
1246  * if configured as single bank only 2 WRP are usable
1247  * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1248  * note: this should be revised, if a device will have the SWAP banks option
1249  */
1250 
1251  int wrp2y_sectors_offset = -1; /* -1 : unused */
1252 
1253  /* if bank_id is BANK1 or ALL_BANKS */
1254  if (dev_bank_id != STM32_BANK2) {
1255  /* get FLASH_WRP1AR */
1256  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1AR_INDEX, 0);
1257  if (ret != ERROR_OK)
1258  return ret;
1259 
1260  /* get WRP1BR */
1261  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1BR_INDEX, 0);
1262  if (ret != ERROR_OK)
1263  return ret;
1264 
1265  /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1266  if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
1267  wrp2y_sectors_offset = 0;
1268  }
1269 
1270  /* if bank_id is BANK2 or ALL_BANKS */
1271  if (dev_bank_id != STM32_BANK1 && stm32l4_info->dual_bank_mode)
1272  wrp2y_sectors_offset = stm32l4_info->bank1_sectors;
1273 
1274  if (wrp2y_sectors_offset >= 0) {
1275  /* get WRP2AR */
1276  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2AR_INDEX, wrp2y_sectors_offset);
1277  if (ret != ERROR_OK)
1278  return ret;
1279 
1280  /* get WRP2BR */
1281  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2BR_INDEX, wrp2y_sectors_offset);
1282  if (ret != ERROR_OK)
1283  return ret;
1284  }
1285 
1286  return ERROR_OK;
1287 }
1288 
1289 static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
1290 {
1291  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1292 
1293  int wrp_start = wrpxy->first - wrpxy->offset;
1294  int wrp_end = wrpxy->last - wrpxy->offset;
1295 
1296  uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
1297  if (stm32l4_info->part_info->flags & F_WRP_HAS_LOCK)
1298  wrp_value |= FLASH_WRPXYR_UNLOCK;
1299 
1300  return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
1301 }
1302 
1303 static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
1304 {
1305  int ret;
1306 
1307  for (unsigned int i = 0; i < n_wrp; i++) {
1308  ret = stm32l4_write_one_wrpxy(bank, &wrpxy[i]);
1309  if (ret != ERROR_OK)
1310  return ret;
1311  }
1312 
1313  return ERROR_OK;
1314 }
1315 
1317 {
1318  unsigned int n_wrp;
1319  struct stm32l4_wrp wrpxy[4];
1320 
1321  int ret = stm32l4_get_all_wrpxy(bank, STM32_ALL_BANKS, wrpxy, &n_wrp);
1322  if (ret != ERROR_OK)
1323  return ret;
1324 
1325  /* initialize all sectors as unprotected */
1326  for (unsigned int i = 0; i < bank->num_sectors; i++)
1327  bank->sectors[i].is_protected = 0;
1328 
1329  /* now check WRPxy and mark the protected sectors */
1330  for (unsigned int i = 0; i < n_wrp; i++) {
1331  if (wrpxy[i].used) {
1332  for (int s = wrpxy[i].first; s <= wrpxy[i].last; s++)
1333  bank->sectors[s].is_protected = 1;
1334  }
1335  }
1336 
1337  return ERROR_OK;
1338 }
1339 
1340 static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
1341  unsigned int last)
1342 {
1343  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1344  int retval, retval2;
1345 
1346  assert((first <= last) && (last < bank->num_sectors));
1347 
1348  if (stm32l4_is_otp(bank)) {
1349  LOG_ERROR("cannot erase OTP memory");
1351  }
1352 
1353  if (bank->target->state != TARGET_HALTED) {
1354  LOG_ERROR("Target not halted");
1355  return ERROR_TARGET_NOT_HALTED;
1356  }
1357 
1358  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1359  /* set all FLASH pages as secure */
1361  if (retval != ERROR_OK) {
1362  /* restore all FLASH pages as non-secure */
1363  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1364  return retval;
1365  }
1366  }
1367 
1368  retval = stm32l4_unlock_reg(bank);
1369  if (retval != ERROR_OK)
1370  goto err_lock;
1371 
1372  /*
1373  Sector Erase
1374  To erase a sector, follow the procedure below:
1375  1. Check that no Flash memory operation is ongoing by
1376  checking the BSY bit in the FLASH_SR register
1377  2. Set the PER bit and select the page and bank
1378  you wish to erase in the FLASH_CR register
1379  3. Set the STRT bit in the FLASH_CR register
1380  4. Wait for the BSY bit to be cleared
1381  */
1382 
1383  for (unsigned int i = first; i <= last; i++) {
1384  uint32_t erase_flags;
1385  erase_flags = FLASH_PER | FLASH_STRT;
1386 
1387  if (i >= stm32l4_info->bank1_sectors) {
1388  uint8_t snb;
1389  snb = i - stm32l4_info->bank1_sectors;
1390  erase_flags |= snb << FLASH_PAGE_SHIFT | stm32l4_info->cr_bker_mask;
1391  } else
1392  erase_flags |= i << FLASH_PAGE_SHIFT;
1394  if (retval != ERROR_OK)
1395  break;
1396 
1398  if (retval != ERROR_OK)
1399  break;
1400  }
1401 
1402 err_lock:
1404 
1405  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1406  /* restore all FLASH pages as non-secure */
1408  if (retval3 != ERROR_OK)
1409  return retval3;
1410  }
1411 
1412  if (retval != ERROR_OK)
1413  return retval;
1414 
1415  return retval2;
1416 }
1417 
1418 static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set,
1419  unsigned int first, unsigned int last)
1420 {
1421  unsigned int i;
1422 
1423  /* check if the desired protection is already configured */
1424  for (i = first; i <= last; i++) {
1425  if (bank->sectors[i].is_protected != set)
1426  break;
1427  else if (i == last) {
1428  LOG_INFO("The specified sectors are already %s", set ? "protected" : "unprotected");
1429  return ERROR_OK;
1430  }
1431  }
1432 
1433  /* all sectors from first to last (or part of them) could have different
1434  * protection other than the requested */
1435  unsigned int n_wrp;
1436  struct stm32l4_wrp wrpxy[4];
1437 
1438  int ret = stm32l4_get_all_wrpxy(bank, bank_id, wrpxy, &n_wrp);
1439  if (ret != ERROR_OK)
1440  return ret;
1441 
1442  /* use bitmap and range helpers to optimize the WRP usage */
1443  DECLARE_BITMAP(pages, bank->num_sectors);
1444  bitmap_zero(pages, bank->num_sectors);
1445 
1446  for (i = 0; i < n_wrp; i++) {
1447  if (wrpxy[i].used) {
1448  for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
1449  set_bit(p, pages);
1450  }
1451  }
1452 
1453  /* we have at most 'n_wrp' WRP areas
1454  * add one range if the user is trying to protect a fifth range */
1455  struct range ranges[n_wrp + 1];
1456  unsigned int ranges_count = 0;
1457 
1458  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1459 
1460  /* pretty-print the currently protected ranges */
1461  if (ranges_count > 0) {
1462  char *ranges_str = range_print_alloc(ranges, ranges_count);
1463  LOG_DEBUG("current protected areas: %s", ranges_str);
1464  free(ranges_str);
1465  } else
1466  LOG_DEBUG("current protected areas: none");
1467 
1468  if (set) { /* flash protect */
1469  for (i = first; i <= last; i++)
1470  set_bit(i, pages);
1471  } else { /* flash unprotect */
1472  for (i = first; i <= last; i++)
1473  clear_bit(i, pages);
1474  }
1475 
1476  /* check the ranges_count after the user request */
1477  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1478 
1479  /* pretty-print the requested areas for protection */
1480  if (ranges_count > 0) {
1481  char *ranges_str = range_print_alloc(ranges, ranges_count);
1482  LOG_DEBUG("requested areas for protection: %s", ranges_str);
1483  free(ranges_str);
1484  } else
1485  LOG_DEBUG("requested areas for protection: none");
1486 
1487  if (ranges_count > n_wrp) {
1488  LOG_ERROR("cannot set the requested protection "
1489  "(only %u write protection areas are available)" , n_wrp);
1490  return ERROR_FAIL;
1491  }
1492 
1493  /* re-init all WRPxy as disabled (first > last)*/
1494  for (i = 0; i < n_wrp; i++) {
1495  wrpxy[i].first = wrpxy[i].offset + 1;
1496  wrpxy[i].last = wrpxy[i].offset;
1497  }
1498 
1499  /* then configure WRPxy areas */
1500  for (i = 0; i < ranges_count; i++) {
1501  wrpxy[i].first = ranges[i].start;
1502  wrpxy[i].last = ranges[i].end;
1503  }
1504 
1505  /* finally write WRPxy registers */
1506  return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
1507 }
1508 
1509 static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
1510 {
1511  struct target *target = bank->target;
1512  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1513 
1514  if (stm32l4_is_otp(bank)) {
1515  LOG_ERROR("cannot protect/unprotect OTP memory");
1517  }
1518 
1519  if (target->state != TARGET_HALTED) {
1520  LOG_ERROR("Target not halted");
1521  return ERROR_TARGET_NOT_HALTED;
1522  }
1523 
1524  /* refresh the sectors' protection */
1525  int ret = stm32l4_protect_check(bank);
1526  if (ret != ERROR_OK)
1527  return ret;
1528 
1529  /* the requested sectors could be located into bank1 and/or bank2 */
1530  if (last < stm32l4_info->bank1_sectors) {
1531  return stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, last);
1532  } else if (first >= stm32l4_info->bank1_sectors) {
1533  return stm32l4_protect_same_bank(bank, STM32_BANK2, set, first, last);
1534  } else {
1535  ret = stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, stm32l4_info->bank1_sectors - 1);
1536  if (ret != ERROR_OK)
1537  return ret;
1538 
1539  return stm32l4_protect_same_bank(bank, STM32_BANK2, set, stm32l4_info->bank1_sectors, last);
1540  }
1541 }
1542 
1543 /* count is the size divided by stm32l4_info->data_width */
1544 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
1545  uint32_t offset, uint32_t count)
1546 {
1547  struct target *target = bank->target;
1548  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1549  struct working_area *write_algorithm;
1550  struct working_area *source;
1551  uint32_t address = bank->base + offset;
1552  struct reg_param reg_params[5];
1553  struct armv7m_algorithm armv7m_info;
1554  int retval = ERROR_OK;
1555 
1556  static const uint8_t stm32l4_flash_write_code[] = {
1557 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1558  };
1559 
1560  if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
1561  &write_algorithm) != ERROR_OK) {
1562  LOG_WARNING("no working area available, can't do block memory writes");
1564  }
1565 
1566  retval = target_write_buffer(target, write_algorithm->address,
1567  sizeof(stm32l4_flash_write_code),
1568  stm32l4_flash_write_code);
1569  if (retval != ERROR_OK) {
1570  target_free_working_area(target, write_algorithm);
1571  return retval;
1572  }
1573 
1574  /* data_width should be multiple of double-word */
1575  assert(stm32l4_info->data_width % 8 == 0);
1576  const size_t extra_size = sizeof(struct stm32l4_work_area);
1577  uint32_t buffer_size = target_get_working_area_avail(target) - extra_size;
1578  /* buffer_size should be multiple of stm32l4_info->data_width */
1579  buffer_size &= ~(stm32l4_info->data_width - 1);
1580 
1581  if (buffer_size < 256) {
1582  LOG_WARNING("large enough working area not available, can't do block memory writes");
1583  target_free_working_area(target, write_algorithm);
1585  } else if (buffer_size > 16384) {
1586  /* probably won't benefit from more than 16k ... */
1587  buffer_size = 16384;
1588  }
1589 
1591  LOG_ERROR("allocating working area failed");
1593  }
1594 
1595  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1596  armv7m_info.core_mode = ARM_MODE_THREAD;
1597 
1598  /* contrib/loaders/flash/stm32/stm32l4x.c:write() arguments */
1599  init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* stm32l4_work_area ptr , status (out) */
1600  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
1601  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
1602  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (of stm32l4_info->data_width) */
1603 
1604  buf_set_u32(reg_params[0].value, 0, 32, source->address);
1605  buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
1606  buf_set_u32(reg_params[2].value, 0, 32, address);
1607  buf_set_u32(reg_params[3].value, 0, 32, count);
1608 
1609  /* write algo stack pointer */
1610  init_reg_param(&reg_params[4], "sp", 32, PARAM_OUT);
1611  buf_set_u32(reg_params[4].value, 0, 32, source->address +
1612  offsetof(struct stm32l4_work_area, stack) + LDR_STACK_SIZE);
1613 
1614  struct stm32l4_loader_params loader_extra_params;
1615 
1616  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_addr,
1618  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_cr_addr,
1620  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_word_size,
1621  stm32l4_info->data_width);
1622  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_bsy_mask,
1623  stm32l4_info->sr_bsy_mask);
1624 
1625  retval = target_write_buffer(target, source->address, sizeof(loader_extra_params),
1626  (uint8_t *) &loader_extra_params);
1627  if (retval != ERROR_OK)
1628  return retval;
1629 
1631  0, NULL,
1632  ARRAY_SIZE(reg_params), reg_params,
1633  source->address + offsetof(struct stm32l4_work_area, fifo),
1634  source->size - offsetof(struct stm32l4_work_area, fifo),
1635  write_algorithm->address, 0,
1636  &armv7m_info);
1637 
1638  if (retval == ERROR_FLASH_OPERATION_FAILED) {
1639  LOG_ERROR("error executing stm32l4 flash write algorithm");
1640 
1641  uint32_t error;
1643  error &= FLASH_ERROR;
1644 
1645  if (error & FLASH_WRPERR)
1646  LOG_ERROR("flash memory write protected");
1647 
1648  if (error != 0) {
1649  LOG_ERROR("flash write failed = %08" PRIx32, error);
1650  /* Clear but report errors */
1652  retval = ERROR_FAIL;
1653  }
1654  }
1655 
1657  target_free_working_area(target, write_algorithm);
1658 
1659  destroy_reg_param(&reg_params[0]);
1660  destroy_reg_param(&reg_params[1]);
1661  destroy_reg_param(&reg_params[2]);
1662  destroy_reg_param(&reg_params[3]);
1663  destroy_reg_param(&reg_params[4]);
1664 
1665  return retval;
1666 }
1667 
1668 /* count is the size divided by stm32l4_info->data_width */
1669 static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
1670  uint32_t offset, uint32_t count)
1671 {
1672  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1673  struct target *target = bank->target;
1674  uint32_t address = bank->base + offset;
1675  int retval = ERROR_OK;
1676 
1677  /* wait for BSY bit */
1679  if (retval != ERROR_OK)
1680  return retval;
1681 
1682  /* set PG in FLASH_CR */
1684  if (retval != ERROR_OK)
1685  return retval;
1686 
1687 
1688  /* write directly to flash memory */
1689  const uint8_t *src = buffer;
1690  const uint32_t data_width_in_words = stm32l4_info->data_width / 4;
1691  while (count--) {
1692  retval = target_write_memory(target, address, 4, data_width_in_words, src);
1693  if (retval != ERROR_OK)
1694  return retval;
1695 
1696  /* wait for BSY bit */
1698  if (retval != ERROR_OK)
1699  return retval;
1700 
1701  src += stm32l4_info->data_width;
1702  address += stm32l4_info->data_width;
1703  }
1704 
1705  /* reset PG in FLASH_CR */
1707  if (retval != ERROR_OK)
1708  return retval;
1709 
1710  return retval;
1711 }
1712 
1713 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
1714  uint32_t offset, uint32_t count)
1715 {
1716  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1717  int retval = ERROR_OK, retval2;
1718 
1720  LOG_ERROR("OTP memory is disabled for write commands");
1721  return ERROR_FAIL;
1722  }
1723 
1724  if (bank->target->state != TARGET_HALTED) {
1725  LOG_ERROR("Target not halted");
1726  return ERROR_TARGET_NOT_HALTED;
1727  }
1728 
1729  /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1730  assert(stm32l4_info->data_width % 8 == 0);
1731 
1732  /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1733  * The flash infrastructure ensures it, do just a security check */
1734  assert(offset % stm32l4_info->data_width == 0);
1735  assert(count % stm32l4_info->data_width == 0);
1736 
1737  /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1738  * data to be written does not go into a gap:
1739  * suppose buffer is fully contained in bank from sector 0 to sector
1740  * num->sectors - 1 and sectors are ordered according to offset
1741  */
1742  struct flash_sector *head = &bank->sectors[0];
1743  struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
1744 
1745  while ((head < tail) && (offset >= (head + 1)->offset)) {
1746  /* buffer does not intersect head nor gap behind head */
1747  head++;
1748  }
1749 
1750  while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
1751  /* buffer does not intersect tail nor gap before tail */
1752  --tail;
1753  }
1754 
1755  LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
1756  offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
1757 
1758  /* Now check that there is no gap from head to tail, this should work
1759  * even for multiple or non-symmetric gaps
1760  */
1761  while (head < tail) {
1762  if (head->offset + head->size != (head + 1)->offset) {
1763  LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
1764  bank->base + head->offset + head->size,
1765  bank->base + (head + 1)->offset - 1);
1766  retval = ERROR_FLASH_DST_OUT_OF_BANK;
1767  }
1768  head++;
1769  }
1770 
1771  if (retval != ERROR_OK)
1772  return retval;
1773 
1774  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1775  /* set all FLASH pages as secure */
1777  if (retval != ERROR_OK) {
1778  /* restore all FLASH pages as non-secure */
1779  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1780  return retval;
1781  }
1782  }
1783 
1784  retval = stm32l4_unlock_reg(bank);
1785  if (retval != ERROR_OK)
1786  goto err_lock;
1787 
1788 
1789  /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1790  * the debug is possible only in non-secure state.
1791  * Thus means the flashloader will run in non-secure mode,
1792  * and the workarea need to be in non-secure RAM */
1793  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
1794  LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1795 
1796  /* first try to write using the loader, for better performance */
1798  count / stm32l4_info->data_width);
1799 
1800  /* if resources are not available write without a loader */
1801  if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1802  LOG_WARNING("falling back to programming without a flash loader (slower)");
1804  count / stm32l4_info->data_width);
1805  }
1806 
1807 err_lock:
1809 
1810  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1811  /* restore all FLASH pages as non-secure */
1813  if (retval3 != ERROR_OK)
1814  return retval3;
1815  }
1816 
1817  if (retval != ERROR_OK) {
1818  LOG_ERROR("block write failed");
1819  return retval;
1820  }
1821  return retval2;
1822 }
1823 
1824 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
1825 {
1826  int retval = ERROR_OK;
1827  struct target *target = bank->target;
1828 
1829  /* try reading possible IDCODE registers, in the following order */
1830  uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
1831 
1832  for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
1833  retval = target_read_u32(target, dbgmcu_idcode[i], id);
1834  if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
1835  return ERROR_OK;
1836  }
1837 
1838  /* Workaround for STM32WL5x devices:
1839  * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1840  * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1841 
1842  struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1843  if (!armv7m) {
1844  LOG_ERROR("Flash requires Cortex-M target");
1845  return ERROR_TARGET_INVALID;
1846  }
1847 
1848  /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1849  * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
1851  armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) {
1852  uint32_t uid64_ids;
1853 
1854  /* UID64 is contains
1855  * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1856  * - Bits 31:08 : STID (company ID) = 0x0080E1
1857  * - Bits 07:00 : DEVID (device ID) = 0x15
1858  *
1859  * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1860  */
1861  retval = target_read_u32(target, UID64_IDS, &uid64_ids);
1862  if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
1863  /* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
1864  *id = DEVID_STM32WLE_WL5XX;
1865  return ERROR_OK;
1866  }
1867  }
1868 
1869  LOG_ERROR("can't get the device id");
1870  return (retval == ERROR_OK) ? ERROR_FAIL : retval;
1871 }
1872 
1873 static const char *get_stm32l4_rev_str(struct flash_bank *bank)
1874 {
1875  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1876  const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1877  assert(part_info);
1878 
1879  const uint16_t rev_id = stm32l4_info->idcode >> 16;
1880  for (unsigned int i = 0; i < part_info->num_revs; i++) {
1881  if (rev_id == part_info->revs[i].rev)
1882  return part_info->revs[i].str;
1883  }
1884  return "'unknown'";
1885 }
1886 
1887 static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
1888 {
1889  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1890  assert(stm32l4_info->part_info);
1891  return stm32l4_is_otp(bank) ? "OTP" :
1892  stm32l4_info->dual_bank_mode ? "Flash dual" :
1893  "Flash single";
1894 }
1895 
1896 static int stm32l4_probe(struct flash_bank *bank)
1897 {
1898  struct target *target = bank->target;
1899  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1900  const struct stm32l4_part_info *part_info;
1901  uint16_t flash_size_kb = 0xffff;
1902 
1903  if (!target_was_examined(target)) {
1904  LOG_ERROR("Target not examined yet");
1906  }
1907 
1908  struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1909  if (!armv7m) {
1910  LOG_ERROR("Flash requires Cortex-M target");
1911  return ERROR_TARGET_INVALID;
1912  }
1913 
1914  stm32l4_info->probed = false;
1915 
1916  /* read stm32 device id registers */
1917  int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
1918  if (retval != ERROR_OK)
1919  return retval;
1920 
1921  const uint32_t device_id = stm32l4_info->idcode & 0xFFF;
1922 
1923  for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
1924  if (device_id == stm32l4_parts[n].id) {
1925  stm32l4_info->part_info = &stm32l4_parts[n];
1926  break;
1927  }
1928  }
1929 
1930  if (!stm32l4_info->part_info) {
1931  LOG_WARNING("Cannot identify target as an %s family device.", device_families);
1932  return ERROR_FAIL;
1933  }
1934 
1935  part_info = stm32l4_info->part_info;
1936  const char *rev_str = get_stm32l4_rev_str(bank);
1937  const uint16_t rev_id = stm32l4_info->idcode >> 16;
1938 
1939  LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
1940  stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
1941 
1942  stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
1943  stm32l4_info->data_width = (part_info->flags & F_QUAD_WORD_PROG) ? 16 : 8;
1944  stm32l4_info->cr_bker_mask = FLASH_BKER;
1945  stm32l4_info->sr_bsy_mask = FLASH_BSY;
1946 
1947  /* Set flash write alignment boundaries.
1948  * Ask the flash infrastructure to ensure required alignment */
1949  bank->write_start_alignment = stm32l4_info->data_width;
1950  bank->write_end_alignment = stm32l4_info->data_width;
1951 
1952  /* Initialize the flash registers layout */
1953  if (part_info->flags & F_HAS_L5_FLASH_REGS)
1954  stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1955  else
1956  stm32l4_info->flash_regs = stm32l4_flash_regs;
1957 
1958  /* read flash option register */
1960  if (retval != ERROR_OK)
1961  return retval;
1962 
1964 
1965  /* for devices with TrustZone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1966  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1967  if (part_info->flags & F_HAS_L5_FLASH_REGS) {
1968  stm32l4_info->flash_regs_base |= STM32L5_REGS_SEC_OFFSET;
1969  stm32l4_info->flash_regs = stm32l5_s_flash_regs;
1970  } else {
1971  LOG_ERROR("BUG: device supported incomplete");
1972  return ERROR_NOT_IMPLEMENTED;
1973  }
1974  }
1975 
1976  if (part_info->flags & F_HAS_TZ)
1977  LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1978  stm32l4_info->tzen,
1979  stm32l4_info->tzen ? "enabled" : "disabled");
1980 
1981  LOG_INFO("RDP level %s (0x%02X)",
1982  stm32l4_info->rdp == RDP_LEVEL_0 ? "0" : stm32l4_info->rdp == RDP_LEVEL_0_5 ? "0.5" : "1",
1983  stm32l4_info->rdp);
1984 
1985  if (stm32l4_is_otp(bank)) {
1986  bank->size = part_info->otp_size;
1987 
1988  LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
1989 
1990  /* OTP memory is considered as one sector */
1991  free(bank->sectors);
1992  bank->num_sectors = 1;
1993  bank->sectors = alloc_block_array(0, part_info->otp_size, 1);
1994 
1995  if (!bank->sectors) {
1996  LOG_ERROR("failed to allocate bank sectors");
1997  return ERROR_FAIL;
1998  }
1999 
2000  stm32l4_info->probed = true;
2001  return ERROR_OK;
2002  } else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
2003  LOG_ERROR("invalid bank base address");
2004  return ERROR_FAIL;
2005  }
2006 
2007  /* get flash size from target. */
2008  retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
2009 
2010  /* failed reading flash size or flash size invalid (early silicon),
2011  * default to max target family */
2012  if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
2013  || flash_size_kb > part_info->max_flash_size_kb) {
2014  LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
2015  part_info->max_flash_size_kb);
2016  flash_size_kb = part_info->max_flash_size_kb;
2017  }
2018 
2019  /* if the user sets the size manually then ignore the probed value
2020  * this allows us to work around devices that have a invalid flash size register value */
2021  if (stm32l4_info->user_bank_size) {
2022  LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
2023  flash_size_kb = stm32l4_info->user_bank_size / 1024;
2024  }
2025 
2026  LOG_INFO("flash size = %d KiB", flash_size_kb);
2027 
2028  /* did we assign a flash size? */
2029  assert((flash_size_kb != 0xffff) && flash_size_kb);
2030 
2031  const bool is_max_flash_size = flash_size_kb == stm32l4_info->part_info->max_flash_size_kb;
2032 
2033  stm32l4_info->bank1_sectors = 0;
2034  stm32l4_info->hole_sectors = 0;
2035 
2036  int num_pages = 0;
2037  int page_size_kb = 0;
2038 
2039  stm32l4_info->dual_bank_mode = false;
2040 
2041  switch (device_id) {
2042  case DEVID_STM32L47_L48XX:
2043  case DEVID_STM32L49_L4AXX:
2044  /* if flash size is max (1M) the device is always dual bank
2045  * STM32L47/L48xx: has variants with 512K
2046  * STM32L49/L4Axx: has variants with 512 and 256
2047  * for these variants:
2048  * if DUAL_BANK = 0 -> single bank
2049  * else -> dual bank without gap
2050  * note: the page size is invariant
2051  */
2052  page_size_kb = 2;
2053  num_pages = flash_size_kb / page_size_kb;
2054  stm32l4_info->bank1_sectors = num_pages;
2055 
2056  /* check DUAL_BANK option bit if the flash is less than 1M */
2057  if (is_max_flash_size || (stm32l4_info->optr & FLASH_L4_DUAL_BANK)) {
2058  stm32l4_info->dual_bank_mode = true;
2059  stm32l4_info->bank1_sectors = num_pages / 2;
2060  }
2061  break;
2062  case DEVID_STM32L43_L44XX:
2063  case DEVID_STM32C01XX:
2064  case DEVID_STM32C03XX:
2065  case DEVID_STM32C05XX:
2066  case DEVID_STM32C071XX:
2067  case DEVID_STM32C09XX:
2068  case DEVID_STM32G05_G06XX:
2069  case DEVID_STM32G07_G08XX:
2070  case DEVID_STM32U031XX:
2072  case DEVID_STM32L45_L46XX:
2073  case DEVID_STM32L41_L42XX:
2074  case DEVID_STM32G03_G04XX:
2075  case DEVID_STM32G43_G44XX:
2076  case DEVID_STM32G49_G4AXX:
2077  case DEVID_STM32WB1XX:
2078  /* single bank flash */
2079  page_size_kb = 2;
2080  num_pages = flash_size_kb / page_size_kb;
2081  stm32l4_info->bank1_sectors = num_pages;
2082  break;
2083  case DEVID_STM32G0B_G0CXX:
2084  /* single/dual bank depending on DUAL_BANK option bit */
2085  page_size_kb = 2;
2086  num_pages = flash_size_kb / page_size_kb;
2087  stm32l4_info->bank1_sectors = num_pages;
2088  stm32l4_info->cr_bker_mask = FLASH_BKER_G0;
2089 
2090  /* check DUAL_BANK bit */
2091  if (stm32l4_info->optr & FLASH_G0_DUAL_BANK) {
2092  stm32l4_info->sr_bsy_mask = FLASH_BSY | FLASH_BSY2;
2093  stm32l4_info->dual_bank_mode = true;
2094  stm32l4_info->bank1_sectors = num_pages / 2;
2095  }
2096  break;
2097  case DEVID_STM32G47_G48XX:
2098  /* STM32G47/8 can be single/dual bank:
2099  * if DUAL_BANK = 0 -> single bank
2100  * else -> dual bank WITH gap
2101  */
2102  page_size_kb = 4;
2103  num_pages = flash_size_kb / page_size_kb;
2104  stm32l4_info->bank1_sectors = num_pages;
2105  if (stm32l4_info->optr & FLASH_G4_DUAL_BANK) {
2106  stm32l4_info->dual_bank_mode = true;
2107  page_size_kb = 2;
2108  num_pages = flash_size_kb / page_size_kb;
2109  stm32l4_info->bank1_sectors = num_pages / 2;
2110 
2111  /* for devices with trimmed flash, there is a gap between both banks */
2112  stm32l4_info->hole_sectors =
2113  (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
2114  }
2115  break;
2116  case DEVID_STM32L4R_L4SXX:
2117  case DEVID_STM32L4P_L4QXX:
2118  /* STM32L4R/S can be single/dual bank:
2119  * if size = 2M check DBANK bit
2120  * if size = 1M check DB1M bit
2121  * STM32L4P/Q can be single/dual bank
2122  * if size = 1M check DBANK bit
2123  * if size = 512K check DB512K bit (same as DB1M bit)
2124  */
2125  page_size_kb = 8;
2126  num_pages = flash_size_kb / page_size_kb;
2127  stm32l4_info->bank1_sectors = num_pages;
2128  if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L4R_DBANK)) ||
2129  (!is_max_flash_size && (stm32l4_info->optr & FLASH_LRR_DB1M))) {
2130  stm32l4_info->dual_bank_mode = true;
2131  page_size_kb = 4;
2132  num_pages = flash_size_kb / page_size_kb;
2133  stm32l4_info->bank1_sectors = num_pages / 2;
2134  }
2135  break;
2136  case DEVID_STM32L55_L56XX:
2137  /* STM32L55/L56xx can be single/dual bank:
2138  * if size = 512K check DBANK bit
2139  * if size = 256K check DB256K bit
2140  *
2141  * default page size is 4kb, if DBANK = 1, the page size is 2kb.
2142  */
2143 
2144  page_size_kb = (stm32l4_info->optr & FLASH_L5_DBANK) ? 2 : 4;
2145  num_pages = flash_size_kb / page_size_kb;
2146  stm32l4_info->bank1_sectors = num_pages;
2147 
2148  if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DBANK)) ||
2149  (!is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DB256))) {
2150  stm32l4_info->dual_bank_mode = true;
2151  stm32l4_info->bank1_sectors = num_pages / 2;
2152  }
2153  break;
2154  case DEVID_STM32U53_U54XX:
2155  case DEVID_STM32U57_U58XX:
2156  case DEVID_STM32U59_U5AXX:
2157  case DEVID_STM32U5F_U5GXX:
2158  /* according to RM0456 Rev 4, Chapter 7.3.1 and 7.9.13
2159  * U53x/U54x have 512K max flash size:
2160  * 512K variants are always in DUAL BANK mode
2161  * 256K and 128K variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2162  * U57x/U58x have 2M max flash size:
2163  * 2M variants are always in DUAL BANK mode
2164  * 1M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2165  * U59x/U5Ax/U5Fx/U5Gx have 4M max flash size:
2166  * 4M variants are always in DUAL BANK mode
2167  * 2M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2168  * Note: flash banks are always contiguous
2169  */
2170 
2171  page_size_kb = 8;
2172  num_pages = flash_size_kb / page_size_kb;
2173  stm32l4_info->bank1_sectors = num_pages;
2174  if (is_max_flash_size || (stm32l4_info->optr & FLASH_U5_DUALBANK)) {
2175  stm32l4_info->dual_bank_mode = true;
2176  stm32l4_info->bank1_sectors = num_pages / 2;
2177  }
2178  break;
2179  case DEVID_STM32WBA5X:
2180  /* single bank flash */
2181  page_size_kb = 8;
2182  num_pages = flash_size_kb / page_size_kb;
2183  stm32l4_info->bank1_sectors = num_pages;
2184  break;
2185  case DEVID_STM32WB5XX:
2186  case DEVID_STM32WB3XX:
2187  /* single bank flash */
2188  page_size_kb = 4;
2189  num_pages = flash_size_kb / page_size_kb;
2190  stm32l4_info->bank1_sectors = num_pages;
2191  break;
2192  case DEVID_STM32WLE_WL5XX:
2193  /* single bank flash */
2194  page_size_kb = 2;
2195  num_pages = flash_size_kb / page_size_kb;
2196  stm32l4_info->bank1_sectors = num_pages;
2197 
2198  /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
2199  * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
2200  if (armv7m->debug_ap && armv7m->debug_ap->ap_num == 1)
2201  stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
2202  break;
2203  default:
2204  LOG_ERROR("unsupported device");
2205  return ERROR_FAIL;
2206  }
2207 
2208  /* ensure that at least there is 1 flash sector / page */
2209  if (num_pages == 0) {
2210  if (stm32l4_info->user_bank_size)
2211  LOG_ERROR("The specified flash size is less than page size");
2212 
2213  LOG_ERROR("Flash pages count cannot be zero");
2214  return ERROR_FAIL;
2215  }
2216 
2217  LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
2218 
2219  const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
2220 
2221  if (gap_size_kb != 0) {
2222  LOG_INFO("gap detected from 0x%08x to 0x%08x",
2223  STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
2224  * page_size_kb * 1024,
2225  STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
2226  * page_size_kb + gap_size_kb) * 1024 - 1);
2227  }
2228 
2229  /* number of significant bits in WRPxxR differs per device,
2230  * always right adjusted, on some devices non-implemented
2231  * bits read as '0', on others as '1' ...
2232  * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
2233  */
2234 
2235  /* use *max_flash_size* instead of actual size as the trimmed versions
2236  * certainly use the same number of bits
2237  */
2238  uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
2239 
2240  /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
2241  stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
2242  assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
2243  LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
2244 
2245  free(bank->sectors);
2246 
2247  bank->size = (flash_size_kb + gap_size_kb) * 1024;
2248  bank->num_sectors = num_pages;
2249  bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
2250  if (!bank->sectors) {
2251  LOG_ERROR("failed to allocate bank sectors");
2252  return ERROR_FAIL;
2253  }
2254 
2255  for (unsigned int i = 0; i < bank->num_sectors; i++) {
2256  bank->sectors[i].offset = i * page_size_kb * 1024;
2257  /* in dual bank configuration, if there is a gap between banks
2258  * we fix up the sector offset to consider this gap */
2259  if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
2260  bank->sectors[i].offset += gap_size_kb * 1024;
2261  bank->sectors[i].size = page_size_kb * 1024;
2262  bank->sectors[i].is_erased = -1;
2263  bank->sectors[i].is_protected = 1;
2264  }
2265 
2266  stm32l4_info->probed = true;
2267  return ERROR_OK;
2268 }
2269 
2271 {
2272  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2273  if (stm32l4_info->probed) {
2274  uint32_t optr_cur;
2275 
2276  /* save flash_regs_base */
2277  uint32_t saved_flash_regs_base = stm32l4_info->flash_regs_base;
2278 
2279  /* for devices with TrustZone, use NS flash registers to read OPTR */
2280  if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
2281  stm32l4_info->flash_regs_base &= ~STM32L5_REGS_SEC_OFFSET;
2282 
2283  /* read flash option register and re-probe if optr value is changed */
2285 
2286  /* restore saved flash_regs_base */
2287  stm32l4_info->flash_regs_base = saved_flash_regs_base;
2288 
2289  if (retval != ERROR_OK)
2290  return retval;
2291 
2292  if (stm32l4_info->optr == optr_cur)
2293  return ERROR_OK;
2294  }
2295 
2296  return stm32l4_probe(bank);
2297 }
2298 
2300 {
2301  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2302  const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
2303 
2304  if (part_info) {
2305  const uint16_t rev_id = stm32l4_info->idcode >> 16;
2306  command_print_sameline(cmd, "%s - Rev %s : 0x%04x", part_info->device_str,
2307  get_stm32l4_rev_str(bank), rev_id);
2308  if (stm32l4_info->probed)
2310  } else {
2311  command_print_sameline(cmd, "Cannot identify target as an %s device", device_families);
2312  }
2313 
2314  return ERROR_OK;
2315 }
2316 
2318 {
2319  int retval, retval2;
2320  struct target *target = bank->target;
2321  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2322 
2323  if (stm32l4_is_otp(bank)) {
2324  LOG_ERROR("cannot erase OTP memory");
2326  }
2327 
2328  uint32_t action = FLASH_MER1;
2329 
2330  if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
2331  action |= FLASH_MER2;
2332 
2333  if (target->state != TARGET_HALTED) {
2334  LOG_ERROR("Target not halted");
2335  return ERROR_TARGET_NOT_HALTED;
2336  }
2337 
2338  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2339  /* set all FLASH pages as secure */
2341  if (retval != ERROR_OK) {
2342  /* restore all FLASH pages as non-secure */
2343  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
2344  return retval;
2345  }
2346  }
2347 
2348  retval = stm32l4_unlock_reg(bank);
2349  if (retval != ERROR_OK)
2350  goto err_lock;
2351 
2352  /* mass erase flash memory */
2354  if (retval != ERROR_OK)
2355  goto err_lock;
2356 
2358  if (retval != ERROR_OK)
2359  goto err_lock;
2360 
2362  if (retval != ERROR_OK)
2363  goto err_lock;
2364 
2366 
2367 err_lock:
2369 
2370  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2371  /* restore all FLASH pages as non-secure */
2373  if (retval3 != ERROR_OK)
2374  return retval3;
2375  }
2376 
2377  if (retval != ERROR_OK)
2378  return retval;
2379 
2380  return retval2;
2381 }
2382 
2383 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
2384 {
2385  if (CMD_ARGC != 1)
2387 
2388  struct flash_bank *bank;
2389  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2390  if (retval != ERROR_OK)
2391  return retval;
2392 
2393  retval = stm32l4_mass_erase(bank);
2394  if (retval == ERROR_OK)
2395  command_print(CMD, "stm32l4x mass erase complete");
2396  else
2397  command_print(CMD, "stm32l4x mass erase failed");
2398 
2399  return retval;
2400 }
2401 
2402 COMMAND_HANDLER(stm32l4_handle_option_read_command)
2403 {
2404  if (CMD_ARGC != 2)
2406 
2407  struct flash_bank *bank;
2408  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2409  if (retval != ERROR_OK)
2410  return retval;
2411 
2412  uint32_t reg_offset, reg_addr;
2413  uint32_t value = 0;
2414 
2415  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2416  reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
2417 
2418  retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
2419  if (retval != ERROR_OK)
2420  return retval;
2421 
2422  command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
2423 
2424  return retval;
2425 }
2426 
2427 COMMAND_HANDLER(stm32l4_handle_option_write_command)
2428 {
2429  if (CMD_ARGC != 3 && CMD_ARGC != 4)
2431 
2432  struct flash_bank *bank;
2433  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2434  if (retval != ERROR_OK)
2435  return retval;
2436 
2437  uint32_t reg_offset;
2438  uint32_t value = 0;
2439  uint32_t mask = 0xFFFFFFFF;
2440 
2441  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2442  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2443 
2444  if (CMD_ARGC > 3)
2446 
2447  command_print(CMD, "%s Option written.\n"
2448  "INFO: a reset or power cycle is required "
2449  "for the new settings to take effect.", bank->driver->name);
2450 
2451  retval = stm32l4_write_option(bank, reg_offset, value, mask);
2452  return retval;
2453 }
2454 
2455 COMMAND_HANDLER(stm32l4_handle_trustzone_command)
2456 {
2457  if (CMD_ARGC < 1 || CMD_ARGC > 2)
2459 
2460  struct flash_bank *bank;
2461  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2462  if (retval != ERROR_OK)
2463  return retval;
2464 
2465  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2466  if (!(stm32l4_info->part_info->flags & F_HAS_TZ)) {
2467  LOG_ERROR("This device does not have a TrustZone");
2468  return ERROR_FAIL;
2469  }
2470 
2472  if (retval != ERROR_OK)
2473  return retval;
2474 
2476 
2477  if (CMD_ARGC == 1) {
2478  /* only display the TZEN value */
2479  LOG_INFO("Global TrustZone Security is %s", stm32l4_info->tzen ? "enabled" : "disabled");
2480  return ERROR_OK;
2481  }
2482 
2483  bool new_tzen;
2484  COMMAND_PARSE_ENABLE(CMD_ARGV[1], new_tzen);
2485 
2486  if (new_tzen == stm32l4_info->tzen) {
2487  LOG_INFO("The requested TZEN is already programmed");
2488  return ERROR_OK;
2489  }
2490 
2491  if (new_tzen) {
2492  if (stm32l4_info->rdp != RDP_LEVEL_0) {
2493  LOG_ERROR("TZEN can be set only when RDP level is 0");
2494  return ERROR_FAIL;
2495  }
2498  } else {
2499  /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2500  * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2501  if (stm32l4_info->rdp != RDP_LEVEL_1 && stm32l4_info->rdp != RDP_LEVEL_0_5) {
2502  LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2503  return ERROR_FAIL;
2504  }
2505 
2508  }
2509 
2510  if (retval != ERROR_OK)
2511  return retval;
2512 
2514 }
2515 
2516 COMMAND_HANDLER(stm32l4_handle_option_load_command)
2517 {
2518  if (CMD_ARGC != 1)
2520 
2521  struct flash_bank *bank;
2522  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2523  if (retval != ERROR_OK)
2524  return retval;
2525 
2526  retval = stm32l4_perform_obl_launch(bank);
2527  if (retval != ERROR_OK) {
2528  command_print(CMD, "stm32l4x option load failed");
2529  return retval;
2530  }
2531 
2532 
2533  command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
2534 
2535  return ERROR_OK;
2536 }
2537 
2538 COMMAND_HANDLER(stm32l4_handle_lock_command)
2539 {
2540  struct target *target = NULL;
2541 
2542  if (CMD_ARGC != 1)
2544 
2545  struct flash_bank *bank;
2546  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2547  if (retval != ERROR_OK)
2548  return retval;
2549 
2550  if (stm32l4_is_otp(bank)) {
2551  LOG_ERROR("cannot lock/unlock OTP memory");
2553  }
2554 
2555  target = bank->target;
2556 
2557  if (target->state != TARGET_HALTED) {
2558  LOG_ERROR("Target not halted");
2559  return ERROR_TARGET_NOT_HALTED;
2560  }
2561 
2562  /* set readout protection level 1 by erasing the RDP option byte */
2563  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2566  command_print(CMD, "%s failed to lock device", bank->driver->name);
2567  return ERROR_OK;
2568  }
2569 
2570  return ERROR_OK;
2571 }
2572 
2573 COMMAND_HANDLER(stm32l4_handle_unlock_command)
2574 {
2575  struct target *target = NULL;
2576 
2577  if (CMD_ARGC != 1)
2579 
2580  struct flash_bank *bank;
2581  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2582  if (retval != ERROR_OK)
2583  return retval;
2584 
2585  if (stm32l4_is_otp(bank)) {
2586  LOG_ERROR("cannot lock/unlock OTP memory");
2588  }
2589 
2590  target = bank->target;
2591 
2592  if (target->state != TARGET_HALTED) {
2593  LOG_ERROR("Target not halted");
2594  return ERROR_TARGET_NOT_HALTED;
2595  }
2596 
2597  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2600  command_print(CMD, "%s failed to unlock device", bank->driver->name);
2601  return ERROR_OK;
2602  }
2603 
2604  return ERROR_OK;
2605 }
2606 
2607 COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
2608 {
2609  if (CMD_ARGC < 1 || CMD_ARGC > 2)
2611 
2612  struct flash_bank *bank;
2613  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2614  if (retval != ERROR_OK)
2615  return retval;
2616 
2617  if (stm32l4_is_otp(bank)) {
2618  LOG_ERROR("OTP memory does not have write protection areas");
2620  }
2621 
2622  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2623  enum stm32_bank_id dev_bank_id = STM32_ALL_BANKS;
2624  if (CMD_ARGC == 2) {
2625  if (strcmp(CMD_ARGV[1], "bank1") == 0)
2626  dev_bank_id = STM32_BANK1;
2627  else if (strcmp(CMD_ARGV[1], "bank2") == 0)
2628  dev_bank_id = STM32_BANK2;
2629  else
2631  }
2632 
2633  if (dev_bank_id == STM32_BANK2) {
2634  if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
2635  LOG_ERROR("this device has no second bank");
2636  return ERROR_FAIL;
2637  } else if (!stm32l4_info->dual_bank_mode) {
2638  LOG_ERROR("this device is configured in single bank mode");
2639  return ERROR_FAIL;
2640  }
2641  }
2642 
2643  int ret;
2644  unsigned int n_wrp, i;
2645  struct stm32l4_wrp wrpxy[4];
2646 
2647  ret = stm32l4_get_all_wrpxy(bank, dev_bank_id, wrpxy, &n_wrp);
2648  if (ret != ERROR_OK)
2649  return ret;
2650 
2651  /* use bitmap and range helpers to better describe protected areas */
2652  DECLARE_BITMAP(pages, bank->num_sectors);
2653  bitmap_zero(pages, bank->num_sectors);
2654 
2655  for (i = 0; i < n_wrp; i++) {
2656  if (wrpxy[i].used) {
2657  for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
2658  set_bit(p, pages);
2659  }
2660  }
2661 
2662  /* we have at most 'n_wrp' WRP areas */
2663  struct range ranges[n_wrp];
2664  unsigned int ranges_count = 0;
2665 
2666  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
2667 
2668  if (ranges_count > 0) {
2669  /* pretty-print the protected ranges */
2670  char *ranges_str = range_print_alloc(ranges, ranges_count);
2671  command_print(CMD, "protected areas: %s", ranges_str);
2672  free(ranges_str);
2673  } else
2674  command_print(CMD, "no protected areas");
2675 
2676  return ERROR_OK;
2677 }
2678 
2679 COMMAND_HANDLER(stm32l4_handle_otp_command)
2680 {
2681  if (CMD_ARGC != 2)
2683 
2684  struct flash_bank *bank;
2685  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2686  if (retval != ERROR_OK)
2687  return retval;
2688 
2689  if (!stm32l4_is_otp(bank)) {
2690  command_print(CMD, "the specified bank is not an OTP memory");
2691  return ERROR_FAIL;
2692  }
2693  if (strcmp(CMD_ARGV[1], "enable") == 0)
2694  stm32l4_otp_enable(bank, true);
2695  else if (strcmp(CMD_ARGV[1], "disable") == 0)
2696  stm32l4_otp_enable(bank, false);
2697  else if (strcmp(CMD_ARGV[1], "show") == 0)
2698  command_print(CMD, "OTP memory bank #%d is %s for write commands.",
2699  bank->bank_number, stm32l4_otp_is_enabled(bank) ? "enabled" : "disabled");
2700  else
2702 
2703  return ERROR_OK;
2704 }
2705 
2706 static const struct command_registration stm32l4_exec_command_handlers[] = {
2707  {
2708  .name = "lock",
2709  .handler = stm32l4_handle_lock_command,
2710  .mode = COMMAND_EXEC,
2711  .usage = "bank_id",
2712  .help = "Lock entire flash device.",
2713  },
2714  {
2715  .name = "unlock",
2716  .handler = stm32l4_handle_unlock_command,
2717  .mode = COMMAND_EXEC,
2718  .usage = "bank_id",
2719  .help = "Unlock entire protected flash device.",
2720  },
2721  {
2722  .name = "mass_erase",
2723  .handler = stm32l4_handle_mass_erase_command,
2724  .mode = COMMAND_EXEC,
2725  .usage = "bank_id",
2726  .help = "Erase entire flash device.",
2727  },
2728  {
2729  .name = "option_read",
2730  .handler = stm32l4_handle_option_read_command,
2731  .mode = COMMAND_EXEC,
2732  .usage = "bank_id reg_offset",
2733  .help = "Read & Display device option bytes.",
2734  },
2735  {
2736  .name = "option_write",
2737  .handler = stm32l4_handle_option_write_command,
2738  .mode = COMMAND_EXEC,
2739  .usage = "bank_id reg_offset value [mask]",
2740  .help = "Write device option bit fields with provided value.",
2741  },
2742  {
2743  .name = "trustzone",
2744  .handler = stm32l4_handle_trustzone_command,
2745  .mode = COMMAND_EXEC,
2746  .usage = "<bank_id> [enable|disable]",
2747  .help = "Configure TrustZone security",
2748  },
2749  {
2750  .name = "wrp_info",
2751  .handler = stm32l4_handle_wrp_info_command,
2752  .mode = COMMAND_EXEC,
2753  .usage = "bank_id [bank1|bank2]",
2754  .help = "list the protected areas using WRP",
2755  },
2756  {
2757  .name = "option_load",
2758  .handler = stm32l4_handle_option_load_command,
2759  .mode = COMMAND_EXEC,
2760  .usage = "bank_id",
2761  .help = "Force re-load of device options (will cause device reset).",
2762  },
2763  {
2764  .name = "otp",
2765  .handler = stm32l4_handle_otp_command,
2766  .mode = COMMAND_EXEC,
2767  .usage = "<bank_id> <enable|disable|show>",
2768  .help = "OTP (One Time Programmable) memory write enable/disable",
2769  },
2771 };
2772 
2773 static const struct command_registration stm32l4_command_handlers[] = {
2774  {
2775  .name = "stm32l4x",
2776  .mode = COMMAND_ANY,
2777  .help = "stm32l4x flash command group",
2778  .usage = "",
2780  },
2782 };
2783 
2784 const struct flash_driver stm32l4x_flash = {
2785  .name = "stm32l4x",
2786  .commands = stm32l4_command_handlers,
2787  .flash_bank_command = stm32l4_flash_bank_command,
2788  .erase = stm32l4_erase,
2789  .protect = stm32l4_protect,
2790  .write = stm32l4_write,
2791  .read = default_flash_read,
2792  .probe = stm32l4_probe,
2793  .auto_probe = stm32l4_auto_probe,
2794  .erase_check = default_flash_blank_check,
2795  .protect_check = stm32l4_protect_check,
2796  .info = get_stm32l4_info,
2797  .free_driver_priv = default_flash_free_driver_priv,
2798 };
void init_reg_param(struct reg_param *param, const char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:38
@ PARAM_OUT
Definition: algorithm.h:16
@ PARAM_IN_OUT
Definition: algorithm.h:17
@ ARM_MODE_THREAD
Definition: arm.h:94
This defines formats and data structures used to talk to ADIv5 entities.
static struct armv7m_common * target_to_armv7m_safe(struct target *target)
Definition: armv7m.h:278
#define ARMV7M_COMMON_MAGIC
Definition: armv7m.h:224
Support functions to access arbitrary bits in a byte array.
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
static int test_bit(unsigned int nr, const volatile unsigned long *addr)
test_bit - Determine whether a bit is set
Definition: bits.h:73
static void bitmap_zero(unsigned long *dst, unsigned int nbits)
bitmap_zero - Clears all the bits in memory
Definition: bits.h:36
static void set_bit(unsigned int nr, volatile unsigned long *addr)
set_bit - Set a bit in memory
Definition: bits.h:60
static void clear_bit(unsigned int nr, volatile unsigned long *addr)
clear_bit - Clear a bit in memory
Definition: bits.h:47
#define DECLARE_BITMAP(name, bits)
Definition: bits.h:29
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:352
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:375
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:118
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:400
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
#define COMMAND_PARSE_ENABLE(in, out)
parses an enable/disable command argument
Definition: command.h:531
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:440
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:251
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:402
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
static enum cortex_m_impl_part cortex_m_get_impl_part(struct target *target)
Definition: cortex_m.h:333
@ CORTEX_M0P_PARTNO
Definition: cortex_m.h:54
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
uint32_t size
Size of dw_spi_transaction::buffer.
Definition: dw-spi-helper.h:4
uint32_t buffer_size
Size of dw_spi_program::buffer.
Definition: dw-spi-helper.h:5
uint32_t address
Starting address. Sector aligned.
Definition: dw-spi-helper.h:0
#define FLASH_PG
Definition: em357.c:44
#define KEY2
Definition: em357.c:68
#define FLASH_PER
Definition: em357.c:45
#define FLASH_BSY
Definition: em357.c:55
#define FLASH_LOCK
Definition: em357.c:50
#define FLASH_STRT
Definition: em357.c:49
#define KEY1
Definition: em357.c:67
uint8_t bank
Definition: esirisc.c:135
int mask
Definition: esirisc.c:1740
#define ERROR_FLASH_OPER_UNSUPPORTED
Definition: flash/common.h:36
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
#define ERROR_FLASH_DST_OUT_OF_BANK
Definition: flash/common.h:31
struct flash_sector * alloc_block_array(uint32_t offset, uint32_t size, unsigned int num_blocks)
Allocate and fill an array of sectors or protection blocks.
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
void alive_sleep(uint64_t ms)
Definition: log.c:467
#define ERROR_NOT_IMPLEMENTED
Definition: log.h:178
#define LOG_WARNING(expr ...)
Definition: log.h:130
#define ERROR_FAIL
Definition: log.h:174
#define LOG_ERROR(expr ...)
Definition: log.h:133
#define LOG_INFO(expr ...)
Definition: log.h:127
#define LOG_DEBUG(expr ...)
Definition: log.h:110
#define ERROR_OK
Definition: log.h:168
#define FLASH_ERROR
Definition: msp432.h:72
struct rtt_control ctrl
Control block.
Definition: rtt/rtt.c:25
struct rtt_source source
Definition: rtt/rtt.c:23
#define FLASH_OBL_LAUNCH
Definition: stm32f1x.c:72
#define FLASH_WRPERR
Definition: stm32f2x.c:157
#define OPTKEY2
Definition: stm32f2x.c:178
#define FLASH_MER1
Definition: stm32f2x.c:142
#define OPTKEY1
Definition: stm32f2x.c:177
stm32l4_rdp
Definition: stm32l4x.c:178
@ RDP_LEVEL_1
Definition: stm32l4x.c:181
@ RDP_LEVEL_2
Definition: stm32l4x.c:182
@ RDP_LEVEL_0_5
Definition: stm32l4x.c:180
@ RDP_LEVEL_0
Definition: stm32l4x.c:179
static const struct stm32l4_rev stm32g05_g06xx_revs[]
Definition: stm32l4x.c:321
static const struct stm32l4_rev stm32c071xx_revs[]
Definition: stm32l4x.c:313
static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id, struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
Definition: stm32l4x.c:1236
static int stm32l4_protect_check(struct flash_bank *bank)
Definition: stm32l4x.c:1316
#define FLASH_ERASE_TIMEOUT
Definition: stm32l4x.c:137
static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, enum stm32l4_flash_reg_index reg_idx, int offset)
Definition: stm32l4x.c:1216
static const struct stm32l4_rev stm32l43_l44xx_revs[]
Definition: stm32l4x.c:296
static const struct stm32l4_rev stm32u53_u54xx_revs[]
Definition: stm32l4x.c:378
static const struct stm32l4_rev stm32u59_u5axx_revs[]
Definition: stm32l4x.c:387
#define F_QUAD_WORD_PROG
Definition: stm32l4x.c:154
static const struct command_registration stm32l4_exec_command_handlers[]
Definition: stm32l4x.c:2706
#define F_NONE
Definition: stm32l4x.c:142
static int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
Definition: stm32l4x.c:961
static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:185
#define F_USE_ALL_WRPXX
Definition: stm32l4x.c:147
stm32l4_flash_reg_index
Definition: stm32l4x.c:161
@ STM32_FLASH_SR_INDEX
Definition: stm32l4x.c:165
@ STM32_FLASH_CR_WLK_INDEX
Definition: stm32l4x.c:169
@ STM32_FLASH_ACR_INDEX
Definition: stm32l4x.c:162
@ STM32_FLASH_OPTR_INDEX
Definition: stm32l4x.c:170
@ STM32_FLASH_WRP1AR_INDEX
Definition: stm32l4x.c:171
@ STM32_FLASH_CR_INDEX
Definition: stm32l4x.c:166
@ STM32_FLASH_WRP2BR_INDEX
Definition: stm32l4x.c:174
@ STM32_FLASH_OPTKEYR_INDEX
Definition: stm32l4x.c:164
@ STM32_FLASH_WRP1BR_INDEX
Definition: stm32l4x.c:172
@ STM32_FLASH_KEYR_INDEX
Definition: stm32l4x.c:163
@ STM32_FLASH_WRP2AR_INDEX
Definition: stm32l4x.c:173
@ STM32_FLASH_REG_INDEX_NUM
Definition: stm32l4x.c:175
static const struct stm32l4_rev stm32c09xx_revs[]
Definition: stm32l4x.c:317
#define F_HAS_TZ
Definition: stm32l4x.c:149
static int stm32l4_perform_obl_launch(struct flash_bank *bank)
Definition: stm32l4x.c:1131
static const struct stm32l4_part_info stm32l4_parts[]
Definition: stm32l4x.c:415
static char * range_print_alloc(struct range *ranges, unsigned int ranges_count)
Definition: stm32l4x.c:853
static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
Definition: stm32l4x.c:1824
static const struct stm32l4_rev stm32g47_g48xx_revs[]
Definition: stm32l4x.c:357
static int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
Definition: stm32l4x.c:949
static bool stm32l4_otp_is_enabled(struct flash_bank *bank)
Definition: stm32l4x.c:901
#define F_HAS_L5_FLASH_REGS
Definition: stm32l4x.c:151
static const char * get_stm32l4_bank_type_str(struct flash_bank *bank)
Definition: stm32l4x.c:1887
static bool stm32l4_is_otp(struct flash_bank *bank)
Definition: stm32l4x.c:876
static int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
Definition: stm32l4x.c:1055
static int range_print_one(struct range *range, char *str)
Definition: stm32l4x.c:845
static const struct stm32l4_rev stm32g03_g04xx_revs[]
Definition: stm32l4x.c:341
static const struct stm32l4_rev stm32c01xx_revs[]
Definition: stm32l4x.c:301
#define F_HAS_DUAL_BANK
Definition: stm32l4x.c:144
static const char * device_families
Definition: stm32l4x.c:290
stm32_bank_id
Definition: stm32l4x.c:274
@ STM32_BANK1
Definition: stm32l4x.c:275
@ STM32_BANK2
Definition: stm32l4x.c:276
@ STM32_ALL_BANKS
Definition: stm32l4x.c:277
static const struct stm32l4_rev stm32u57_u58xx_revs[]
Definition: stm32l4x.c:382
static const struct command_registration stm32l4_command_handlers[]
Definition: stm32l4x.c:2773
static const struct stm32l4_rev stm32l45_l46xx_revs[]
Definition: stm32l4x.c:333
static int stm32l4_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1340
static const struct stm32l4_rev stm32l4p_l4qxx_revs[]
Definition: stm32l4x.c:366
static const struct stm32l4_rev stm32l41_l42xx_revs[]
Definition: stm32l4x.c:337
static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
Definition: stm32l4x.c:882
static const struct stm32l4_rev stm32l47_l48xx_revs[]
Definition: stm32l4x.c:292
static const struct stm32l4_rev stm32l4r_l4sxx_revs[]
Definition: stm32l4x.c:361
static const struct stm32l4_rev stm32c05xx_revs[]
Definition: stm32l4x.c:309
static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
Definition: stm32l4x.c:1168
static const struct stm32l4_rev stm32l55_l56xx_revs[]
Definition: stm32l4x.c:370
static const struct stm32l4_rev stm32wb1xx_revs[]
Definition: stm32l4x.c:399
static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
Definition: stm32l4x.c:973
static const struct stm32l4_rev stm32wba5x_revs[]
Definition: stm32l4x.c:395
static int stm32l4_mass_erase(struct flash_bank *bank)
Definition: stm32l4x.c:2317
static const char * get_stm32l4_rev_str(struct flash_bank *bank)
Definition: stm32l4x.c:1873
static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
Definition: stm32l4x.c:2299
COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
Definition: stm32l4x.c:2383
static const struct stm32l4_rev stm32_g07_g08xx_revs[]
Definition: stm32l4x.c:325
static const struct stm32l4_rev stm32g43_g44xx_revs[]
Definition: stm32l4x.c:353
static const struct stm32l4_rev stm32c03xx_revs[]
Definition: stm32l4x.c:305
static uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
Definition: stm32l4x.c:936
static const struct stm32l4_rev stm32wle_wl5xx_revs[]
Definition: stm32l4x.c:411
static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1418
FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
Definition: stm32l4x.c:795
static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
set all FLASH_SECBB registers to the same value
Definition: stm32l4x.c:1013
static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1713
static const struct stm32l4_rev stm32g49_g4axx_revs[]
Definition: stm32l4x.c:374
const struct flash_driver stm32l4x_flash
Definition: stm32l4x.c:2784
static int stm32l4_probe(struct flash_bank *bank)
Definition: stm32l4x.c:1896
static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:223
static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1669
static int stm32l4_read_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t *value)
Definition: stm32l4x.c:954
static const struct stm32l4_rev stm32u0xx_revs[]
Definition: stm32l4x.c:349
static int stm32l4_unlock_option_reg(struct flash_bank *bank)
Definition: stm32l4x.c:1098
static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:198
#define F_WRP_HAS_LOCK
Definition: stm32l4x.c:157
static int stm32l4_unlock_reg(struct flash_bank *bank)
Definition: stm32l4x.c:1062
static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
Definition: stm32l4x.c:1303
static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
Definition: stm32l4x.c:907
static const struct stm32l4_rev stm32wb3xx_revs[]
Definition: stm32l4x.c:407
#define FLASH_WRITE_TIMEOUT
Definition: stm32l4x.c:138
static const struct stm32l4_rev stm32wb5xx_revs[]
Definition: stm32l4x.c:403
static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits, struct range *ranges, unsigned int *ranges_count)
Definition: stm32l4x.c:824
static const struct stm32l4_rev stm32u5f_u5gxx_revs[]
Definition: stm32l4x.c:391
static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:210
static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1544
static int stm32l4_write_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t value)
Definition: stm32l4x.c:966
static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1509
static uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index)
Definition: stm32l4x.c:942
static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
Definition: stm32l4x.c:1289
static const struct stm32l4_rev stm32l49_l4axx_revs[]
Definition: stm32l4x.c:329
static int stm32l4_auto_probe(struct flash_bank *bank)
Definition: stm32l4x.c:2270
static const struct stm32l4_rev stm32g0b_g0cxx_revs[]
Definition: stm32l4x.c:345
#define DEVID_STM32G03_G04XX
Definition: stm32l4x.h:104
#define DEVID_STM32L55_L56XX
Definition: stm32l4x.h:110
#define DBGMCU_IDCODE_G0
Definition: stm32l4x.h:83
#define DEVID_STM32G0B_G0CXX
Definition: stm32l4x.h:105
#define FLASH_L5_DB256
Definition: stm32l4x.h:68
#define FLASH_SECBB_SECURE
Definition: stm32l4x.h:79
#define DBGMCU_IDCODE_L5
Definition: stm32l4x.h:85
#define FLASH_G0_DUAL_BANK
Definition: stm32l4x.h:62
#define STM32_FLASH_S_BANK_BASE
Definition: stm32l4x.h:125
#define DEVID_STM32G49_G4AXX
Definition: stm32l4x.h:112
#define DEVID_STM32WBA5X
Definition: stm32l4x.h:116
#define DEVID_STM32WB1XX
Definition: stm32l4x.h:118
#define DEVID_STM32C03XX
Definition: stm32l4x.h:96
#define FLASH_OPTSTRT
Definition: stm32l4x.h:30
#define FLASH_SECBB2(X)
Definition: stm32l4x.h:77
#define DEVID_STM32U53_U54XX
Definition: stm32l4x.h:97
#define DEVID_STM32L4R_L4SXX
Definition: stm32l4x.h:108
#define UID64_IDS
Definition: stm32l4x.h:87
#define FLASH_L5_DBANK
Definition: stm32l4x.h:67
#define FLASH_L4_DUAL_BANK
Definition: stm32l4x.h:64
#define FLASH_PAGE_SHIFT
Definition: stm32l4x.h:25
#define DEVID_STM32G47_G48XX
Definition: stm32l4x.h:107
#define FLASH_U5_DUALBANK
Definition: stm32l4x.h:69
#define DEVID_STM32U5F_U5GXX
Definition: stm32l4x.h:111
#define STM32_FLASH_BANK_BASE
Definition: stm32l4x.h:124
#define FLASH_G4_DUAL_BANK
Definition: stm32l4x.h:63
#define DEVID_STM32L47_L48XX
Definition: stm32l4x.h:91
#define DEVID_STM32G07_G08XX
Definition: stm32l4x.h:100
#define DEVID_STM32C071XX
Definition: stm32l4x.h:117
#define DEVID_STM32WB5XX
Definition: stm32l4x.h:119
#define DEVID_STM32U59_U5AXX
Definition: stm32l4x.h:113
#define DEVID_STM32L49_L4AXX
Definition: stm32l4x.h:101
#define DEVID_STM32L43_L44XX
Definition: stm32l4x.h:92
#define FLASH_RDP_MASK
Definition: stm32l4x.h:61
#define DEVID_STM32L41_L42XX
Definition: stm32l4x.h:103
#define DEVID_STM32U073_U083XX
Definition: stm32l4x.h:115
#define DEVID_STM32WLE_WL5XX
Definition: stm32l4x.h:121
#define FLASH_L4R_DBANK
Definition: stm32l4x.h:65
#define DEVID_STM32G05_G06XX
Definition: stm32l4x.h:98
#define LDR_STACK_SIZE
Definition: stm32l4x.h:131
#define DEVID_STM32U031XX
Definition: stm32l4x.h:99
#define FLASH_OPTLOCK
Definition: stm32l4x.h:34
#define DEVID_STM32WB3XX
Definition: stm32l4x.h:120
#define DEVID_STM32C09XX
Definition: stm32l4x.h:95
#define FLASH_WRPXYR_UNLOCK
Definition: stm32l4x.h:73
#define FLASH_TZEN
Definition: stm32l4x.h:70
#define DEVID_STM32G43_G44XX
Definition: stm32l4x.h:106
#define UID64_IDS_STM32WL
Definition: stm32l4x.h:88
#define FLASH_BSY2
Definition: stm32l4x.h:39
#define FLASH_SECBB_NON_SECURE
Definition: stm32l4x.h:80
#define STM32L5_REGS_SEC_OFFSET
Definition: stm32l4x.h:128
#define FLASH_SECBB1(X)
Definition: stm32l4x.h:76
#define FLASH_BKER_G0
Definition: stm32l4x.h:27
#define DEVID_STM32U57_U58XX
Definition: stm32l4x.h:114
#define DBGMCU_IDCODE_L4_G4
Definition: stm32l4x.h:84
#define DEVID_STM32L4P_L4QXX
Definition: stm32l4x.h:109
#define FLASH_LRR_DB1M
Definition: stm32l4x.h:66
#define DEVID_STM32C05XX
Definition: stm32l4x.h:94
#define FLASH_BKER
Definition: stm32l4x.h:26
#define DEVID_STM32C01XX
Definition: stm32l4x.h:93
#define DEVID_STM32L45_L46XX
Definition: stm32l4x.h:102
#define FLASH_MER2
Definition: stm32l4x.h:28
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
Definition: arm_adi_v5.h:261
unsigned int common_magic
Definition: armv7m.h:299
enum arm_mode core_mode
Definition: armv7m.h:301
struct adiv5_ap * debug_ap
Definition: armv7m.h:234
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
const char * name
Definition: command.h:234
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
Describes the geometry and status of a single flash sector within a flash bank.
Definition: nor/core.h:28
uint32_t offset
Bus offset from start of the flash chip (in bytes).
Definition: nor/core.h:30
uint32_t size
Number of bytes in this flash sector.
Definition: nor/core.h:32
unsigned int start
Definition: stm32l4x.c:820
unsigned int end
Definition: stm32l4x.c:821
unsigned int bank1_sectors
Definition: stm32l4x.c:257
uint32_t wrpxxr_mask
Definition: stm32l4x.c:264
uint32_t user_bank_size
Definition: stm32l4x.c:260
const uint32_t * flash_regs
Definition: stm32l4x.c:267
uint32_t flash_regs_base
Definition: stm32l4x.c:266
enum stm32l4_rdp rdp
Definition: stm32l4x.c:269
uint32_t idcode
Definition: stm32l4x.c:256
uint32_t cr_bker_mask
Definition: stm32l4x.c:262
uint32_t data_width
Definition: stm32l4x.c:261
const struct stm32l4_part_info * part_info
Definition: stm32l4x.c:265
uint32_t sr_bsy_mask
Definition: stm32l4x.c:263
const uint32_t otp_size
Definition: stm32l4x.c:251
const struct stm32l4_rev * revs
Definition: stm32l4x.c:244
const char * device_str
Definition: stm32l4x.c:243
const uint32_t fsize_addr
Definition: stm32l4x.c:249
const uint32_t flash_regs_base
Definition: stm32l4x.c:248
const uint32_t flags
Definition: stm32l4x.c:247
const uint32_t otp_base
Definition: stm32l4x.c:250
const size_t num_revs
Definition: stm32l4x.c:245
const uint16_t max_flash_size_kb
Definition: stm32l4x.c:246
const char * str
Definition: stm32l4x.c:238
const uint16_t rev
Definition: stm32l4x.c:237
uint8_t stack[LDR_STACK_SIZE]
Definition: stm32l4x.h:140
bool used
Definition: stm32l4x.c:283
enum stm32l4_flash_reg_index reg_idx
Definition: stm32l4x.c:281
int offset
Definition: stm32l4x.c:286
uint32_t value
Definition: stm32l4x.c:282
Definition: target.h:119
enum target_state state
Definition: target.h:160
Definition: psoc6.c:83
target_addr_t address
Definition: target.h:89
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
Definition: target.c:361
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2351
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1275
uint32_t target_get_working_area_avail(struct target *target)
Definition: target.c:2174
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2070
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2650
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2128
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:1976
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
Definition: target.c:2583
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
Definition: target.c:940
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2559
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:786
static bool target_was_examined(const struct target *target)
Definition: target.h:432
#define ERROR_TARGET_INVALID
Definition: target.h:783
@ TARGET_HALTED
Definition: target.h:58
#define ERROR_TARGET_NOT_EXAMINED
Definition: target.h:793
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:790
#define ERROR_TARGET_FAILURE
Definition: target.h:787
#define TARGET_ADDR_FMT
Definition: types.h:342
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
#define NULL
Definition: usb.h:16
uint8_t status[4]
Definition: vdebug.c:17
uint8_t cmd
Definition: vdebug.c:1
uint8_t offset[4]
Definition: vdebug.c:9
uint8_t count[4]
Definition: vdebug.c:22