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mips64.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /*
4  * Support for processors implementing MIPS64 instruction set
5  *
6  * Copyright (C) 2014 by Andrey Sidorov <anysidorov@gmail.com>
7  * Copyright (C) 2014 by Aleksey Kuleshov <rndfax@yandex.ru>
8  * Copyright (C) 2014 by Antony Pavlov <antonynpavlov@gmail.com>
9  * Copyright (C) 2014 by Peter Mamonov <pmamonov@gmail.com>
10  *
11  * Based on the work of:
12  * Copyright (C) 2008 by Spencer Oliver
13  * Copyright (C) 2008 by David T.L. Wong
14  * Copyright (C) 2010 by Konstantin Kostyukhin, Nikolay Shmyrev
15  */
16 
17 #ifdef HAVE_CONFIG_H
18 #include "config.h"
19 #endif
20 
21 #include "mips64.h"
22 
23 static const struct {
24  unsigned int id;
25  const char *name;
26  enum reg_type type;
27  const char *group;
28  const char *feature;
29  int flag;
30 } mips64_regs[] = {
31  { 0, "r0", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
32  { 1, "r1", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
33  { 2, "r2", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
34  { 3, "r3", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
35  { 4, "r4", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
36  { 5, "r5", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
37  { 6, "r6", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
38  { 7, "r7", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
39  { 8, "r8", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
40  { 9, "r9", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
41  { 10, "r10", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
42  { 11, "r11", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
43  { 12, "r12", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
44  { 13, "r13", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
45  { 14, "r14", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
46  { 15, "r15", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
47  { 16, "r16", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
48  { 17, "r17", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
49  { 18, "r18", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
50  { 19, "r19", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
51  { 20, "r20", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
52  { 21, "r21", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
53  { 22, "r22", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
54  { 23, "r23", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
55  { 24, "r24", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
56  { 25, "r25", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
57  { 26, "r26", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
58  { 27, "r27", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
59  { 28, "r28", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
60  { 29, "r29", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
61  { 30, "r30", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
62  { 31, "r31", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
63  { 32, "lo", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
64  { 33, "hi", REG_TYPE_UINT64, NULL, "org.gnu.gdb.mips.cpu", 0 },
65  { MIPS64_NUM_CORE_REGS + 0, "pc", REG_TYPE_UINT64, NULL,
66  "org.gnu.gdb.mips.cpu", 0 },
67  { MIPS64_NUM_CORE_REGS + 1, "Random", REG_TYPE_UINT32, NULL,
68  "org.gnu.gdb.mips.cp0", 0 },
69  { MIPS64_NUM_CORE_REGS + 2, "Entrylo_0", REG_TYPE_UINT64, NULL,
70  "org.gnu.gdb.mips.cp0", 0 },
71  { MIPS64_NUM_CORE_REGS + 3, "Entrylo_1", REG_TYPE_UINT64, NULL,
72  "org.gnu.gdb.mips.cp0", 0 },
73  { MIPS64_NUM_CORE_REGS + 4, "Context", REG_TYPE_UINT64, NULL,
74  "org.gnu.gdb.mips.cp0", 0 },
75  { MIPS64_NUM_CORE_REGS + 5, "Pagemask", REG_TYPE_UINT32, NULL,
76  "org.gnu.gdb.mips.cp0", 0 },
77  { MIPS64_NUM_CORE_REGS + 6, "Wired", REG_TYPE_UINT32, NULL,
78  "org.gnu.gdb.mips.cp0", 0 },
79  { MIPS64_NUM_CORE_REGS + 7, "badvaddr", REG_TYPE_UINT64, NULL,
80  "org.gnu.gdb.mips.cp0", 0 },
81  { MIPS64_NUM_CORE_REGS + 8, "Count", REG_TYPE_UINT32, NULL,
82  "org.gnu.gdb.mips.cp0", 0 },
83  { MIPS64_NUM_CORE_REGS + 9, "EntryHi", REG_TYPE_UINT64, NULL,
84  "org.gnu.gdb.mips.cp0", 0 },
85  { MIPS64_NUM_CORE_REGS + 10, "Compare", REG_TYPE_UINT32, NULL,
86  "org.gnu.gdb.mips.cp0", 0 },
87  { MIPS64_NUM_CORE_REGS + 11, "status", REG_TYPE_UINT32, NULL,
88  "org.gnu.gdb.mips.cp0", 0 },
89  { MIPS64_NUM_CORE_REGS + 12, "cause", REG_TYPE_UINT32, NULL,
90  "org.gnu.gdb.mips.cp0", 0 },
91  { MIPS64_NUM_CORE_REGS + 13, "EPC", REG_TYPE_UINT64, NULL,
92  "org.gnu.gdb.mips.cp0", 0 },
93  { MIPS64_NUM_CORE_REGS + 14, "PrID", REG_TYPE_UINT32, NULL,
94  "org.gnu.gdb.mips.cp0", 0 },
95  { MIPS64_NUM_CORE_REGS + 15, "Config", REG_TYPE_UINT32, NULL,
96  "org.gnu.gdb.mips.cp0", 0 },
97  { MIPS64_NUM_CORE_REGS + 16, "LLA", REG_TYPE_UINT32, NULL,
98  "org.gnu.gdb.mips.cp0", 0 },
99  { MIPS64_NUM_CORE_REGS + 17, "WatchLo0", REG_TYPE_UINT64, NULL,
100  "org.gnu.gdb.mips.cp0", 0 },
101  { MIPS64_NUM_CORE_REGS + 18, "WatchLo1", REG_TYPE_UINT64, NULL,
102  "org.gnu.gdb.mips.cp0", 0 },
103  { MIPS64_NUM_CORE_REGS + 19, "WatchHi0", REG_TYPE_UINT32, NULL,
104  "org.gnu.gdb.mips.cp0", 0 },
105  { MIPS64_NUM_CORE_REGS + 20, "WatchHi1", REG_TYPE_UINT32, NULL,
106  "org.gnu.gdb.mips.cp0", 0 },
107  { MIPS64_NUM_CORE_REGS + 21, "Xcontext", REG_TYPE_UINT64, NULL,
108  "org.gnu.gdb.mips.cp0", 0 },
109  { MIPS64_NUM_CORE_REGS + 22, "ChipMemCtrl", REG_TYPE_UINT32, NULL,
110  "org.gnu.gdb.mips.cp0", 0 },
111  { MIPS64_NUM_CORE_REGS + 23, "Debug", REG_TYPE_UINT32, NULL,
112  "org.gnu.gdb.mips.cp0", 0 },
113  { MIPS64_NUM_CORE_REGS + 24, "Perfcount, sel=0", REG_TYPE_UINT32, NULL,
114  "org.gnu.gdb.mips.cp0", 0 },
115  { MIPS64_NUM_CORE_REGS + 25, "Perfcount, sel=1", REG_TYPE_UINT64, NULL,
116  "org.gnu.gdb.mips.cp0", 0 },
117  { MIPS64_NUM_CORE_REGS + 26, "Perfcount, sel=2", REG_TYPE_UINT32, NULL,
118  "org.gnu.gdb.mips.cp0", 0 },
119  { MIPS64_NUM_CORE_REGS + 27, "Perfcount, sel=3", REG_TYPE_UINT64, NULL,
120  "org.gnu.gdb.mips.cp0", 0 },
121  { MIPS64_NUM_CORE_REGS + 28, "ECC", REG_TYPE_UINT32, NULL,
122  "org.gnu.gdb.mips.cp0", 0 },
123  { MIPS64_NUM_CORE_REGS + 29, "CacheErr", REG_TYPE_UINT32, NULL,
124  "org.gnu.gdb.mips.cp0", 0 },
125  { MIPS64_NUM_CORE_REGS + 30, "TagLo", REG_TYPE_UINT32, NULL,
126  "org.gnu.gdb.mips.cp0", 0 },
127  { MIPS64_NUM_CORE_REGS + 31, "TagHi", REG_TYPE_UINT32, NULL,
128  "org.gnu.gdb.mips.cp0", 0 },
129  { MIPS64_NUM_CORE_REGS + 32, "DataHi", REG_TYPE_UINT64, NULL,
130  "org.gnu.gdb.mips.cp0", 0 },
131  { MIPS64_NUM_CORE_REGS + 33, "EEPC", REG_TYPE_UINT64, NULL,
132  "org.gnu.gdb.mips.cp0", 0 },
133  { MIPS64_NUM_CORE_C0_REGS + 0, "f0", REG_TYPE_IEEE_DOUBLE, NULL,
134  "org.gnu.gdb.mips.fpu", 0 },
135  { MIPS64_NUM_CORE_C0_REGS + 1, "f1", REG_TYPE_IEEE_DOUBLE, NULL,
136  "org.gnu.gdb.mips.fpu", 0 },
137  { MIPS64_NUM_CORE_C0_REGS + 2, "f2", REG_TYPE_IEEE_DOUBLE, NULL,
138  "org.gnu.gdb.mips.fpu", 0 },
139  { MIPS64_NUM_CORE_C0_REGS + 3, "f3", REG_TYPE_IEEE_DOUBLE, NULL,
140  "org.gnu.gdb.mips.fpu", 0 },
141  { MIPS64_NUM_CORE_C0_REGS + 4, "f4", REG_TYPE_IEEE_DOUBLE, NULL,
142  "org.gnu.gdb.mips.fpu", 0 },
143  { MIPS64_NUM_CORE_C0_REGS + 5, "f5", REG_TYPE_IEEE_DOUBLE, NULL,
144  "org.gnu.gdb.mips.fpu", 0 },
145  { MIPS64_NUM_CORE_C0_REGS + 6, "f6", REG_TYPE_IEEE_DOUBLE, NULL,
146  "org.gnu.gdb.mips.fpu", 0 },
147  { MIPS64_NUM_CORE_C0_REGS + 7, "f7", REG_TYPE_IEEE_DOUBLE, NULL,
148  "org.gnu.gdb.mips.fpu", 0 },
149  { MIPS64_NUM_CORE_C0_REGS + 8, "f8", REG_TYPE_IEEE_DOUBLE, NULL,
150  "org.gnu.gdb.mips.fpu", 0 },
151  { MIPS64_NUM_CORE_C0_REGS + 9, "f9", REG_TYPE_IEEE_DOUBLE, NULL,
152  "org.gnu.gdb.mips.fpu", 0 },
153  { MIPS64_NUM_CORE_C0_REGS + 10, "f10", REG_TYPE_IEEE_DOUBLE, NULL,
154  "org.gnu.gdb.mips.fpu", 0 },
155  { MIPS64_NUM_CORE_C0_REGS + 11, "f11", REG_TYPE_IEEE_DOUBLE, NULL,
156  "org.gnu.gdb.mips.fpu", 0 },
157  { MIPS64_NUM_CORE_C0_REGS + 12, "f12", REG_TYPE_IEEE_DOUBLE, NULL,
158  "org.gnu.gdb.mips.fpu", 0 },
159  { MIPS64_NUM_CORE_C0_REGS + 13, "f13", REG_TYPE_IEEE_DOUBLE, NULL,
160  "org.gnu.gdb.mips.fpu", 0 },
161  { MIPS64_NUM_CORE_C0_REGS + 14, "f14", REG_TYPE_IEEE_DOUBLE, NULL,
162  "org.gnu.gdb.mips.fpu", 0 },
163  { MIPS64_NUM_CORE_C0_REGS + 15, "f15", REG_TYPE_IEEE_DOUBLE, NULL,
164  "org.gnu.gdb.mips.fpu", 0 },
165  { MIPS64_NUM_CORE_C0_REGS + 16, "f16", REG_TYPE_IEEE_DOUBLE, NULL,
166  "org.gnu.gdb.mips.fpu", 0 },
167  { MIPS64_NUM_CORE_C0_REGS + 17, "f17", REG_TYPE_IEEE_DOUBLE, NULL,
168  "org.gnu.gdb.mips.fpu", 0 },
169  { MIPS64_NUM_CORE_C0_REGS + 18, "f18", REG_TYPE_IEEE_DOUBLE, NULL,
170  "org.gnu.gdb.mips.fpu", 0 },
171  { MIPS64_NUM_CORE_C0_REGS + 19, "f19", REG_TYPE_IEEE_DOUBLE, NULL,
172  "org.gnu.gdb.mips.fpu", 0 },
173  { MIPS64_NUM_CORE_C0_REGS + 20, "f20", REG_TYPE_IEEE_DOUBLE, NULL,
174  "org.gnu.gdb.mips.fpu", 0 },
175  { MIPS64_NUM_CORE_C0_REGS + 21, "f21", REG_TYPE_IEEE_DOUBLE, NULL,
176  "org.gnu.gdb.mips.fpu", 0 },
177  { MIPS64_NUM_CORE_C0_REGS + 22, "f22", REG_TYPE_IEEE_DOUBLE, NULL,
178  "org.gnu.gdb.mips.fpu", 0 },
179  { MIPS64_NUM_CORE_C0_REGS + 23, "f23", REG_TYPE_IEEE_DOUBLE, NULL,
180  "org.gnu.gdb.mips.fpu", 0 },
181  { MIPS64_NUM_CORE_C0_REGS + 24, "f24", REG_TYPE_IEEE_DOUBLE, NULL,
182  "org.gnu.gdb.mips.fpu", 0 },
183  { MIPS64_NUM_CORE_C0_REGS + 25, "f25", REG_TYPE_IEEE_DOUBLE, NULL,
184  "org.gnu.gdb.mips.fpu", 0 },
185  { MIPS64_NUM_CORE_C0_REGS + 26, "f26", REG_TYPE_IEEE_DOUBLE, NULL,
186  "org.gnu.gdb.mips.fpu", 0 },
187  { MIPS64_NUM_CORE_C0_REGS + 27, "f27", REG_TYPE_IEEE_DOUBLE, NULL,
188  "org.gnu.gdb.mips.fpu", 0 },
189  { MIPS64_NUM_CORE_C0_REGS + 28, "f28", REG_TYPE_IEEE_DOUBLE, NULL,
190  "org.gnu.gdb.mips.fpu", 0 },
191  { MIPS64_NUM_CORE_C0_REGS + 29, "f29", REG_TYPE_IEEE_DOUBLE, NULL,
192  "org.gnu.gdb.mips.fpu", 0 },
193  { MIPS64_NUM_CORE_C0_REGS + 30, "f30", REG_TYPE_IEEE_DOUBLE, NULL,
194  "org.gnu.gdb.mips.fpu", 0 },
195  { MIPS64_NUM_CORE_C0_REGS + 31, "f31", REG_TYPE_IEEE_DOUBLE, NULL,
196  "org.gnu.gdb.mips.fpu", 0 },
197  { MIPS64_NUM_CORE_C0_REGS + 32, "fcsr", REG_TYPE_INT, "float",
198  "org.gnu.gdb.mips.fpu", 0 },
199  { MIPS64_NUM_CORE_C0_REGS + 33, "fir", REG_TYPE_INT, "float",
200  "org.gnu.gdb.mips.fpu", 0 },
201  { MIPS64_NUM_CORE_C0_REGS + 34, "fconfig", REG_TYPE_INT, "float",
202  "org.gnu.gdb.mips.fpu", 0 },
203  { MIPS64_NUM_CORE_C0_REGS + 35, "fccr", REG_TYPE_INT, "float",
204  "org.gnu.gdb.mips.fpu", 0 },
205  { MIPS64_NUM_CORE_C0_REGS + 36, "fexr", REG_TYPE_INT, "float",
206  "org.gnu.gdb.mips.fpu", 0 },
207  { MIPS64_NUM_CORE_C0_REGS + 37, "fenr", REG_TYPE_INT, "float",
208  "org.gnu.gdb.mips.fpu", 0 },
209 };
210 
211 static int reg_type2size(enum reg_type type)
212 {
213  switch (type) {
214  case REG_TYPE_UINT32:
215  case REG_TYPE_INT:
216  return 32;
217  case REG_TYPE_UINT64:
218  case REG_TYPE_IEEE_DOUBLE:
219  return 64;
220  default:
221  return 64;
222  }
223 }
224 
225 static int mips64_get_core_reg(struct reg *reg)
226 {
227  struct mips64_core_reg *mips64_reg = reg->arch_info;
228  struct target *target = mips64_reg->target;
229  struct mips64_common *mips64_target = target->arch_info;
230 
231  if (target->state != TARGET_HALTED)
232  return ERROR_TARGET_NOT_HALTED;
233 
234  return mips64_target->read_core_reg(target, mips64_reg->num);
235 }
236 
237 static int mips64_set_core_reg(struct reg *reg, uint8_t *buf)
238 {
239  struct mips64_core_reg *mips64_reg = reg->arch_info;
240  struct target *target = mips64_reg->target;
241  uint64_t value = buf_get_u64(buf, 0, 64);
242 
243  if (target->state != TARGET_HALTED)
244  return ERROR_TARGET_NOT_HALTED;
245 
246  buf_set_u64(reg->value, 0, 64, value);
247  reg->dirty = true;
248  reg->valid = true;
249 
250  return ERROR_OK;
251 }
252 
253 static int mips64_read_core_reg(struct target *target, int num)
254 {
255  uint64_t reg_value;
256 
257  /* get pointers to arch-specific information */
258  struct mips64_common *mips64 = target->arch_info;
259 
260  if ((num < 0) || (num >= MIPS64_NUM_REGS))
261  return ERROR_COMMAND_ARGUMENT_INVALID;
262 
263  reg_value = mips64->core_regs[num];
264  buf_set_u64(mips64->core_cache->reg_list[num].value, 0, 64, reg_value);
265  mips64->core_cache->reg_list[num].valid = true;
266  mips64->core_cache->reg_list[num].dirty = false;
267 
268  return ERROR_OK;
269 }
270 
271 static int mips64_write_core_reg(struct target *target, int num)
272 {
273  uint64_t reg_value;
274 
275  /* get pointers to arch-specific information */
276  struct mips64_common *mips64 = target->arch_info;
277 
278  if ((num < 0) || (num >= MIPS64_NUM_REGS))
279  return ERROR_COMMAND_ARGUMENT_INVALID;
280 
281  reg_value = buf_get_u64(mips64->core_cache->reg_list[num].value, 0, 64);
282  mips64->core_regs[num] = reg_value;
283  LOG_DEBUG("write core reg %i value 0x%" PRIx64, num, reg_value);
284  mips64->core_cache->reg_list[num].valid = true;
285  mips64->core_cache->reg_list[num].dirty = false;
286 
287  return ERROR_OK;
288 }
289 
290 int mips64_invalidate_core_regs(struct target *target)
291 {
292  /* get pointers to arch-specific information */
293  struct mips64_common *mips64 = target->arch_info;
294  unsigned int i;
295 
296  for (i = 0; i < mips64->core_cache->num_regs; i++) {
297  mips64->core_cache->reg_list[i].valid = false;
298  mips64->core_cache->reg_list[i].dirty = false;
299  }
300 
301  return ERROR_OK;
302 }
303 
304 
305 int mips64_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
306  int *reg_list_size, enum target_register_class reg_class)
307 {
308  /* get pointers to arch-specific information */
309  struct mips64_common *mips64 = target->arch_info;
310  register int i;
311 
312  /* include floating point registers */
313  *reg_list_size = MIPS64_NUM_REGS;
314  *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
315 
316  for (i = 0; i < MIPS64_NUM_REGS; i++)
317  (*reg_list)[i] = &mips64->core_cache->reg_list[i];
318 
319  return ERROR_OK;
320 }
321 
322 int mips64_save_context(struct target *target)
323 {
324  int retval;
325  struct mips64_common *mips64 = target->arch_info;
326  struct mips_ejtag *ejtag_info = &mips64->ejtag_info;
327 
328  retval = mips64_pracc_read_regs(ejtag_info, mips64->core_regs);
329  if (retval != ERROR_OK)
330  return retval;
331 
332  for (unsigned int i = 0; i < MIPS64_NUM_REGS; i++)
333  retval = mips64->read_core_reg(target, i);
334 
335  return retval;
336 }
337 
338 int mips64_restore_context(struct target *target)
339 {
340  struct mips64_common *mips64 = target->arch_info;
341  struct mips_ejtag *ejtag_info = &mips64->ejtag_info;
342 
343  for (unsigned int i = 0; i < MIPS64_NUM_REGS; i++) {
344  if (mips64->core_cache->reg_list[i].dirty)
345  mips64->write_core_reg(target, i);
346  }
347 
348  return mips64_pracc_write_regs(ejtag_info, mips64->core_regs);
349 }
350 
351 int mips64_arch_state(struct target *target)
352 {
353  struct mips64_common *mips64 = target->arch_info;
354  struct reg *pc = &mips64->core_cache->reg_list[MIPS64_PC];
355 
356  if (mips64->common_magic != MIPS64_COMMON_MAGIC) {
357  LOG_ERROR("BUG: called for a non-MIPS64 target");
358  exit(-1);
359  }
360 
361  LOG_USER("target halted due to %s, pc: 0x%" PRIx64,
362  debug_reason_name(target), buf_get_u64(pc->value, 0, 64));
363 
364  return ERROR_OK;
365 }
366 
367 static const struct reg_arch_type mips64_reg_type = {
368  .get = mips64_get_core_reg,
369  .set = mips64_set_core_reg,
370 };
371 
372 int mips64_build_reg_cache(struct target *target)
373 {
374  /* get pointers to arch-specific information */
375  struct mips64_common *mips64 = target->arch_info;
376  struct reg_cache **cache_p, *cache;
377  struct mips64_core_reg *arch_info = NULL;
378  struct reg *reg_list = NULL;
379  unsigned int i;
380 
381  cache = calloc(1, sizeof(*cache));
382  if (!cache) {
383  LOG_ERROR("unable to allocate cache");
384  return ERROR_FAIL;
385  }
386 
387  reg_list = calloc(MIPS64_NUM_REGS, sizeof(*reg_list));
388  if (!reg_list) {
389  LOG_ERROR("unable to allocate reg_list");
390  goto alloc_fail;
391  }
392 
393  arch_info = calloc(MIPS64_NUM_REGS, sizeof(*arch_info));
394  if (!arch_info) {
395  LOG_ERROR("unable to allocate arch_info");
396  goto alloc_fail;
397  }
398 
399  for (i = 0; i < MIPS64_NUM_REGS; i++) {
400  struct mips64_core_reg *a = &arch_info[i];
401  struct reg *r = &reg_list[i];
402 
403  r->arch_info = &arch_info[i];
404  r->caller_save = true; /* gdb defaults to true */
405  r->exist = true;
406  r->feature = &a->feature;
407  r->feature->name = mips64_regs[i].feature;
408  r->group = mips64_regs[i].group;
409  r->name = mips64_regs[i].name;
410  r->number = i;
411  r->reg_data_type = &a->reg_data_type;
412  r->reg_data_type->type = mips64_regs[i].type;
413  r->size = reg_type2size(mips64_regs[i].type);
414  r->type = &mips64_reg_type;
415  r->value = &a->value[0];
416 
417  a->mips64_common = mips64;
418  a->num = mips64_regs[i].id;
419  a->target = target;
420  }
421 
422  cache->name = "mips64 registers";
423  cache->reg_list = reg_list;
424  cache->num_regs = MIPS64_NUM_REGS;
425 
426  cache_p = register_get_last_cache_p(&target->reg_cache);
427  (*cache_p) = cache;
428 
429  mips64->core_cache = cache;
430 
431  return ERROR_OK;
432 
433 alloc_fail:
434  free(cache);
435  free(reg_list);
436  free(arch_info);
437 
438  return ERROR_FAIL;
439 }
440 
441 int mips64_init_arch_info(struct target *target, struct mips64_common *mips64,
442  struct jtag_tap *tap)
443 {
444  mips64->bp_scanned = false;
445  mips64->common_magic = MIPS64_COMMON_MAGIC;
446  mips64->data_break_list = NULL;
447  mips64->ejtag_info.tap = tap;
448  mips64->fast_data_area = NULL;
449  mips64->mips64mode32 = false;
450  mips64->read_core_reg = mips64_read_core_reg;
451  mips64->write_core_reg = mips64_write_core_reg;
452 
453  return ERROR_OK;
454 }
455 
456 int mips64_run_algorithm(struct target *target, int num_mem_params,
457  struct mem_param *mem_params, int num_reg_params,
458  struct reg_param *reg_params, target_addr_t entry_point,
459  target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
460 {
461  /* TODO */
462  return ERROR_OK;
463 }
464 
465 int mips64_examine(struct target *target)
466 {
467  struct mips64_common *mips64 = target->arch_info;
468 
469  if (target_was_examined(target))
470  return ERROR_OK;
471 
472  /* TODO: why we do not do mips64_configure_break_unit() here? */
473  mips64->bp_scanned = false;
474  mips64->num_data_bpoints = 0;
475  mips64->num_data_bpoints_avail = 0;
476  mips64->num_inst_bpoints = 0;
477  mips64->num_inst_bpoints_avail = 0;
478 
479  return ERROR_OK;
480 }
481 
482 static int mips64_configure_i_break_unit(struct target *target)
483 {
484  /* get pointers to arch-specific information */
485  struct mips64_common *mips64 = target->arch_info;
486  struct mips64_comparator *ibl;
487  uint64_t bpinfo;
488  int retval;
489  int i;
490 
491  /* get number of inst breakpoints */
492  retval = target_read_u64(target, EJTAG64_V25_IBS, &bpinfo);
493  if (retval != ERROR_OK)
494  return retval;
495 
496  mips64->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
497  mips64->num_inst_bpoints_avail = mips64->num_inst_bpoints;
498  ibl = calloc(mips64->num_inst_bpoints, sizeof(*ibl));
499  if (!ibl) {
500  LOG_ERROR("unable to allocate inst_break_list");
501  return ERROR_FAIL;
502  }
503 
504  for (i = 0; i < mips64->num_inst_bpoints; i++)
505  ibl[i].reg_address = EJTAG64_V25_IBA0 + (0x100 * i);
506 
507  mips64->inst_break_list = ibl;
508  /* clear IBIS reg */
509  retval = target_write_u64(target, EJTAG64_V25_IBS, 0);
510  if (retval != ERROR_OK)
511  return retval;
512 
513  return ERROR_OK;
514 }
515 
516 static int mips64_configure_d_break_unit(struct target *target)
517 {
518  struct mips64_common *mips64 = target->arch_info;
519  struct mips64_comparator *dbl;
520  uint64_t bpinfo;
521  int retval;
522  int i;
523 
524  /* get number of data breakpoints */
525  retval = target_read_u64(target, EJTAG64_V25_DBS, &bpinfo);
526  if (retval != ERROR_OK)
527  return retval;
528 
529  mips64->num_data_bpoints = (bpinfo >> 24) & 0x0F;
530  mips64->num_data_bpoints_avail = mips64->num_data_bpoints;
531 
532  dbl = calloc(mips64->num_data_bpoints, sizeof(*dbl));
533 
534  if (!dbl) {
535  LOG_ERROR("unable to allocate data_break_list");
536  return ERROR_FAIL;
537  }
538 
539  for (i = 0; i < mips64->num_data_bpoints; i++)
540  dbl[i].reg_address = EJTAG64_V25_DBA0 + (0x100 * i);
541 
542  mips64->data_break_list = dbl;
543 
544  /* clear DBIS reg */
545  retval = target_write_u64(target, EJTAG64_V25_DBS, 0);
546  if (retval != ERROR_OK)
547  return retval;
548 
549  return ERROR_OK;
550 }
551 
552 int mips64_configure_break_unit(struct target *target)
553 {
554  struct mips64_common *mips64 = target->arch_info;
555  uint64_t dcr;
556  int retval;
557 
558  if (mips64->bp_scanned)
559  return ERROR_OK;
560 
561  /* get info about breakpoint support */
562  retval = target_read_u64(target, EJTAG64_DCR, &dcr);
563  if (retval != ERROR_OK)
564  return retval;
565 
566  if (dcr & EJTAG64_DCR_IB) {
567  retval = mips64_configure_i_break_unit(target);
568  if (retval != ERROR_OK)
569  return retval;
570  }
571 
572  if (dcr & EJTAG64_DCR_DB) {
573  retval = mips64_configure_d_break_unit(target);
574  if (retval != ERROR_OK)
575  return retval;
576  }
577 
578  LOG_DEBUG("DCR 0x%" PRIx64 " numinst %i numdata %i", dcr,
579  mips64->num_inst_bpoints, mips64->num_data_bpoints);
580 
581  mips64->bp_scanned = true;
582 
583  return ERROR_OK;
584 }
585 
586 int mips64_enable_interrupts(struct target *target, bool enable)
587 {
588  int retval;
589  bool update = false;
590  uint64_t dcr;
591 
592  /* read debug control register */
593  retval = target_read_u64(target, EJTAG64_DCR, &dcr);
594  if (retval != ERROR_OK)
595  return retval;
596 
597  if (enable) {
598  if (!(dcr & EJTAG64_DCR_INTE)) {
599  /* enable interrupts */
600  dcr |= EJTAG64_DCR_INTE;
601  update = true;
602  }
603  } else {
604  if (dcr & EJTAG64_DCR_INTE) {
605  /* disable interrupts */
606  dcr &= ~(uint64_t)EJTAG64_DCR_INTE;
607  update = true;
608  }
609  }
610 
611  if (update) {
612  retval = target_write_u64(target, EJTAG64_DCR, dcr);
613  if (retval != ERROR_OK)
614  return retval;
615  }
616 
617  return ERROR_OK;
618 }
buf_get_u64
static uint64_t buf_get_u64(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 64-bit word.
Definition: binarybuffer.h:134
buf_set_u64
static void buf_set_u64(uint8_t *_buffer, unsigned int first, unsigned int num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:65
ERROR_COMMAND_ARGUMENT_INVALID
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:407
LOG_USER
#define LOG_USER(expr ...)
Definition: log.h:150
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:188
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:147
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:124
ERROR_OK
#define ERROR_OK
Definition: log.h:182
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int mips64_invalidate_core_regs(struct target *target)
Definition: mips64.c:290
mips64_regs
static const struct @118 mips64_regs[]
mips64_set_core_reg
static int mips64_set_core_reg(struct reg *reg, uint8_t *buf)
Definition: mips64.c:237
mips64_read_core_reg
static int mips64_read_core_reg(struct target *target, int num)
Definition: mips64.c:253
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static int mips64_get_core_reg(struct reg *reg)
Definition: mips64.c:225
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static int reg_type2size(enum reg_type type)
Definition: mips64.c:211
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int mips64_init_arch_info(struct target *target, struct mips64_common *mips64, struct jtag_tap *tap)
Definition: mips64.c:441
mips64_restore_context
int mips64_restore_context(struct target *target)
Definition: mips64.c:338
mips64_examine
int mips64_examine(struct target *target)
Definition: mips64.c:465
mips64_enable_interrupts
int mips64_enable_interrupts(struct target *target, bool enable)
Definition: mips64.c:586
mips64_configure_d_break_unit
static int mips64_configure_d_break_unit(struct target *target)
Definition: mips64.c:516
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int mips64_arch_state(struct target *target)
Definition: mips64.c:351
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const char * group
Definition: mips64.c:27
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int mips64_configure_break_unit(struct target *target)
Definition: mips64.c:552
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int mips64_build_reg_cache(struct target *target)
Definition: mips64.c:372
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int mips64_save_context(struct target *target)
Definition: mips64.c:322
mips64_configure_i_break_unit
static int mips64_configure_i_break_unit(struct target *target)
Definition: mips64.c:482
mips64_run_algorithm
int mips64_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Definition: mips64.c:456
name
const char * name
Definition: mips64.c:25
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static int mips64_write_core_reg(struct target *target, int num)
Definition: mips64.c:271
type
enum reg_type type
Definition: mips64.c:26
id
unsigned int id
Definition: mips64.c:24
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static const struct reg_arch_type mips64_reg_type
Definition: mips64.c:367
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int flag
Definition: mips64.c:29
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int mips64_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: mips64.c:305
feature
const char * feature
Definition: mips64.c:28
MIPS64_NUM_CORE_REGS
#define MIPS64_NUM_CORE_REGS
Definition: mips64.h:65
MIPS64_NUM_CORE_C0_REGS
#define MIPS64_NUM_CORE_C0_REGS
Definition: mips64.h:73
MIPS64_COMMON_MAGIC
#define MIPS64_COMMON_MAGIC
Definition: mips64.h:22
MIPS64_PC
#define MIPS64_PC
Definition: mips64.h:75
MIPS64_NUM_REGS
#define MIPS64_NUM_REGS
Definition: mips64.h:69
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int mips64_pracc_write_regs(struct mips_ejtag *ejtag_info, uint64_t *regs)
Definition: mips64_pracc.c:827
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int mips64_pracc_read_regs(struct mips_ejtag *ejtag_info, uint64_t *regs)
Definition: mips64_pracc.c:1037
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#define EJTAG64_DCR_DB
Definition: mips_ejtag.h:180
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#define EJTAG64_V25_DBS
Definition: mips_ejtag.h:185
EJTAG64_V25_DBA0
#define EJTAG64_V25_DBA0
Definition: mips_ejtag.h:184
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#define EJTAG64_DCR_INTE
Definition: mips_ejtag.h:182
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#define EJTAG64_DCR
Definition: mips_ejtag.h:178
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#define EJTAG64_DCR_IB
Definition: mips_ejtag.h:181
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#define EJTAG64_V25_IBS
Definition: mips_ejtag.h:187
EJTAG64_V25_IBA0
#define EJTAG64_V25_IBA0
Definition: mips_ejtag.h:186
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struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
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Definition: register.h:19
REG_TYPE_INT
@ REG_TYPE_INT
Definition: register.h:21
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@ REG_TYPE_IEEE_DOUBLE
Definition: register.h:37
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@ REG_TYPE_UINT32
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@ REG_TYPE_UINT64
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Definition: jtag.h:101
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Definition: mips64.h:83
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int(* read_core_reg)(struct target *target, int num)
Definition: mips64.h:102
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Definition: mips64.h:95
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Definition: mips64.h:91
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Definition: mips64.h:93
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Definition: mips64.h:99
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Definition: mips64.h:84
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Definition: mips64.h:103
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Definition: mips64.h:87
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struct mips_ejtag ejtag_info
Definition: mips64.h:88
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uint64_t core_regs[MIPS64_NUM_REGS]
Definition: mips64.h:89
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Definition: mips64.h:77
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Definition: mips64.h:80
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Definition: mips64.h:108
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Definition: mips64.h:113
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Definition: mips64.h:111
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Definition: mips64.h:110
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Definition: mips64.h:109
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Definition: mips64.h:114
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Definition: mips_ejtag.h:205
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Definition: mips_ejtag.h:206
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Definition: register.h:151
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Definition: register.h:152
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Definition: register.h:144
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Definition: target.c:2541
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Definition: target.h:113
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#define ERROR_TARGET_NOT_HALTED
Definition: target.h:817
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static bool target_was_examined(const struct target *target)
Definition: target.h:443
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:58
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#define NULL
Definition: usb.h:16