OpenOCD
fm3.c
Go to the documentation of this file.
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2011 by Marc Willam, Holger Wech *
5  * openOCD.fseu(AT)de.fujitsu.com *
6  * Copyright (C) 2011 Ronny Strutz *
7  * *
8  * Copyright (C) 2013 Nemui Trinomius *
9  * nemuisan_kawausogasuki@live.jp *
10  ***************************************************************************/
11 
12 #ifdef HAVE_CONFIG_H
13 #include "config.h"
14 #endif
15 
16 #include "imp.h"
17 #include <helper/binarybuffer.h>
18 #include <target/algorithm.h>
19 #include <target/armv7m.h>
20 
21 #define FLASH_DQ6 0x40 /* Data toggle flag bit (TOGG) position */
22 #define FLASH_DQ5 0x20 /* Time limit exceeding flag bit (TLOV) position */
23 
24 enum fm3_variant {
25  MB9BFXX1, /* Flash Type '1' */
26  MB9BFXX2,
27  MB9BFXX3,
28  MB9BFXX4,
29  MB9BFXX5,
30  MB9BFXX6,
31  MB9BFXX7,
32  MB9BFXX8,
33 
34  MB9AFXX1, /* Flash Type '2' */
35  MB9AFXX2,
36  MB9AFXX3,
37  MB9AFXX4,
38  MB9AFXX5,
39  MB9AFXX6,
40  MB9AFXX7,
41  MB9AFXX8,
42 };
43 
44 enum fm3_flash_type {
45  FM3_NO_FLASH_TYPE = 0,
46  FM3_FLASH_TYPE1 = 1,
47  FM3_FLASH_TYPE2 = 2
48 };
49 
50 struct fm3_flash_bank {
51  enum fm3_variant variant;
52  enum fm3_flash_type flashtype;
53  bool probed;
54 };
55 
56 FLASH_BANK_COMMAND_HANDLER(fm3_flash_bank_command)
57 {
58  struct fm3_flash_bank *fm3_info;
59 
60  if (CMD_ARGC < 6)
61  return ERROR_COMMAND_SYNTAX_ERROR;
62 
63  fm3_info = malloc(sizeof(struct fm3_flash_bank));
64  bank->driver_priv = fm3_info;
65 
66  /* Flash type '1' */
67  if (strcmp(CMD_ARGV[5], "mb9bfxx1.cpu") == 0) {
68  fm3_info->variant = MB9BFXX1;
69  fm3_info->flashtype = FM3_FLASH_TYPE1;
70  } else if (strcmp(CMD_ARGV[5], "mb9bfxx2.cpu") == 0) {
71  fm3_info->variant = MB9BFXX2;
72  fm3_info->flashtype = FM3_FLASH_TYPE1;
73  } else if (strcmp(CMD_ARGV[5], "mb9bfxx3.cpu") == 0) {
74  fm3_info->variant = MB9BFXX3;
75  fm3_info->flashtype = FM3_FLASH_TYPE1;
76  } else if (strcmp(CMD_ARGV[5], "mb9bfxx4.cpu") == 0) {
77  fm3_info->variant = MB9BFXX4;
78  fm3_info->flashtype = FM3_FLASH_TYPE1;
79  } else if (strcmp(CMD_ARGV[5], "mb9bfxx5.cpu") == 0) {
80  fm3_info->variant = MB9BFXX5;
81  fm3_info->flashtype = FM3_FLASH_TYPE1;
82  } else if (strcmp(CMD_ARGV[5], "mb9bfxx6.cpu") == 0) {
83  fm3_info->variant = MB9BFXX6;
84  fm3_info->flashtype = FM3_FLASH_TYPE1;
85  } else if (strcmp(CMD_ARGV[5], "mb9bfxx7.cpu") == 0) {
86  fm3_info->variant = MB9BFXX7;
87  fm3_info->flashtype = FM3_FLASH_TYPE1;
88  } else if (strcmp(CMD_ARGV[5], "mb9bfxx8.cpu") == 0) {
89  fm3_info->variant = MB9BFXX8;
90  fm3_info->flashtype = FM3_FLASH_TYPE1;
91  } else if (strcmp(CMD_ARGV[5], "mb9afxx1.cpu") == 0) { /* Flash type '2' */
92  fm3_info->variant = MB9AFXX1;
93  fm3_info->flashtype = FM3_FLASH_TYPE2;
94  } else if (strcmp(CMD_ARGV[5], "mb9afxx2.cpu") == 0) {
95  fm3_info->variant = MB9AFXX2;
96  fm3_info->flashtype = FM3_FLASH_TYPE2;
97  } else if (strcmp(CMD_ARGV[5], "mb9afxx3.cpu") == 0) {
98  fm3_info->variant = MB9AFXX3;
99  fm3_info->flashtype = FM3_FLASH_TYPE2;
100  } else if (strcmp(CMD_ARGV[5], "mb9afxx4.cpu") == 0) {
101  fm3_info->variant = MB9AFXX4;
102  fm3_info->flashtype = FM3_FLASH_TYPE2;
103  } else if (strcmp(CMD_ARGV[5], "mb9afxx5.cpu") == 0) {
104  fm3_info->variant = MB9AFXX5;
105  fm3_info->flashtype = FM3_FLASH_TYPE2;
106  } else if (strcmp(CMD_ARGV[5], "mb9afxx6.cpu") == 0) {
107  fm3_info->variant = MB9AFXX6;
108  fm3_info->flashtype = FM3_FLASH_TYPE2;
109  } else if (strcmp(CMD_ARGV[5], "mb9afxx7.cpu") == 0) {
110  fm3_info->variant = MB9AFXX7;
111  fm3_info->flashtype = FM3_FLASH_TYPE2;
112  } else if (strcmp(CMD_ARGV[5], "mb9afxx8.cpu") == 0) {
113  fm3_info->variant = MB9AFXX8;
114  fm3_info->flashtype = FM3_FLASH_TYPE2;
115  }
116 
117  /* unknown Flash type */
118  else {
119  LOG_ERROR("unknown fm3 variant: %s", CMD_ARGV[5]);
120  free(fm3_info);
121  return ERROR_FLASH_BANK_INVALID;
122  }
123 
124  fm3_info->probed = false;
125 
126  return ERROR_OK;
127 }
128 
129 /* Data polling algorithm */
130 static int fm3_busy_wait(struct target *target, uint32_t offset, int timeout_ms)
131 {
132  int retval = ERROR_OK;
133  uint8_t state1, state2;
134  int ms = 0;
135 
136  /* While(1) loop exit via "break" and "return" on error */
137  while (1) {
138  /* dummy-read - see flash manual */
139  retval = target_read_u8(target, offset, &state1);
140  if (retval != ERROR_OK)
141  return retval;
142 
143  /* Data polling 1 */
144  retval = target_read_u8(target, offset, &state1);
145  if (retval != ERROR_OK)
146  return retval;
147 
148  /* Data polling 2 */
149  retval = target_read_u8(target, offset, &state2);
150  if (retval != ERROR_OK)
151  return retval;
152 
153  /* Flash command finished via polled data equal? */
154  if ((state1 & FLASH_DQ6) == (state2 & FLASH_DQ6))
155  break;
156  /* Timeout Flag? */
157  else if (state1 & FLASH_DQ5) {
158  /* Retry data polling */
159 
160  /* Data polling 1 */
161  retval = target_read_u8(target, offset, &state1);
162  if (retval != ERROR_OK)
163  return retval;
164 
165  /* Data polling 2 */
166  retval = target_read_u8(target, offset, &state2);
167  if (retval != ERROR_OK)
168  return retval;
169 
170  /* Flash command finished via polled data equal? */
171  if ((state1 & FLASH_DQ6) != (state2 & FLASH_DQ6))
172  return ERROR_FLASH_OPERATION_FAILED;
173 
174  /* finish anyway */
175  break;
176  }
177  usleep(1000);
178  ++ms;
179 
180  /* Polling time exceeded? */
181  if (ms > timeout_ms) {
182  LOG_ERROR("Polling data reading timed out!");
183  return ERROR_FLASH_OPERATION_FAILED;
184  }
185  }
186 
187  if (retval == ERROR_OK)
188  LOG_DEBUG("fm3_busy_wait(%" PRIx32 ") needs about %d ms", offset, ms);
189 
190  return retval;
191 }
192 
193 static int fm3_erase(struct flash_bank *bank, unsigned int first,
194  unsigned int last)
195 {
196  struct fm3_flash_bank *fm3_info = bank->driver_priv;
197  struct target *target = bank->target;
198  int retval = ERROR_OK;
199  uint32_t u32_dummy_read;
200  int odd;
201  uint32_t u32_flash_type;
202  uint32_t u32_flash_seq_address1;
203  uint32_t u32_flash_seq_address2;
204 
205  struct working_area *write_algorithm;
206  struct reg_param reg_params[3];
207  struct armv7m_algorithm armv7m_info;
208 
209  u32_flash_type = (uint32_t) fm3_info->flashtype;
210 
211  if (u32_flash_type == FM3_FLASH_TYPE1) {
212  u32_flash_seq_address1 = 0x00001550;
213  u32_flash_seq_address2 = 0x00000AA8;
214  } else if (u32_flash_type == FM3_FLASH_TYPE2) {
215  u32_flash_seq_address1 = 0x00000AA8;
216  u32_flash_seq_address2 = 0x00000554;
217  } else {
218  LOG_ERROR("Flash/Device type unknown!");
219  return ERROR_FLASH_OPERATION_FAILED;
220  }
221 
222  if (target->state != TARGET_HALTED) {
223  LOG_ERROR("Target not halted");
224  return ERROR_TARGET_NOT_HALTED;
225  }
226 
227  /* RAMCODE used for fm3 Flash sector erase: */
228  /* R0 keeps Flash Sequence address 1 (u32FlashSeq1) */
229  /* R1 keeps Flash Sequence address 2 (u32FlashSeq2) */
230  /* R2 keeps Flash Offset address (ofs) */
231  static const uint8_t fm3_flash_erase_sector_code[] = {
232  /* *(uint16_t*)u32FlashSeq1 = 0xAA; */
233  0xAA, 0x24, /* MOVS R4, #0xAA */
234  0x04, 0x80, /* STRH R4, [R0, #0] */
235  /* *(uint16_t*)u32FlashSeq2 = 0x55; */
236  0x55, 0x23, /* MOVS R3, #0x55 */
237  0x0B, 0x80, /* STRH R3, [R1, #0] */
238  /* *(uint16_t*)u32FlashSeq1 = 0x80; */
239  0x80, 0x25, /* MOVS R5, #0x80 */
240  0x05, 0x80, /* STRH R5, [R0, #0] */
241  /* *(uint16_t*)u32FlashSeq1 = 0xAA; */
242  0x04, 0x80, /* STRH R4, [R0, #0] */
243  /* *(uint16_t*)u32FlashSeq2 = 0x55; */
244  0x0B, 0x80, /* STRH R3, [R1, #0] */
245  /* Sector_Erase Command (0x30) */
246  /* *(uint16_t*)ofs = 0x30; */
247  0x30, 0x20, /* MOVS R0, #0x30 */
248  0x10, 0x80, /* STRH R0, [R2, #0] */
249  /* End Code */
250  0x00, 0xBE, /* BKPT #0 */
251  };
252 
253  LOG_INFO("Fujitsu MB9[A/B]FXXX: Sector Erase ... (%u to %u)", first, last);
254 
255  /* disable HW watchdog */
256  retval = target_write_u32(target, 0x40011C00, 0x1ACCE551);
257  if (retval != ERROR_OK)
258  return retval;
259 
260  retval = target_write_u32(target, 0x40011C00, 0xE5331AAE);
261  if (retval != ERROR_OK)
262  return retval;
263 
264  retval = target_write_u32(target, 0x40011008, 0x00000000);
265  if (retval != ERROR_OK)
266  return retval;
267 
268  /* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash access) */
269  retval = target_write_u32(target, 0x40000000, 0x0001);
270  if (retval != ERROR_OK)
271  return retval;
272 
273  /* dummy read of FASZR */
274  retval = target_read_u32(target, 0x40000000, &u32_dummy_read);
275  if (retval != ERROR_OK)
276  return retval;
277 
278  /* allocate working area with flash sector erase code */
279  if (target_alloc_working_area(target, sizeof(fm3_flash_erase_sector_code),
280  &write_algorithm) != ERROR_OK) {
281  LOG_WARNING("no working area available, can't do block memory writes");
282  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
283  }
284  retval = target_write_buffer(target, write_algorithm->address,
285  sizeof(fm3_flash_erase_sector_code), fm3_flash_erase_sector_code);
286  if (retval != ERROR_OK)
287  return retval;
288 
289  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
290  armv7m_info.core_mode = ARM_MODE_THREAD;
291 
292  init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* u32_flash_seq_address1 */
293  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* u32_flash_seq_address2 */
294  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* offset */
295 
296  /* write code buffer and use Flash sector erase code within fm3 */
297  for (unsigned int sector = first ; sector <= last ; sector++) {
298  uint32_t offset = bank->sectors[sector].offset;
299 
300  for (odd = 0; odd < 2 ; odd++) {
301  if (odd)
302  offset += 4;
303 
304  buf_set_u32(reg_params[0].value, 0, 32, u32_flash_seq_address1);
305  buf_set_u32(reg_params[1].value, 0, 32, u32_flash_seq_address2);
306  buf_set_u32(reg_params[2].value, 0, 32, offset);
307 
308  retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
309  write_algorithm->address, 0, 100000, &armv7m_info);
310  if (retval != ERROR_OK) {
311  LOG_ERROR("Error executing flash erase programming algorithm");
312  return ERROR_FLASH_OPERATION_FAILED;
313  }
314 
315  retval = fm3_busy_wait(target, offset, 500);
316  if (retval != ERROR_OK)
317  return retval;
318  }
319  }
320 
321  target_free_working_area(target, write_algorithm);
322  destroy_reg_param(&reg_params[0]);
323  destroy_reg_param(&reg_params[1]);
324  destroy_reg_param(&reg_params[2]);
325 
326  /* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash access) */
327  retval = target_write_u32(target, 0x40000000, 0x0002);
328  if (retval != ERROR_OK)
329  return retval;
330 
331  // dummy read of FASZR
332  return target_read_u32(target, 0x40000000, &u32_dummy_read);
333 }
334 
335 static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer,
336  uint32_t offset, uint32_t count)
337 {
338  struct fm3_flash_bank *fm3_info = bank->driver_priv;
339  struct target *target = bank->target;
340  uint32_t buffer_size = 2048; /* Default minimum value */
341  struct working_area *write_algorithm;
342  struct working_area *source;
343  uint32_t address = bank->base + offset;
344  struct reg_param reg_params[6];
345  struct armv7m_algorithm armv7m_info;
346  int retval = ERROR_OK;
347  uint32_t u32_flash_type;
348  uint32_t u32_flash_seq_address1;
349  uint32_t u32_flash_seq_address2;
350 
351  /* Increase buffer_size if needed */
352  if (buffer_size < (target->working_area_size / 2))
353  buffer_size = (target->working_area_size / 2);
354 
355  u32_flash_type = (uint32_t) fm3_info->flashtype;
356 
357  if (u32_flash_type == FM3_FLASH_TYPE1) {
358  u32_flash_seq_address1 = 0x00001550;
359  u32_flash_seq_address2 = 0x00000AA8;
360  } else if (u32_flash_type == FM3_FLASH_TYPE2) {
361  u32_flash_seq_address1 = 0x00000AA8;
362  u32_flash_seq_address2 = 0x00000554;
363  } else {
364  LOG_ERROR("Flash/Device type unknown!");
365  return ERROR_FLASH_OPERATION_FAILED;
366  }
367 
368  /* RAMCODE used for fm3 Flash programming: */
369  /* R0 keeps source start address (u32Source) */
370  /* R1 keeps target start address (u32Target) */
371  /* R2 keeps number of halfwords to write (u32Count) */
372  /* R3 keeps Flash Sequence address 1 (u32FlashSeq1) */
373  /* R4 keeps Flash Sequence address 2 (u32FlashSeq2) */
374  /* R5 returns result value (u32FlashResult) */
375 
376  static const uint8_t fm3_flash_write_code[] = {
377  /* fm3_FLASH_IF->FASZ &= 0xFFFD; */
378  0x5F, 0xF0, 0x80, 0x45, /* MOVS.W R5, #(fm3_FLASH_IF->FASZ) */
379  0x2D, 0x68, /* LDR R5, [R5] */
380  0x4F, 0xF6, 0xFD, 0x76, /* MOVW R6, #0xFFFD */
381  0x35, 0x40, /* ANDS R5, R5, R6 */
382  0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
383  0x35, 0x60, /* STR R5, [R6] */
384  /* fm3_FLASH_IF->FASZ |= 1; */
385  0x5F, 0xF0, 0x80, 0x45, /* MOVS.W R5, #(fm3_FLASH_IF->FASZ) */
386  0x2D, 0x68, /* LDR R5, [R3] */
387  0x55, 0xF0, 0x01, 0x05, /* ORRS.W R5, R5, #1 */
388  0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
389  0x35, 0x60, /* STR R5, [R6] */
390  /* u32_dummy_read = fm3_FLASH_IF->FASZ; */
391  0x28, 0x4D, /* LDR.N R5, ??u32_dummy_read */
392  0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
393  0x36, 0x68, /* LDR R6, [R6] */
394  0x2E, 0x60, /* STR R6, [R5] */
395  /* u32FlashResult = FLASH_WRITE_NO_RESULT */
396  0x26, 0x4D, /* LDR.N R5, ??u32FlashResult */
397  0x00, 0x26, /* MOVS R6, #0 */
398  0x2E, 0x60, /* STR R6, [R5] */
399  /* while ((u32Count > 0 ) */
400  /* && (u32FlashResult */
401  /* == FLASH_WRITE_NO_RESULT)) */
402  0x01, 0x2A, /* L0: CMP R2, #1 */
403  0x2C, 0xDB, /* BLT.N L1 */
404  0x24, 0x4D, /* LDR.N R5, ??u32FlashResult */
405  0x2D, 0x68, /* LDR R5, [R5] */
406  0x00, 0x2D, /* CMP R5, #0 */
407  0x28, 0xD1, /* BNE.N L1 */
408  /* *u32FlashSeq1 = FLASH_WRITE_1; */
409  0xAA, 0x25, /* MOVS R5, #0xAA */
410  0x1D, 0x60, /* STR R5, [R3] */
411  /* *u32FlashSeq2 = FLASH_WRITE_2; */
412  0x55, 0x25, /* MOVS R5, #0x55 */
413  0x25, 0x60, /* STR R5, [R4] */
414  /* *u32FlashSeq1 = FLASH_WRITE_3; */
415  0xA0, 0x25, /* MOVS R5, #0xA0 */
416  0x1D, 0x60, /* STRH R5, [R3] */
417  /* *(volatile uint16_t*)u32Target */
418  /* = *(volatile uint16_t*)u32Source; */
419  0x05, 0x88, /* LDRH R5, [R0] */
420  0x0D, 0x80, /* STRH R5, [R1] */
421  /* while (u32FlashResult */
422  /* == FLASH_WRITE_NO_RESTULT) */
423  0x1E, 0x4D, /* L2: LDR.N R5, ??u32FlashResult */
424  0x2D, 0x68, /* LDR R5, [R5] */
425  0x00, 0x2D, /* CMP R5, #0 */
426  0x11, 0xD1, /* BNE.N L3 */
427  /* if ((*(volatile uint16_t*)u32Target */
428  /* & FLASH_DQ5) == FLASH_DQ5) */
429  0x0D, 0x88, /* LDRH R5, [R1] */
430  0xAD, 0x06, /* LSLS R5, R5, #0x1A */
431  0x02, 0xD5, /* BPL.N L4 */
432  /* u32FlashResult = FLASH_WRITE_TIMEOUT */
433  0x1A, 0x4D, /* LDR.N R5, ??u32FlashResult */
434  0x02, 0x26, /* MOVS R6, #2 */
435  0x2E, 0x60, /* STR R6, [R5] */
436  /* if ((*(volatile uint16_t *)u32Target */
437  /* & FLASH_DQ7) */
438  /* == (*(volatile uint16_t*)u32Source */
439  /* & FLASH_DQ7)) */
440  0x0D, 0x88, /* L4: LDRH R5, [R1] */
441  0x15, 0xF0, 0x80, 0x05, /* ANDS.W R5, R5, #0x80 */
442  0x06, 0x88, /* LDRH R6, [R0] */
443  0x16, 0xF0, 0x80, 0x06, /* ANDS.W R6, R6, #0x80 */
444  0xB5, 0x42, /* CMP R5, R6 */
445  0xED, 0xD1, /* BNE.N L2 */
446  /* u32FlashResult = FLASH_WRITE_OKAY */
447  0x15, 0x4D, /* LDR.N R5, ??u32FlashResult */
448  0x01, 0x26, /* MOVS R6, #1 */
449  0x2E, 0x60, /* STR R6, [R5] */
450  0xE9, 0xE7, /* B.N L2 */
451  /* if (u32FlashResult */
452  /* != FLASH_WRITE_TIMEOUT) */
453  0x13, 0x4D, /* LDR.N R5, ??u32FlashResult */
454  0x2D, 0x68, /* LDR R5, [R5] */
455  0x02, 0x2D, /* CMP R5, #2 */
456  0x02, 0xD0, /* BEQ.N L5 */
457  /* u32FlashResult = FLASH_WRITE_NO_RESULT */
458  0x11, 0x4D, /* LDR.N R5, ??u32FlashResult */
459  0x00, 0x26, /* MOVS R6, #0 */
460  0x2E, 0x60, /* STR R6, [R5] */
461  /* u32Count--; */
462  0x52, 0x1E, /* L5: SUBS R2, R2, #1 */
463  /* u32Source += 2; */
464  0x80, 0x1C, /* ADDS R0, R0, #2 */
465  /* u32Target += 2; */
466  0x89, 0x1C, /* ADDS R1, R1, #2 */
467  0xD0, 0xE7, /* B.N L0 */
468  /* fm3_FLASH_IF->FASZ &= 0xFFFE; */
469  0x5F, 0xF0, 0x80, 0x45, /* L1: MOVS.W R5, #(fm3_FLASH_IF->FASZ) */
470  0x2D, 0x68, /* LDR R5, [R5] */
471  0x4F, 0xF6, 0xFE, 0x76, /* MOVW R6, #0xFFFE */
472  0x35, 0x40, /* ANDS R5, R5, R6 */
473  0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
474  0x35, 0x60, /* STR R5, [R6] */
475  /* fm3_FLASH_IF->FASZ |= 2; */
476  0x5F, 0xF0, 0x80, 0x45, /* MOVS.W R5, #(fm3_FLASH_IF->FASZ) */
477  0x2D, 0x68, /* LDR R5, [R5] */
478  0x55, 0xF0, 0x02, 0x05, /* ORRS.W R5, R5, #2 */
479  0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
480  0x35, 0x60, /* STR R5, [R6] */
481  /* u32_dummy_read = fm3_FLASH_IF->FASZ; */
482  0x04, 0x4D, /* LDR.N R5, ??u32_dummy_read */
483  0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
484  0x36, 0x68, /* LDR R6, [R6] */
485  0x2E, 0x60, /* STR R6, [R5] */
486  /* copy u32FlashResult to R3 for return */
487  /* value */
488  0xDF, 0xF8, 0x08, 0x50, /* LDR.W R5, ??u32FlashResult */
489  0x2D, 0x68, /* LDR R5, [R5] */
490  /* Breakpoint here */
491  0x00, 0xBE, /* BKPT #0 */
492 
493  /* The following address pointers assume, that the code is running from */
494  /* SRAM basic-address + 8.These address pointers will be patched, if a */
495  /* different start address in RAM is used (e.g. for Flash type 2)! */
496  /* Default SRAM basic-address is 0x20000000. */
497  0x00, 0x00, 0x00, 0x20, /* u32_dummy_read address in RAM (0x20000000) */
498  0x04, 0x00, 0x00, 0x20 /* u32FlashResult address in RAM (0x20000004) */
499  };
500 
501  LOG_INFO("Fujitsu MB9[A/B]FXXX: FLASH Write ...");
502 
503  /* disable HW watchdog */
504  retval = target_write_u32(target, 0x40011C00, 0x1ACCE551);
505  if (retval != ERROR_OK)
506  return retval;
507 
508  retval = target_write_u32(target, 0x40011C00, 0xE5331AAE);
509  if (retval != ERROR_OK)
510  return retval;
511 
512  retval = target_write_u32(target, 0x40011008, 0x00000000);
513  if (retval != ERROR_OK)
514  return retval;
515 
516  count = count / 2; /* number bytes -> number halfwords */
517 
518  /* check code alignment */
519  if (offset & 0x1) {
520  LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
521  return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
522  }
523 
524  /* allocate working area and variables with flash programming code */
525  if (target_alloc_working_area(target, sizeof(fm3_flash_write_code) + 8,
526  &write_algorithm) != ERROR_OK) {
527  LOG_WARNING("no working area available, can't do block memory writes");
528  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
529  }
530 
531  retval = target_write_buffer(target, write_algorithm->address + 8,
532  sizeof(fm3_flash_write_code), fm3_flash_write_code);
533  if (retval != ERROR_OK)
534  return retval;
535 
536  /* Patching 'local variable address' */
537  /* Algorithm: u32_dummy_read: */
538  retval = target_write_u32(target, (write_algorithm->address + 8)
539  + sizeof(fm3_flash_write_code) - 8, (write_algorithm->address));
540  if (retval != ERROR_OK)
541  return retval;
542  /* Algorithm: u32FlashResult: */
543  retval = target_write_u32(target, (write_algorithm->address + 8)
544  + sizeof(fm3_flash_write_code) - 4, (write_algorithm->address) + 4);
545  if (retval != ERROR_OK)
546  return retval;
547 
548 
549 
550  /* memory buffer */
551  while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
552  buffer_size /= 2;
553  if (buffer_size <= 256) {
554  /* free working area, write algorithm already allocated */
555  target_free_working_area(target, write_algorithm);
556 
557  LOG_WARNING("No large enough working area available, can't do block memory writes");
558  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
559  }
560  }
561 
562  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
563  armv7m_info.core_mode = ARM_MODE_THREAD;
564 
565  init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* source start address */
566  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* target start address */
567  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* number of halfwords to program */
568  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* Flash Sequence address 1 */
569  init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* Flash Sequence address 1 */
570  init_reg_param(&reg_params[5], "r5", 32, PARAM_IN); /* result */
571 
572  /* write code buffer and use Flash programming code within fm3 */
573  /* Set breakpoint to 0 with time-out of 1000 ms */
574  while (count > 0) {
575  uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
576 
577  retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer);
578  if (retval != ERROR_OK)
579  break;
580 
581  buf_set_u32(reg_params[0].value, 0, 32, source->address);
582  buf_set_u32(reg_params[1].value, 0, 32, address);
583  buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
584  buf_set_u32(reg_params[3].value, 0, 32, u32_flash_seq_address1);
585  buf_set_u32(reg_params[4].value, 0, 32, u32_flash_seq_address2);
586 
587  retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
588  (write_algorithm->address + 8), 0, 1000, &armv7m_info);
589  if (retval != ERROR_OK) {
590  LOG_ERROR("Error executing fm3 Flash programming algorithm");
591  retval = ERROR_FLASH_OPERATION_FAILED;
592  break;
593  }
594 
595  if (buf_get_u32(reg_params[5].value, 0, 32) != ERROR_OK) {
596  LOG_ERROR("Fujitsu MB9[A/B]FXXX: Flash programming ERROR (Timeout) -> Reg R3: %" PRIx32,
597  buf_get_u32(reg_params[5].value, 0, 32));
598  retval = ERROR_FLASH_OPERATION_FAILED;
599  break;
600  }
601 
602  buffer += thisrun_count * 2;
603  address += thisrun_count * 2;
604  count -= thisrun_count;
605  }
606 
607  target_free_working_area(target, source);
608  target_free_working_area(target, write_algorithm);
609 
610  destroy_reg_param(&reg_params[0]);
611  destroy_reg_param(&reg_params[1]);
612  destroy_reg_param(&reg_params[2]);
613  destroy_reg_param(&reg_params[3]);
614  destroy_reg_param(&reg_params[4]);
615  destroy_reg_param(&reg_params[5]);
616 
617  return retval;
618 }
619 
620 static int fm3_probe(struct flash_bank *bank)
621 {
622  struct fm3_flash_bank *fm3_info = bank->driver_priv;
623  uint16_t num_pages;
624 
625  if (bank->target->state != TARGET_HALTED) {
626  LOG_ERROR("Target not halted");
627  return ERROR_TARGET_NOT_HALTED;
628  }
629 
630 /*
631  -- page-- start -- blocksize - mpu - totalFlash --
632  page0 0x00000 16k
633  page1 0x04000 16k
634  page2 0x08000 96k ___ fxx3 128k Flash
635  page3 0x20000 128k ___ fxx4 256k Flash
636  page4 0x40000 128k ___ fxx5 384k Flash
637  page5 0x60000 128k ___ fxx6 512k Flash
638 -----------------------
639  page6 0x80000 128k
640  page7 0xa0000 128k ___ fxx7 256k Flash
641  page8 0xc0000 128k
642  page9 0xe0000 128k ___ fxx8 256k Flash
643  */
644 
645  num_pages = 10; /* max number of Flash pages for malloc */
646  fm3_info->probed = false;
647 
648  bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
649  bank->base = 0x00000000;
650  bank->size = 32 * 1024; /* bytes */
651 
652  bank->sectors[0].offset = 0;
653  bank->sectors[0].size = 16 * 1024;
654  bank->sectors[0].is_erased = -1;
655  bank->sectors[0].is_protected = -1;
656 
657  bank->sectors[1].offset = 0x4000;
658  bank->sectors[1].size = 16 * 1024;
659  bank->sectors[1].is_erased = -1;
660  bank->sectors[1].is_protected = -1;
661 
662  if ((fm3_info->variant == MB9BFXX1)
663  || (fm3_info->variant == MB9AFXX1)) {
664  num_pages = 3;
665  bank->size = 64 * 1024; /* bytes */
666  bank->num_sectors = num_pages;
667 
668  bank->sectors[2].offset = 0x8000;
669  bank->sectors[2].size = 32 * 1024;
670  bank->sectors[2].is_erased = -1;
671  bank->sectors[2].is_protected = -1;
672  }
673 
674  if ((fm3_info->variant == MB9BFXX2)
675  || (fm3_info->variant == MB9BFXX4)
676  || (fm3_info->variant == MB9BFXX5)
677  || (fm3_info->variant == MB9BFXX6)
678  || (fm3_info->variant == MB9BFXX7)
679  || (fm3_info->variant == MB9BFXX8)
680  || (fm3_info->variant == MB9AFXX2)
681  || (fm3_info->variant == MB9AFXX4)
682  || (fm3_info->variant == MB9AFXX5)
683  || (fm3_info->variant == MB9AFXX6)
684  || (fm3_info->variant == MB9AFXX7)
685  || (fm3_info->variant == MB9AFXX8)) {
686  num_pages = 3;
687  bank->size = 128 * 1024; /* bytes */
688  bank->num_sectors = num_pages;
689 
690  bank->sectors[2].offset = 0x8000;
691  bank->sectors[2].size = 96 * 1024;
692  bank->sectors[2].is_erased = -1;
693  bank->sectors[2].is_protected = -1;
694  }
695 
696  if ((fm3_info->variant == MB9BFXX4)
697  || (fm3_info->variant == MB9BFXX5)
698  || (fm3_info->variant == MB9BFXX6)
699  || (fm3_info->variant == MB9BFXX7)
700  || (fm3_info->variant == MB9BFXX8)
701  || (fm3_info->variant == MB9AFXX4)
702  || (fm3_info->variant == MB9AFXX5)
703  || (fm3_info->variant == MB9AFXX6)
704  || (fm3_info->variant == MB9AFXX7)
705  || (fm3_info->variant == MB9AFXX8)) {
706  num_pages = 4;
707  bank->size = 256 * 1024; /* bytes */
708  bank->num_sectors = num_pages;
709 
710  bank->sectors[3].offset = 0x20000;
711  bank->sectors[3].size = 128 * 1024;
712  bank->sectors[3].is_erased = -1;
713  bank->sectors[3].is_protected = -1;
714  }
715 
716  if ((fm3_info->variant == MB9BFXX5)
717  || (fm3_info->variant == MB9BFXX6)
718  || (fm3_info->variant == MB9BFXX7)
719  || (fm3_info->variant == MB9BFXX8)
720  || (fm3_info->variant == MB9AFXX5)
721  || (fm3_info->variant == MB9AFXX6)
722  || (fm3_info->variant == MB9AFXX7)
723  || (fm3_info->variant == MB9AFXX8)) {
724  num_pages = 5;
725  bank->size = 384 * 1024; /* bytes */
726  bank->num_sectors = num_pages;
727 
728  bank->sectors[4].offset = 0x40000;
729  bank->sectors[4].size = 128 * 1024;
730  bank->sectors[4].is_erased = -1;
731  bank->sectors[4].is_protected = -1;
732  }
733 
734  if ((fm3_info->variant == MB9BFXX6)
735  || (fm3_info->variant == MB9BFXX7)
736  || (fm3_info->variant == MB9BFXX8)
737  || (fm3_info->variant == MB9AFXX6)
738  || (fm3_info->variant == MB9AFXX7)
739  || (fm3_info->variant == MB9AFXX8)) {
740  num_pages = 6;
741  bank->size = 512 * 1024; /* bytes */
742  bank->num_sectors = num_pages;
743 
744  bank->sectors[5].offset = 0x60000;
745  bank->sectors[5].size = 128 * 1024;
746  bank->sectors[5].is_erased = -1;
747  bank->sectors[5].is_protected = -1;
748  }
749 
750  if ((fm3_info->variant == MB9BFXX7)
751  || (fm3_info->variant == MB9BFXX8)
752  || (fm3_info->variant == MB9AFXX7)
753  || (fm3_info->variant == MB9AFXX8)) {
754  num_pages = 8;
755  bank->size = 768 * 1024; /* bytes */
756  bank->num_sectors = num_pages;
757 
758  bank->sectors[6].offset = 0x80000;
759  bank->sectors[6].size = 128 * 1024;
760  bank->sectors[6].is_erased = -1;
761  bank->sectors[6].is_protected = -1;
762 
763  bank->sectors[7].offset = 0xa0000;
764  bank->sectors[7].size = 128 * 1024;
765  bank->sectors[7].is_erased = -1;
766  bank->sectors[7].is_protected = -1;
767  }
768 
769  if ((fm3_info->variant == MB9BFXX8)
770  || (fm3_info->variant == MB9AFXX8)) {
771  num_pages = 10;
772  bank->size = 1024 * 1024; /* bytes */
773  bank->num_sectors = num_pages;
774 
775  bank->sectors[8].offset = 0xc0000;
776  bank->sectors[8].size = 128 * 1024;
777  bank->sectors[8].is_erased = -1;
778  bank->sectors[8].is_protected = -1;
779 
780  bank->sectors[9].offset = 0xe0000;
781  bank->sectors[9].size = 128 * 1024;
782  bank->sectors[9].is_erased = -1;
783  bank->sectors[9].is_protected = -1;
784  }
785 
786  fm3_info->probed = true;
787 
788  return ERROR_OK;
789 }
790 
791 static int fm3_auto_probe(struct flash_bank *bank)
792 {
793  struct fm3_flash_bank *fm3_info = bank->driver_priv;
794  if (fm3_info->probed)
795  return ERROR_OK;
796  return fm3_probe(bank);
797 }
798 
799 /* Chip erase */
800 static int fm3_chip_erase(struct flash_bank *bank)
801 {
802  struct target *target = bank->target;
803  struct fm3_flash_bank *fm3_info2 = bank->driver_priv;
804  int retval = ERROR_OK;
805  uint32_t u32_dummy_read;
806  uint32_t u32_flash_type;
807  uint32_t u32_flash_seq_address1;
808  uint32_t u32_flash_seq_address2;
809 
810  struct working_area *write_algorithm;
811  struct reg_param reg_params[3];
812  struct armv7m_algorithm armv7m_info;
813 
814  u32_flash_type = (uint32_t) fm3_info2->flashtype;
815 
816  if (u32_flash_type == FM3_FLASH_TYPE1) {
817  LOG_INFO("*** Erasing mb9bfxxx type");
818  u32_flash_seq_address1 = 0x00001550;
819  u32_flash_seq_address2 = 0x00000AA8;
820  } else if (u32_flash_type == FM3_FLASH_TYPE2) {
821  LOG_INFO("*** Erasing mb9afxxx type");
822  u32_flash_seq_address1 = 0x00000AA8;
823  u32_flash_seq_address2 = 0x00000554;
824  } else {
825  LOG_ERROR("Flash/Device type unknown!");
826  return ERROR_FLASH_OPERATION_FAILED;
827  }
828 
829  if (target->state != TARGET_HALTED) {
830  LOG_ERROR("Target not halted");
831  return ERROR_TARGET_NOT_HALTED;
832  }
833 
834  /* RAMCODE used for fm3 Flash chip erase: */
835  /* R0 keeps Flash Sequence address 1 (u32FlashSeq1) */
836  /* R1 keeps Flash Sequence address 2 (u32FlashSeq2) */
837  static const uint8_t fm3_flash_erase_chip_code[] = {
838  /* *(uint16_t*)u32FlashSeq1 = 0xAA; */
839  0xAA, 0x22, /* MOVS R2, #0xAA */
840  0x02, 0x80, /* STRH R2, [R0, #0] */
841  /* *(uint16_t*)u32FlashSeq2 = 0x55; */
842  0x55, 0x23, /* MOVS R3, #0x55 */
843  0x0B, 0x80, /* STRH R3, [R1, #0] */
844  /* *(uint16_t*)u32FlashSeq1 = 0x80; */
845  0x80, 0x24, /* MOVS R4, #0x80 */
846  0x04, 0x80, /* STRH R4, [R0, #0] */
847  /* *(uint16_t*)u32FlashSeq1 = 0xAA; */
848  0x02, 0x80, /* STRH R2, [R0, #0] */
849  /* *(uint16_t*)u32FlashSeq2 = 0x55; */
850  0x0B, 0x80, /* STRH R3, [R1, #0] */
851  /* Chip_Erase Command 0x10 */
852  /* *(uint16_t*)u32FlashSeq1 = 0x10; */
853  0x10, 0x21, /* MOVS R1, #0x10 */
854  0x01, 0x80, /* STRH R1, [R0, #0] */
855  /* End Code */
856  0x00, 0xBE, /* BKPT #0 */
857  };
858 
859  LOG_INFO("Fujitsu MB9[A/B]xxx: Chip Erase ... (may take several seconds)");
860 
861  /* disable HW watchdog */
862  retval = target_write_u32(target, 0x40011C00, 0x1ACCE551);
863  if (retval != ERROR_OK)
864  return retval;
865 
866  retval = target_write_u32(target, 0x40011C00, 0xE5331AAE);
867  if (retval != ERROR_OK)
868  return retval;
869 
870  retval = target_write_u32(target, 0x40011008, 0x00000000);
871  if (retval != ERROR_OK)
872  return retval;
873 
874  /* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash access) */
875  retval = target_write_u32(target, 0x40000000, 0x0001);
876  if (retval != ERROR_OK)
877  return retval;
878 
879  /* dummy read of FASZR */
880  retval = target_read_u32(target, 0x40000000, &u32_dummy_read);
881  if (retval != ERROR_OK)
882  return retval;
883 
884  /* allocate working area with flash chip erase code */
885  if (target_alloc_working_area(target, sizeof(fm3_flash_erase_chip_code),
886  &write_algorithm) != ERROR_OK) {
887  LOG_WARNING("no working area available, can't do block memory writes");
888  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
889  }
890  retval = target_write_buffer(target, write_algorithm->address,
891  sizeof(fm3_flash_erase_chip_code), fm3_flash_erase_chip_code);
892  if (retval != ERROR_OK)
893  return retval;
894 
895  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
896  armv7m_info.core_mode = ARM_MODE_THREAD;
897 
898  init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* u32_flash_seq_address1 */
899  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* u32_flash_seq_address2 */
900 
901  buf_set_u32(reg_params[0].value, 0, 32, u32_flash_seq_address1);
902  buf_set_u32(reg_params[1].value, 0, 32, u32_flash_seq_address2);
903 
904  retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
905  write_algorithm->address, 0, 100000, &armv7m_info);
906  if (retval != ERROR_OK) {
907  LOG_ERROR("Error executing flash erase programming algorithm");
908  return ERROR_FLASH_OPERATION_FAILED;
909  }
910 
911  target_free_working_area(target, write_algorithm);
912 
913  destroy_reg_param(&reg_params[0]);
914  destroy_reg_param(&reg_params[1]);
915 
916  retval = fm3_busy_wait(target, u32_flash_seq_address2, 20000); /* 20s timeout */
917  if (retval != ERROR_OK)
918  return retval;
919 
920  /* FASZR = 0x02, Re-enables CPU Run Mode (32-bit Flash access) */
921  retval = target_write_u32(target, 0x40000000, 0x0002);
922  if (retval != ERROR_OK)
923  return retval;
924 
925  // dummy read of FASZR
926  return target_read_u32(target, 0x40000000, &u32_dummy_read);
927 }
928 
929 COMMAND_HANDLER(fm3_handle_chip_erase_command)
930 {
931  if (CMD_ARGC < 1)
932  return ERROR_COMMAND_SYNTAX_ERROR;
933 
934  struct flash_bank *bank;
935  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
936  if (retval != ERROR_OK)
937  return retval;
938 
939  if (fm3_chip_erase(bank) == ERROR_OK) {
940  command_print(CMD, "fm3 chip erase complete");
941  } else {
942  command_print(CMD, "fm3 chip erase failed");
943  }
944 
945  return ERROR_OK;
946 }
947 
948 static const struct command_registration fm3_exec_command_handlers[] = {
949  {
950  .name = "chip_erase",
951  .usage = "<bank>",
952  .handler = fm3_handle_chip_erase_command,
953  .mode = COMMAND_EXEC,
954  .help = "Erase entire Flash device.",
955  },
956  COMMAND_REGISTRATION_DONE
957 };
958 
959 static const struct command_registration fm3_command_handlers[] = {
960  {
961  .name = "fm3",
962  .mode = COMMAND_ANY,
963  .help = "fm3 Flash command group",
964  .usage = "",
965  .chain = fm3_exec_command_handlers,
966  },
967  COMMAND_REGISTRATION_DONE
968 };
969 
970 const struct flash_driver fm3_flash = {
971  .name = "fm3",
972  .commands = fm3_command_handlers,
973  .flash_bank_command = fm3_flash_bank_command,
974  .erase = fm3_erase,
975  .write = fm3_write_block,
976  .probe = fm3_probe,
977  .auto_probe = fm3_auto_probe,
978  .erase_check = default_flash_blank_check,
979  .free_driver_priv = default_flash_free_driver_priv,
980 };
init_reg_param
void init_reg_param(struct reg_param *param, const char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
destroy_reg_param
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:38
PARAM_OUT
@ PARAM_OUT
Definition: algorithm.h:16
PARAM_IN
@ PARAM_IN
Definition: algorithm.h:15
ARM_MODE_THREAD
@ ARM_MODE_THREAD
Definition: arm.h:94
ARMV7M_COMMON_MAGIC
#define ARMV7M_COMMON_MAGIC
Definition: armv7m.h:229
binarybuffer.h
Support functions to access arbitrary bits in a byte array.
buf_get_u32
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:104
buf_set_u32
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:389
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:146
CALL_COMMAND_HANDLER
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:123
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:161
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:405
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:156
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:256
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
buffer
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
buffer_size
uint32_t buffer_size
Size of dw_spi_program::buffer.
Definition: dw-spi-helper.h:5
address
uint32_t address
Starting address. Sector aligned.
Definition: dw-spi-helper.h:0
bank
uint8_t bank
Definition: esirisc.c:135
ERROR_FLASH_BANK_INVALID
#define ERROR_FLASH_BANK_INVALID
Definition: flash/common.h:28
ERROR_FLASH_OPERATION_FAILED
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
ERROR_FLASH_DST_BREAKS_ALIGNMENT
#define ERROR_FLASH_DST_BREAKS_ALIGNMENT
Definition: flash/common.h:32
default_flash_blank_check
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
Definition: flash/nor/core.c:377
default_flash_free_driver_priv
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
Definition: flash/nor/core.c:210
fm3_exec_command_handlers
static const struct command_registration fm3_exec_command_handlers[]
Definition: fm3.c:948
fm3_probe
static int fm3_probe(struct flash_bank *bank)
Definition: fm3.c:620
FLASH_BANK_COMMAND_HANDLER
FLASH_BANK_COMMAND_HANDLER(fm3_flash_bank_command)
Definition: fm3.c:56
fm3_busy_wait
static int fm3_busy_wait(struct target *target, uint32_t offset, int timeout_ms)
Definition: fm3.c:130
fm3_erase
static int fm3_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: fm3.c:193
fm3_variant
fm3_variant
Definition: fm3.c:24
MB9BFXX2
@ MB9BFXX2
Definition: fm3.c:26
MB9AFXX4
@ MB9AFXX4
Definition: fm3.c:37
MB9AFXX8
@ MB9AFXX8
Definition: fm3.c:41
MB9AFXX1
@ MB9AFXX1
Definition: fm3.c:34
MB9BFXX4
@ MB9BFXX4
Definition: fm3.c:28
MB9BFXX1
@ MB9BFXX1
Definition: fm3.c:25
MB9BFXX5
@ MB9BFXX5
Definition: fm3.c:29
MB9BFXX6
@ MB9BFXX6
Definition: fm3.c:30
MB9AFXX5
@ MB9AFXX5
Definition: fm3.c:38
MB9AFXX2
@ MB9AFXX2
Definition: fm3.c:35
MB9BFXX8
@ MB9BFXX8
Definition: fm3.c:32
MB9AFXX7
@ MB9AFXX7
Definition: fm3.c:40
MB9AFXX6
@ MB9AFXX6
Definition: fm3.c:39
MB9AFXX3
@ MB9AFXX3
Definition: fm3.c:36
MB9BFXX7
@ MB9BFXX7
Definition: fm3.c:31
MB9BFXX3
@ MB9BFXX3
Definition: fm3.c:27
FLASH_DQ6
#define FLASH_DQ6
Definition: fm3.c:21
fm3_flash
const struct flash_driver fm3_flash
Definition: fm3.c:970
fm3_flash_type
fm3_flash_type
Definition: fm3.c:44
FM3_NO_FLASH_TYPE
@ FM3_NO_FLASH_TYPE
Definition: fm3.c:45
FM3_FLASH_TYPE2
@ FM3_FLASH_TYPE2
Definition: fm3.c:47
FM3_FLASH_TYPE1
@ FM3_FLASH_TYPE1
Definition: fm3.c:46
FLASH_DQ5
#define FLASH_DQ5
Definition: fm3.c:22
fm3_chip_erase
static int fm3_chip_erase(struct flash_bank *bank)
Definition: fm3.c:800
fm3_command_handlers
static const struct command_registration fm3_command_handlers[]
Definition: fm3.c:959
fm3_auto_probe
static int fm3_auto_probe(struct flash_bank *bank)
Definition: fm3.c:791
COMMAND_HANDLER
COMMAND_HANDLER(fm3_handle_chip_erase_command)
Definition: fm3.c:929
fm3_write_block
static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: fm3.c:335
LOG_WARNING
#define LOG_WARNING(expr ...)
Definition: log.h:144
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:147
LOG_INFO
#define LOG_INFO(expr ...)
Definition: log.h:141
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:124
ERROR_OK
#define ERROR_OK
Definition: log.h:182
source
struct rtt_source source
Definition: rtt/rtt.c:23
armv7m_algorithm
Definition: armv7m.h:305
armv7m_algorithm::common_magic
unsigned int common_magic
Definition: armv7m.h:306
armv7m_algorithm::core_mode
enum arm_mode core_mode
Definition: armv7m.h:308
command_registration
Definition: command.h:238
command_registration::name
const char * name
Definition: command.h:239
flash_bank
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
flash_driver
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
flash_driver::name
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
flash_sector
Describes the geometry and status of a single flash sector within a flash bank.
Definition: nor/core.h:28
fm3_flash_bank
Definition: fm3.c:50
fm3_flash_bank::probed
bool probed
Definition: fm3.c:53
fm3_flash_bank::flashtype
enum fm3_flash_type flashtype
Definition: fm3.c:52
fm3_flash_bank::variant
enum fm3_variant variant
Definition: fm3.c:51
reg_param
Definition: algorithm.h:27
target
Definition: target.h:119
target::working_area_size
uint32_t working_area_size
Definition: target.h:161
target::state
enum target_state state
Definition: target.h:167
working_area
Definition: target.h:88
working_area::address
target_addr_t address
Definition: target.h:89
target_write_buffer
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2369
target_read_u8
int target_read_u8(struct target *target, target_addr_t address, uint8_t *value)
Definition: target.c:2601
target_run_algorithm
int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Downloads a target-specific native code algorithm to the target, and executes it.
Definition: target.c:786
target_alloc_working_area
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2090
target_write_u32
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2635
target_free_working_area
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2148
target_read_u32
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2561
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:817
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:58
ERROR_TARGET_RESOURCE_NOT_AVAILABLE
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:821
NULL
#define NULL
Definition: usb.h:16
offset
uint8_t offset[4]
Definition: vdebug.c:9
count
uint8_t count[4]
Definition: vdebug.c:22