OpenOCD
at91sam3.c
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1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code)
2 
3 /*
4  * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com>
5  *
6  * at91sam3s* support
7  * Copyright (C) 2010 by Olaf Lüke <olaf@uni-paderborn.de>
8  * Copyright (C) 2011 by Olivier Schonken and Jim Norris
9  *
10  * Some of the lower level code was based on code supplied by
11  * ATMEL under BSD-Source-Code License and this copyright.
12  * ATMEL Microcontroller Software Support
13  * Copyright (c) 2009, Atmel Corporation. All rights reserved.
14  */
15 
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19 
20 #include "imp.h"
21 #include <helper/time_support.h>
22 
23 #define REG_NAME_WIDTH (12)
24 
25 /* at91sam3u series (has one or two flash banks) */
26 #define FLASH_BANK0_BASE_U 0x00080000
27 #define FLASH_BANK1_BASE_U 0x00100000
28 
29 /* at91sam3s series (has always one flash bank) */
30 #define FLASH_BANK_BASE_S 0x00400000
31 
32 /* at91sam3sd series (has always two flash banks) */
33 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
34 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
35 
36 
37 /* at91sam3n series (has always one flash bank) */
38 #define FLASH_BANK_BASE_N 0x00400000
39 
40 /* at91sam3a/x series has two flash banks*/
41 #define FLASH_BANK0_BASE_AX 0x00080000
42 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
43 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
44 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
45 
46 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
47 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
48 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
49 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
50 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
51 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
52 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
53 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
54 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
55 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
56 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
57 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
58 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
59 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
60 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
61 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
62 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
63 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
64 
65 #define OFFSET_EFC_FMR 0
66 #define OFFSET_EFC_FCR 4
67 #define OFFSET_EFC_FSR 8
68 #define OFFSET_EFC_FRR 12
69 
70 static float _tomhz(uint32_t freq_hz)
71 {
72  float f;
73 
74  f = ((float)(freq_hz)) / 1000000.0;
75  return f;
76 }
77 
78 /* How the chip is configured. */
79 struct sam3_cfg {
80  uint32_t unique_id[4];
81 
82  uint32_t slow_freq;
83  uint32_t rc_freq;
84  uint32_t mainosc_freq;
85  uint32_t plla_freq;
86  uint32_t mclk_freq;
87  uint32_t cpu_freq;
88  uint32_t fclk_freq;
89  uint32_t pclk0_freq;
90  uint32_t pclk1_freq;
91  uint32_t pclk2_freq;
92 
93 
94 #define SAM3_CHIPID_CIDR (0x400E0740)
95  uint32_t CHIPID_CIDR;
96 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
97  uint32_t CHIPID_CIDR2;
98 #define SAM3_CHIPID_EXID (0x400E0744)
99  uint32_t CHIPID_EXID;
100 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
101  uint32_t CHIPID_EXID2;
102 
103 
104 #define SAM3_PMC_BASE (0x400E0400)
105 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
106  uint32_t PMC_SCSR;
107 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
108  uint32_t PMC_PCSR;
109 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
110  uint32_t CKGR_UCKR;
111 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
112  uint32_t CKGR_MOR;
113 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
114  uint32_t CKGR_MCFR;
115 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
116  uint32_t CKGR_PLLAR;
117 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
118  uint32_t PMC_MCKR;
119 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
120  uint32_t PMC_PCK0;
121 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
122  uint32_t PMC_PCK1;
123 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
124  uint32_t PMC_PCK2;
125 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
126  uint32_t PMC_SR;
127 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
128  uint32_t PMC_IMR;
129 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
130  uint32_t PMC_FSMR;
131 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
132  uint32_t PMC_FSPR;
133 };
134 
135 /*
136  * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
137  * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
138  * the flash wait state (FWS) should be set to 6. It seems like that the
139  * cause of the problem is not the flash itself, but the flash write
140  * buffer. Ie the wait states have to be set before writing into the
141  * buffer.
142  * Tested and confirmed with SAM3N and SAM3U
143  */
144 
145 struct sam3_bank_private {
146  bool probed;
147  /* DANGER: THERE ARE DRAGONS HERE.. */
148  /* NOTE: If you add more 'ghost' pointers */
149  /* be aware that you must *manually* update */
150  /* these pointers in the function sam3_get_details() */
151  /* See the comment "Here there be dragons" */
152 
153  /* so we can find the chip we belong to */
154  struct sam3_chip *chip;
155  /* so we can find the original bank pointer */
156  struct flash_bank *bank;
157  unsigned int bank_number;
158  uint32_t controller_address;
159  uint32_t base_address;
160  uint32_t flash_wait_states;
161  bool present;
162  unsigned int size_bytes;
163  unsigned int nsectors;
164  unsigned int sector_size;
165  unsigned int page_size;
166 };
167 
168 struct sam3_chip_details {
169  /* THERE ARE DRAGONS HERE.. */
170  /* note: If you add pointers here */
171  /* be careful about them as they */
172  /* may need to be updated inside */
173  /* the function: "sam3_get_details() */
174  /* which copy/overwrites the */
175  /* 'runtime' copy of this structure */
176  uint32_t chipid_cidr;
177  const char *name;
178 
179  unsigned int n_gpnvms;
180 #define SAM3_N_NVM_BITS 3
181  unsigned int gpnvm[SAM3_N_NVM_BITS];
182  unsigned int total_flash_size;
183  unsigned int total_sram_size;
184  unsigned int n_banks;
185 #define SAM3_MAX_FLASH_BANKS 2
186  /* these are "initialized" from the global const data */
187  struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
188 };
189 
190 struct sam3_chip {
191  struct sam3_chip *next;
192  bool probed;
193 
194  /* this is "initialized" from the global const structure */
195  struct sam3_chip_details details;
196  struct target *target;
197  struct sam3_cfg cfg;
198 };
199 
200 
201 struct sam3_reg_list {
202  uint32_t address; size_t struct_offset; const char *name;
203  void (*explain_func)(struct sam3_chip *chip);
204 };
205 
206 static struct sam3_chip *all_sam3_chips;
207 
208 static struct sam3_chip *get_current_sam3(struct command_invocation *cmd)
209 {
210  struct target *t;
211  static struct sam3_chip *p;
212 
213  t = get_current_target(cmd->ctx);
214  if (!t) {
215  command_print_sameline(cmd, "No current target?\n");
216  return NULL;
217  }
218 
219  p = all_sam3_chips;
220  if (!p) {
221  /* this should not happen */
222  /* the command is not registered until the chip is created? */
223  command_print_sameline(cmd, "No SAM3 chips exist?\n");
224  return NULL;
225  }
226 
227  while (p) {
228  if (p->target == t)
229  return p;
230  p = p->next;
231  }
232  command_print_sameline(cmd, "Cannot find SAM3 chip?\n");
233  return NULL;
234 }
235 
236 /* these are used to *initialize* the "chip->details" structure. */
237 static const struct sam3_chip_details all_sam3_details[] = {
238  /* Start at91sam3u* series */
239  {
240  .chipid_cidr = 0x28100960,
241  .name = "at91sam3u4e",
242  .total_flash_size = 256 * 1024,
243  .total_sram_size = 52 * 1024,
244  .n_gpnvms = 3,
245  .n_banks = 2,
246 
247  /* System boots at address 0x0 */
248  /* gpnvm[1] = selects boot code */
249  /* if gpnvm[1] == 0 */
250  /* boot is via "SAMBA" (rom) */
251  /* else */
252  /* boot is via FLASH */
253  /* Selection is via gpnvm[2] */
254  /* endif */
255  /* */
256  /* NOTE: banks 0 & 1 switch places */
257  /* if gpnvm[2] == 0 */
258  /* Bank0 is the boot rom */
259  /* else */
260  /* Bank1 is the boot rom */
261  /* endif */
262 /* .bank[0] = { */
263  {
264  {
265  .probed = false,
266  .chip = NULL,
267  .bank = NULL,
268  .bank_number = 0,
269  .base_address = FLASH_BANK0_BASE_U,
270  .controller_address = 0x400e0800,
271  .flash_wait_states = 6, /* workaround silicon bug */
272  .present = 1,
273  .size_bytes = 128 * 1024,
274  .nsectors = 16,
275  .sector_size = 8192,
276  .page_size = 256,
277  },
278 
279 /* .bank[1] = { */
280  {
281  .probed = false,
282  .chip = NULL,
283  .bank = NULL,
284  .bank_number = 1,
285  .base_address = FLASH_BANK1_BASE_U,
286  .controller_address = 0x400e0a00,
287  .flash_wait_states = 6, /* workaround silicon bug */
288  .present = 1,
289  .size_bytes = 128 * 1024,
290  .nsectors = 16,
291  .sector_size = 8192,
292  .page_size = 256,
293  },
294  },
295  },
296 
297  {
298  .chipid_cidr = 0x281a0760,
299  .name = "at91sam3u2e",
300  .total_flash_size = 128 * 1024,
301  .total_sram_size = 36 * 1024,
302  .n_gpnvms = 2,
303  .n_banks = 1,
304 
305  /* System boots at address 0x0 */
306  /* gpnvm[1] = selects boot code */
307  /* if gpnvm[1] == 0 */
308  /* boot is via "SAMBA" (rom) */
309  /* else */
310  /* boot is via FLASH */
311  /* Selection is via gpnvm[2] */
312  /* endif */
313 /* .bank[0] = { */
314  {
315  {
316  .probed = false,
317  .chip = NULL,
318  .bank = NULL,
319  .bank_number = 0,
320  .base_address = FLASH_BANK0_BASE_U,
321  .controller_address = 0x400e0800,
322  .flash_wait_states = 6, /* workaround silicon bug */
323  .present = 1,
324  .size_bytes = 128 * 1024,
325  .nsectors = 16,
326  .sector_size = 8192,
327  .page_size = 256,
328  },
329 /* .bank[1] = { */
330  {
331  .present = 0,
332  .probed = false,
333  .bank_number = 1,
334  },
335  },
336  },
337  {
338  .chipid_cidr = 0x28190560,
339  .name = "at91sam3u1e",
340  .total_flash_size = 64 * 1024,
341  .total_sram_size = 20 * 1024,
342  .n_gpnvms = 2,
343  .n_banks = 1,
344 
345  /* System boots at address 0x0 */
346  /* gpnvm[1] = selects boot code */
347  /* if gpnvm[1] == 0 */
348  /* boot is via "SAMBA" (rom) */
349  /* else */
350  /* boot is via FLASH */
351  /* Selection is via gpnvm[2] */
352  /* endif */
353  /* */
354 
355 /* .bank[0] = { */
356  {
357  {
358  .probed = false,
359  .chip = NULL,
360  .bank = NULL,
361  .bank_number = 0,
362  .base_address = FLASH_BANK0_BASE_U,
363  .controller_address = 0x400e0800,
364  .flash_wait_states = 6, /* workaround silicon bug */
365  .present = 1,
366  .size_bytes = 64 * 1024,
367  .nsectors = 8,
368  .sector_size = 8192,
369  .page_size = 256,
370  },
371 
372 /* .bank[1] = { */
373  {
374  .present = 0,
375  .probed = false,
376  .bank_number = 1,
377  },
378  },
379  },
380 
381  {
382  .chipid_cidr = 0x28000960,
383  .name = "at91sam3u4c",
384  .total_flash_size = 256 * 1024,
385  .total_sram_size = 52 * 1024,
386  .n_gpnvms = 3,
387  .n_banks = 2,
388 
389  /* System boots at address 0x0 */
390  /* gpnvm[1] = selects boot code */
391  /* if gpnvm[1] == 0 */
392  /* boot is via "SAMBA" (rom) */
393  /* else */
394  /* boot is via FLASH */
395  /* Selection is via gpnvm[2] */
396  /* endif */
397  /* */
398  /* NOTE: banks 0 & 1 switch places */
399  /* if gpnvm[2] == 0 */
400  /* Bank0 is the boot rom */
401  /* else */
402  /* Bank1 is the boot rom */
403  /* endif */
404  {
405  {
406 /* .bank[0] = { */
407  .probed = false,
408  .chip = NULL,
409  .bank = NULL,
410  .bank_number = 0,
411  .base_address = FLASH_BANK0_BASE_U,
412  .controller_address = 0x400e0800,
413  .flash_wait_states = 6, /* workaround silicon bug */
414  .present = 1,
415  .size_bytes = 128 * 1024,
416  .nsectors = 16,
417  .sector_size = 8192,
418  .page_size = 256,
419  },
420 /* .bank[1] = { */
421  {
422  .probed = false,
423  .chip = NULL,
424  .bank = NULL,
425  .bank_number = 1,
426  .base_address = FLASH_BANK1_BASE_U,
427  .controller_address = 0x400e0a00,
428  .flash_wait_states = 6, /* workaround silicon bug */
429  .present = 1,
430  .size_bytes = 128 * 1024,
431  .nsectors = 16,
432  .sector_size = 8192,
433  .page_size = 256,
434  },
435  },
436  },
437 
438  {
439  .chipid_cidr = 0x280a0760,
440  .name = "at91sam3u2c",
441  .total_flash_size = 128 * 1024,
442  .total_sram_size = 36 * 1024,
443  .n_gpnvms = 2,
444  .n_banks = 1,
445 
446  /* System boots at address 0x0 */
447  /* gpnvm[1] = selects boot code */
448  /* if gpnvm[1] == 0 */
449  /* boot is via "SAMBA" (rom) */
450  /* else */
451  /* boot is via FLASH */
452  /* Selection is via gpnvm[2] */
453  /* endif */
454  {
455 /* .bank[0] = { */
456  {
457  .probed = false,
458  .chip = NULL,
459  .bank = NULL,
460  .bank_number = 0,
461  .base_address = FLASH_BANK0_BASE_U,
462  .controller_address = 0x400e0800,
463  .flash_wait_states = 6, /* workaround silicon bug */
464  .present = 1,
465  .size_bytes = 128 * 1024,
466  .nsectors = 16,
467  .sector_size = 8192,
468  .page_size = 256,
469  },
470 /* .bank[1] = { */
471  {
472  .present = 0,
473  .probed = false,
474  .bank_number = 1,
475  },
476  },
477  },
478  {
479  .chipid_cidr = 0x28090560,
480  .name = "at91sam3u1c",
481  .total_flash_size = 64 * 1024,
482  .total_sram_size = 20 * 1024,
483  .n_gpnvms = 2,
484  .n_banks = 1,
485 
486  /* System boots at address 0x0 */
487  /* gpnvm[1] = selects boot code */
488  /* if gpnvm[1] == 0 */
489  /* boot is via "SAMBA" (rom) */
490  /* else */
491  /* boot is via FLASH */
492  /* Selection is via gpnvm[2] */
493  /* endif */
494  /* */
495 
496  {
497 /* .bank[0] = { */
498  {
499  .probed = false,
500  .chip = NULL,
501  .bank = NULL,
502  .bank_number = 0,
503  .base_address = FLASH_BANK0_BASE_U,
504  .controller_address = 0x400e0800,
505  .flash_wait_states = 6, /* workaround silicon bug */
506  .present = 1,
507  .size_bytes = 64 * 1024,
508  .nsectors = 8,
509  .sector_size = 8192,
510  .page_size = 256,
511  },
512 /* .bank[1] = { */
513  {
514  .present = 0,
515  .probed = false,
516  .bank_number = 1,
517 
518  },
519  },
520  },
521 
522  /* Start at91sam3s* series */
523 
524  /* Note: The preliminary at91sam3s datasheet says on page 302 */
525  /* that the flash controller is at address 0x400E0800. */
526  /* This is _not_ the case, the controller resides at address 0x400e0a00. */
527  {
528  .chipid_cidr = 0x28A00960,
529  .name = "at91sam3s4c",
530  .total_flash_size = 256 * 1024,
531  .total_sram_size = 48 * 1024,
532  .n_gpnvms = 2,
533  .n_banks = 1,
534  {
535 /* .bank[0] = { */
536  {
537  .probed = false,
538  .chip = NULL,
539  .bank = NULL,
540  .bank_number = 0,
541  .base_address = FLASH_BANK_BASE_S,
542  .controller_address = 0x400e0a00,
543  .flash_wait_states = 6, /* workaround silicon bug */
544  .present = 1,
545  .size_bytes = 256 * 1024,
546  .nsectors = 16,
547  .sector_size = 16384,
548  .page_size = 256,
549  },
550 /* .bank[1] = { */
551  {
552  .present = 0,
553  .probed = false,
554  .bank_number = 1,
555 
556  },
557  },
558  },
559 
560  {
561  .chipid_cidr = 0x28900960,
562  .name = "at91sam3s4b",
563  .total_flash_size = 256 * 1024,
564  .total_sram_size = 48 * 1024,
565  .n_gpnvms = 2,
566  .n_banks = 1,
567  {
568 /* .bank[0] = { */
569  {
570  .probed = false,
571  .chip = NULL,
572  .bank = NULL,
573  .bank_number = 0,
574  .base_address = FLASH_BANK_BASE_S,
575  .controller_address = 0x400e0a00,
576  .flash_wait_states = 6, /* workaround silicon bug */
577  .present = 1,
578  .size_bytes = 256 * 1024,
579  .nsectors = 16,
580  .sector_size = 16384,
581  .page_size = 256,
582  },
583 /* .bank[1] = { */
584  {
585  .present = 0,
586  .probed = false,
587  .bank_number = 1,
588 
589  },
590  },
591  },
592  {
593  .chipid_cidr = 0x28800960,
594  .name = "at91sam3s4a",
595  .total_flash_size = 256 * 1024,
596  .total_sram_size = 48 * 1024,
597  .n_gpnvms = 2,
598  .n_banks = 1,
599  {
600 /* .bank[0] = { */
601  {
602  .probed = false,
603  .chip = NULL,
604  .bank = NULL,
605  .bank_number = 0,
606  .base_address = FLASH_BANK_BASE_S,
607  .controller_address = 0x400e0a00,
608  .flash_wait_states = 6, /* workaround silicon bug */
609  .present = 1,
610  .size_bytes = 256 * 1024,
611  .nsectors = 16,
612  .sector_size = 16384,
613  .page_size = 256,
614  },
615 /* .bank[1] = { */
616  {
617  .present = 0,
618  .probed = false,
619  .bank_number = 1,
620 
621  },
622  },
623  },
624  {
625  .chipid_cidr = 0x28AA0760,
626  .name = "at91sam3s2c",
627  .total_flash_size = 128 * 1024,
628  .total_sram_size = 32 * 1024,
629  .n_gpnvms = 2,
630  .n_banks = 1,
631  {
632 /* .bank[0] = { */
633  {
634  .probed = false,
635  .chip = NULL,
636  .bank = NULL,
637  .bank_number = 0,
638  .base_address = FLASH_BANK_BASE_S,
639  .controller_address = 0x400e0a00,
640  .flash_wait_states = 6, /* workaround silicon bug */
641  .present = 1,
642  .size_bytes = 128 * 1024,
643  .nsectors = 8,
644  .sector_size = 16384,
645  .page_size = 256,
646  },
647 /* .bank[1] = { */
648  {
649  .present = 0,
650  .probed = false,
651  .bank_number = 1,
652 
653  },
654  },
655  },
656  {
657  .chipid_cidr = 0x289A0760,
658  .name = "at91sam3s2b",
659  .total_flash_size = 128 * 1024,
660  .total_sram_size = 32 * 1024,
661  .n_gpnvms = 2,
662  .n_banks = 1,
663  {
664 /* .bank[0] = { */
665  {
666  .probed = false,
667  .chip = NULL,
668  .bank = NULL,
669  .bank_number = 0,
670  .base_address = FLASH_BANK_BASE_S,
671  .controller_address = 0x400e0a00,
672  .flash_wait_states = 6, /* workaround silicon bug */
673  .present = 1,
674  .size_bytes = 128 * 1024,
675  .nsectors = 8,
676  .sector_size = 16384,
677  .page_size = 256,
678  },
679 /* .bank[1] = { */
680  {
681  .present = 0,
682  .probed = false,
683  .bank_number = 1,
684 
685  },
686  },
687  },
688  {
689  .chipid_cidr = 0x298B0A60,
690  .name = "at91sam3sd8a",
691  .total_flash_size = 512 * 1024,
692  .total_sram_size = 64 * 1024,
693  .n_gpnvms = 3,
694  .n_banks = 2,
695  {
696 /* .bank[0] = { */
697  {
698  .probed = false,
699  .chip = NULL,
700  .bank = NULL,
701  .bank_number = 0,
702  .base_address = FLASH_BANK0_BASE_SD,
703  .controller_address = 0x400e0a00,
704  .flash_wait_states = 6, /* workaround silicon bug */
705  .present = 1,
706  .size_bytes = 256 * 1024,
707  .nsectors = 16,
708  .sector_size = 32768,
709  .page_size = 256,
710  },
711 /* .bank[1] = { */
712  {
713  .probed = false,
714  .chip = NULL,
715  .bank = NULL,
716  .bank_number = 1,
717  .base_address = FLASH_BANK1_BASE_512K_SD,
718  .controller_address = 0x400e0a00,
719  .flash_wait_states = 6, /* workaround silicon bug */
720  .present = 1,
721  .size_bytes = 256 * 1024,
722  .nsectors = 16,
723  .sector_size = 32768,
724  .page_size = 256,
725  },
726  },
727  },
728  {
729  .chipid_cidr = 0x299B0A60,
730  .name = "at91sam3sd8b",
731  .total_flash_size = 512 * 1024,
732  .total_sram_size = 64 * 1024,
733  .n_gpnvms = 3,
734  .n_banks = 2,
735  {
736 /* .bank[0] = { */
737  {
738  .probed = false,
739  .chip = NULL,
740  .bank = NULL,
741  .bank_number = 0,
742  .base_address = FLASH_BANK0_BASE_SD,
743  .controller_address = 0x400e0a00,
744  .flash_wait_states = 6, /* workaround silicon bug */
745  .present = 1,
746  .size_bytes = 256 * 1024,
747  .nsectors = 16,
748  .sector_size = 32768,
749  .page_size = 256,
750  },
751 /* .bank[1] = { */
752  {
753  .probed = false,
754  .chip = NULL,
755  .bank = NULL,
756  .bank_number = 1,
757  .base_address = FLASH_BANK1_BASE_512K_SD,
758  .controller_address = 0x400e0a00,
759  .flash_wait_states = 6, /* workaround silicon bug */
760  .present = 1,
761  .size_bytes = 256 * 1024,
762  .nsectors = 16,
763  .sector_size = 32768,
764  .page_size = 256,
765  },
766  },
767  },
768  {
769  .chipid_cidr = 0x29ab0a60,
770  .name = "at91sam3sd8c",
771  .total_flash_size = 512 * 1024,
772  .total_sram_size = 64 * 1024,
773  .n_gpnvms = 3,
774  .n_banks = 2,
775  {
776 /* .bank[0] = { */
777  {
778  .probed = false,
779  .chip = NULL,
780  .bank = NULL,
781  .bank_number = 0,
782  .base_address = FLASH_BANK0_BASE_SD,
783  .controller_address = 0x400e0a00,
784  .flash_wait_states = 6, /* workaround silicon bug */
785  .present = 1,
786  .size_bytes = 256 * 1024,
787  .nsectors = 16,
788  .sector_size = 32768,
789  .page_size = 256,
790  },
791 /* .bank[1] = { */
792  {
793  .probed = false,
794  .chip = NULL,
795  .bank = NULL,
796  .bank_number = 1,
797  .base_address = FLASH_BANK1_BASE_512K_SD,
798  .controller_address = 0x400e0a00,
799  .flash_wait_states = 6, /* workaround silicon bug */
800  .present = 1,
801  .size_bytes = 256 * 1024,
802  .nsectors = 16,
803  .sector_size = 32768,
804  .page_size = 256,
805  },
806  },
807  },
808  {
809  .chipid_cidr = 0x288A0760,
810  .name = "at91sam3s2a",
811  .total_flash_size = 128 * 1024,
812  .total_sram_size = 32 * 1024,
813  .n_gpnvms = 2,
814  .n_banks = 1,
815  {
816 /* .bank[0] = { */
817  {
818  .probed = false,
819  .chip = NULL,
820  .bank = NULL,
821  .bank_number = 0,
822  .base_address = FLASH_BANK_BASE_S,
823  .controller_address = 0x400e0a00,
824  .flash_wait_states = 6, /* workaround silicon bug */
825  .present = 1,
826  .size_bytes = 128 * 1024,
827  .nsectors = 8,
828  .sector_size = 16384,
829  .page_size = 256,
830  },
831 /* .bank[1] = { */
832  {
833  .present = 0,
834  .probed = false,
835  .bank_number = 1,
836 
837  },
838  },
839  },
840  {
841  .chipid_cidr = 0x28A90560,
842  .name = "at91sam3s1c",
843  .total_flash_size = 64 * 1024,
844  .total_sram_size = 16 * 1024,
845  .n_gpnvms = 2,
846  .n_banks = 1,
847  {
848 /* .bank[0] = { */
849  {
850  .probed = false,
851  .chip = NULL,
852  .bank = NULL,
853  .bank_number = 0,
854  .base_address = FLASH_BANK_BASE_S,
855  .controller_address = 0x400e0a00,
856  .flash_wait_states = 6, /* workaround silicon bug */
857  .present = 1,
858  .size_bytes = 64 * 1024,
859  .nsectors = 4,
860  .sector_size = 16384,
861  .page_size = 256,
862  },
863 /* .bank[1] = { */
864  {
865  .present = 0,
866  .probed = false,
867  .bank_number = 1,
868 
869  },
870  },
871  },
872  {
873  .chipid_cidr = 0x28990560,
874  .name = "at91sam3s1b",
875  .total_flash_size = 64 * 1024,
876  .total_sram_size = 16 * 1024,
877  .n_gpnvms = 2,
878  .n_banks = 1,
879  {
880 /* .bank[0] = { */
881  {
882  .probed = false,
883  .chip = NULL,
884  .bank = NULL,
885  .bank_number = 0,
886  .base_address = FLASH_BANK_BASE_S,
887  .controller_address = 0x400e0a00,
888  .flash_wait_states = 6, /* workaround silicon bug */
889  .present = 1,
890  .size_bytes = 64 * 1024,
891  .nsectors = 4,
892  .sector_size = 16384,
893  .page_size = 256,
894  },
895 /* .bank[1] = { */
896  {
897  .present = 0,
898  .probed = false,
899  .bank_number = 1,
900 
901  },
902  },
903  },
904  {
905  .chipid_cidr = 0x28890560,
906  .name = "at91sam3s1a",
907  .total_flash_size = 64 * 1024,
908  .total_sram_size = 16 * 1024,
909  .n_gpnvms = 2,
910  .n_banks = 1,
911  {
912 /* .bank[0] = { */
913  {
914  .probed = false,
915  .chip = NULL,
916  .bank = NULL,
917  .bank_number = 0,
918  .base_address = FLASH_BANK_BASE_S,
919  .controller_address = 0x400e0a00,
920  .flash_wait_states = 6, /* workaround silicon bug */
921  .present = 1,
922  .size_bytes = 64 * 1024,
923  .nsectors = 4,
924  .sector_size = 16384,
925  .page_size = 256,
926  },
927 /* .bank[1] = { */
928  {
929  .present = 0,
930  .probed = false,
931  .bank_number = 1,
932 
933  },
934  },
935  },
936  {
937  .chipid_cidr = 0x288B0A60,
938  .name = "at91sam3s8a",
939  .total_flash_size = 256 * 2048,
940  .total_sram_size = 64 * 1024,
941  .n_gpnvms = 2,
942  .n_banks = 1,
943  {
944 /* .bank[0] = { */
945  {
946  .probed = false,
947  .chip = NULL,
948  .bank = NULL,
949  .bank_number = 0,
950  .base_address = FLASH_BANK_BASE_S,
951  .controller_address = 0x400e0a00,
952  .flash_wait_states = 6, /* workaround silicon bug */
953  .present = 1,
954  .size_bytes = 256 * 2048,
955  .nsectors = 16,
956  .sector_size = 32768,
957  .page_size = 256,
958  },
959 /* .bank[1] = { */
960  {
961  .present = 0,
962  .probed = false,
963  .bank_number = 1,
964 
965  },
966  },
967  },
968  {
969  .chipid_cidr = 0x289B0A60,
970  .name = "at91sam3s8b",
971  .total_flash_size = 256 * 2048,
972  .total_sram_size = 64 * 1024,
973  .n_gpnvms = 2,
974  .n_banks = 1,
975  {
976 /* .bank[0] = { */
977  {
978  .probed = false,
979  .chip = NULL,
980  .bank = NULL,
981  .bank_number = 0,
982  .base_address = FLASH_BANK_BASE_S,
983  .controller_address = 0x400e0a00,
984  .flash_wait_states = 6, /* workaround silicon bug */
985  .present = 1,
986  .size_bytes = 256 * 2048,
987  .nsectors = 16,
988  .sector_size = 32768,
989  .page_size = 256,
990  },
991 /* .bank[1] = { */
992  {
993  .present = 0,
994  .probed = false,
995  .bank_number = 1,
996 
997  },
998  },
999  },
1000  {
1001  .chipid_cidr = 0x28AB0A60,
1002  .name = "at91sam3s8c",
1003  .total_flash_size = 256 * 2048,
1004  .total_sram_size = 64 * 1024,
1005  .n_gpnvms = 2,
1006  .n_banks = 1,
1007  {
1008 /* .bank[0] = { */
1009  {
1010  .probed = false,
1011  .chip = NULL,
1012  .bank = NULL,
1013  .bank_number = 0,
1014  .base_address = FLASH_BANK_BASE_S,
1015  .controller_address = 0x400e0a00,
1016  .flash_wait_states = 6, /* workaround silicon bug */
1017  .present = 1,
1018  .size_bytes = 256 * 2048,
1019  .nsectors = 16,
1020  .sector_size = 32768,
1021  .page_size = 256,
1022  },
1023 /* .bank[1] = { */
1024  {
1025  .present = 0,
1026  .probed = false,
1027  .bank_number = 1,
1028 
1029  },
1030  },
1031  },
1032 
1033  /* Start at91sam3n* series */
1034  {
1035  .chipid_cidr = 0x29540960,
1036  .name = "at91sam3n4c",
1037  .total_flash_size = 256 * 1024,
1038  .total_sram_size = 24 * 1024,
1039  .n_gpnvms = 3,
1040  .n_banks = 1,
1041 
1042  /* System boots at address 0x0 */
1043  /* gpnvm[1] = selects boot code */
1044  /* if gpnvm[1] == 0 */
1045  /* boot is via "SAMBA" (rom) */
1046  /* else */
1047  /* boot is via FLASH */
1048  /* Selection is via gpnvm[2] */
1049  /* endif */
1050  /* */
1051  /* NOTE: banks 0 & 1 switch places */
1052  /* if gpnvm[2] == 0 */
1053  /* Bank0 is the boot rom */
1054  /* else */
1055  /* Bank1 is the boot rom */
1056  /* endif */
1057 /* .bank[0] = { */
1058  {
1059  {
1060  .probed = false,
1061  .chip = NULL,
1062  .bank = NULL,
1063  .bank_number = 0,
1064  .base_address = FLASH_BANK_BASE_N,
1065  .controller_address = 0x400e0A00,
1066  .flash_wait_states = 6, /* workaround silicon bug */
1067  .present = 1,
1068  .size_bytes = 256 * 1024,
1069  .nsectors = 16,
1070  .sector_size = 16384,
1071  .page_size = 256,
1072  },
1073 
1074 /* .bank[1] = { */
1075  {
1076  .present = 0,
1077  .probed = false,
1078  .bank_number = 1,
1079  },
1080  },
1081  },
1082 
1083  {
1084  .chipid_cidr = 0x29440960,
1085  .name = "at91sam3n4b",
1086  .total_flash_size = 256 * 1024,
1087  .total_sram_size = 24 * 1024,
1088  .n_gpnvms = 3,
1089  .n_banks = 1,
1090 
1091  /* System boots at address 0x0 */
1092  /* gpnvm[1] = selects boot code */
1093  /* if gpnvm[1] == 0 */
1094  /* boot is via "SAMBA" (rom) */
1095  /* else */
1096  /* boot is via FLASH */
1097  /* Selection is via gpnvm[2] */
1098  /* endif */
1099  /* */
1100  /* NOTE: banks 0 & 1 switch places */
1101  /* if gpnvm[2] == 0 */
1102  /* Bank0 is the boot rom */
1103  /* else */
1104  /* Bank1 is the boot rom */
1105  /* endif */
1106 /* .bank[0] = { */
1107  {
1108  {
1109  .probed = false,
1110  .chip = NULL,
1111  .bank = NULL,
1112  .bank_number = 0,
1113  .base_address = FLASH_BANK_BASE_N,
1114  .controller_address = 0x400e0A00,
1115  .flash_wait_states = 6, /* workaround silicon bug */
1116  .present = 1,
1117  .size_bytes = 256 * 1024,
1118  .nsectors = 16,
1119  .sector_size = 16384,
1120  .page_size = 256,
1121  },
1122 
1123 /* .bank[1] = { */
1124  {
1125  .present = 0,
1126  .probed = false,
1127  .bank_number = 1,
1128  },
1129  },
1130  },
1131 
1132  {
1133  .chipid_cidr = 0x29340960,
1134  .name = "at91sam3n4a",
1135  .total_flash_size = 256 * 1024,
1136  .total_sram_size = 24 * 1024,
1137  .n_gpnvms = 3,
1138  .n_banks = 1,
1139 
1140  /* System boots at address 0x0 */
1141  /* gpnvm[1] = selects boot code */
1142  /* if gpnvm[1] == 0 */
1143  /* boot is via "SAMBA" (rom) */
1144  /* else */
1145  /* boot is via FLASH */
1146  /* Selection is via gpnvm[2] */
1147  /* endif */
1148  /* */
1149  /* NOTE: banks 0 & 1 switch places */
1150  /* if gpnvm[2] == 0 */
1151  /* Bank0 is the boot rom */
1152  /* else */
1153  /* Bank1 is the boot rom */
1154  /* endif */
1155 /* .bank[0] = { */
1156  {
1157  {
1158  .probed = false,
1159  .chip = NULL,
1160  .bank = NULL,
1161  .bank_number = 0,
1162  .base_address = FLASH_BANK_BASE_N,
1163  .controller_address = 0x400e0A00,
1164  .flash_wait_states = 6, /* workaround silicon bug */
1165  .present = 1,
1166  .size_bytes = 256 * 1024,
1167  .nsectors = 16,
1168  .sector_size = 16384,
1169  .page_size = 256,
1170  },
1171 
1172 /* .bank[1] = { */
1173  {
1174  .present = 0,
1175  .probed = false,
1176  .bank_number = 1,
1177  },
1178  },
1179  },
1180 
1181  {
1182  .chipid_cidr = 0x29590760,
1183  .name = "at91sam3n2c",
1184  .total_flash_size = 128 * 1024,
1185  .total_sram_size = 16 * 1024,
1186  .n_gpnvms = 3,
1187  .n_banks = 1,
1188 
1189  /* System boots at address 0x0 */
1190  /* gpnvm[1] = selects boot code */
1191  /* if gpnvm[1] == 0 */
1192  /* boot is via "SAMBA" (rom) */
1193  /* else */
1194  /* boot is via FLASH */
1195  /* Selection is via gpnvm[2] */
1196  /* endif */
1197  /* */
1198  /* NOTE: banks 0 & 1 switch places */
1199  /* if gpnvm[2] == 0 */
1200  /* Bank0 is the boot rom */
1201  /* else */
1202  /* Bank1 is the boot rom */
1203  /* endif */
1204 /* .bank[0] = { */
1205  {
1206  {
1207  .probed = false,
1208  .chip = NULL,
1209  .bank = NULL,
1210  .bank_number = 0,
1211  .base_address = FLASH_BANK_BASE_N,
1212  .controller_address = 0x400e0A00,
1213  .flash_wait_states = 6, /* workaround silicon bug */
1214  .present = 1,
1215  .size_bytes = 128 * 1024,
1216  .nsectors = 8,
1217  .sector_size = 16384,
1218  .page_size = 256,
1219  },
1220 
1221 /* .bank[1] = { */
1222  {
1223  .present = 0,
1224  .probed = false,
1225  .bank_number = 1,
1226  },
1227  },
1228  },
1229 
1230  {
1231  .chipid_cidr = 0x29490760,
1232  .name = "at91sam3n2b",
1233  .total_flash_size = 128 * 1024,
1234  .total_sram_size = 16 * 1024,
1235  .n_gpnvms = 3,
1236  .n_banks = 1,
1237 
1238  /* System boots at address 0x0 */
1239  /* gpnvm[1] = selects boot code */
1240  /* if gpnvm[1] == 0 */
1241  /* boot is via "SAMBA" (rom) */
1242  /* else */
1243  /* boot is via FLASH */
1244  /* Selection is via gpnvm[2] */
1245  /* endif */
1246  /* */
1247  /* NOTE: banks 0 & 1 switch places */
1248  /* if gpnvm[2] == 0 */
1249  /* Bank0 is the boot rom */
1250  /* else */
1251  /* Bank1 is the boot rom */
1252  /* endif */
1253 /* .bank[0] = { */
1254  {
1255  {
1256  .probed = false,
1257  .chip = NULL,
1258  .bank = NULL,
1259  .bank_number = 0,
1260  .base_address = FLASH_BANK_BASE_N,
1261  .controller_address = 0x400e0A00,
1262  .flash_wait_states = 6, /* workaround silicon bug */
1263  .present = 1,
1264  .size_bytes = 128 * 1024,
1265  .nsectors = 8,
1266  .sector_size = 16384,
1267  .page_size = 256,
1268  },
1269 
1270 /* .bank[1] = { */
1271  {
1272  .present = 0,
1273  .probed = false,
1274  .bank_number = 1,
1275  },
1276  },
1277  },
1278 
1279  {
1280  .chipid_cidr = 0x29390760,
1281  .name = "at91sam3n2a",
1282  .total_flash_size = 128 * 1024,
1283  .total_sram_size = 16 * 1024,
1284  .n_gpnvms = 3,
1285  .n_banks = 1,
1286 
1287  /* System boots at address 0x0 */
1288  /* gpnvm[1] = selects boot code */
1289  /* if gpnvm[1] == 0 */
1290  /* boot is via "SAMBA" (rom) */
1291  /* else */
1292  /* boot is via FLASH */
1293  /* Selection is via gpnvm[2] */
1294  /* endif */
1295  /* */
1296  /* NOTE: banks 0 & 1 switch places */
1297  /* if gpnvm[2] == 0 */
1298  /* Bank0 is the boot rom */
1299  /* else */
1300  /* Bank1 is the boot rom */
1301  /* endif */
1302 /* .bank[0] = { */
1303  {
1304  {
1305  .probed = false,
1306  .chip = NULL,
1307  .bank = NULL,
1308  .bank_number = 0,
1309  .base_address = FLASH_BANK_BASE_N,
1310  .controller_address = 0x400e0A00,
1311  .flash_wait_states = 6, /* workaround silicon bug */
1312  .present = 1,
1313  .size_bytes = 128 * 1024,
1314  .nsectors = 8,
1315  .sector_size = 16384,
1316  .page_size = 256,
1317  },
1318 
1319 /* .bank[1] = { */
1320  {
1321  .present = 0,
1322  .probed = false,
1323  .bank_number = 1,
1324  },
1325  },
1326  },
1327 
1328  {
1329  .chipid_cidr = 0x29580560,
1330  .name = "at91sam3n1c",
1331  .total_flash_size = 64 * 1024,
1332  .total_sram_size = 8 * 1024,
1333  .n_gpnvms = 3,
1334  .n_banks = 1,
1335 
1336  /* System boots at address 0x0 */
1337  /* gpnvm[1] = selects boot code */
1338  /* if gpnvm[1] == 0 */
1339  /* boot is via "SAMBA" (rom) */
1340  /* else */
1341  /* boot is via FLASH */
1342  /* Selection is via gpnvm[2] */
1343  /* endif */
1344  /* */
1345  /* NOTE: banks 0 & 1 switch places */
1346  /* if gpnvm[2] == 0 */
1347  /* Bank0 is the boot rom */
1348  /* else */
1349  /* Bank1 is the boot rom */
1350  /* endif */
1351 /* .bank[0] = { */
1352  {
1353  {
1354  .probed = false,
1355  .chip = NULL,
1356  .bank = NULL,
1357  .bank_number = 0,
1358  .base_address = FLASH_BANK_BASE_N,
1359  .controller_address = 0x400e0A00,
1360  .flash_wait_states = 6, /* workaround silicon bug */
1361  .present = 1,
1362  .size_bytes = 64 * 1024,
1363  .nsectors = 4,
1364  .sector_size = 16384,
1365  .page_size = 256,
1366  },
1367 
1368 /* .bank[1] = { */
1369  {
1370  .present = 0,
1371  .probed = false,
1372  .bank_number = 1,
1373  },
1374  },
1375  },
1376 
1377  {
1378  .chipid_cidr = 0x29480560,
1379  .name = "at91sam3n1b",
1380  .total_flash_size = 64 * 1024,
1381  .total_sram_size = 8 * 1024,
1382  .n_gpnvms = 3,
1383  .n_banks = 1,
1384 
1385  /* System boots at address 0x0 */
1386  /* gpnvm[1] = selects boot code */
1387  /* if gpnvm[1] == 0 */
1388  /* boot is via "SAMBA" (rom) */
1389  /* else */
1390  /* boot is via FLASH */
1391  /* Selection is via gpnvm[2] */
1392  /* endif */
1393  /* */
1394  /* NOTE: banks 0 & 1 switch places */
1395  /* if gpnvm[2] == 0 */
1396  /* Bank0 is the boot rom */
1397  /* else */
1398  /* Bank1 is the boot rom */
1399  /* endif */
1400 /* .bank[0] = { */
1401  {
1402  {
1403  .probed = false,
1404  .chip = NULL,
1405  .bank = NULL,
1406  .bank_number = 0,
1407  .base_address = FLASH_BANK_BASE_N,
1408  .controller_address = 0x400e0A00,
1409  .flash_wait_states = 6, /* workaround silicon bug */
1410  .present = 1,
1411  .size_bytes = 64 * 1024,
1412  .nsectors = 4,
1413  .sector_size = 16384,
1414  .page_size = 256,
1415  },
1416 
1417 /* .bank[1] = { */
1418  {
1419  .present = 0,
1420  .probed = false,
1421  .bank_number = 1,
1422  },
1423  },
1424  },
1425 
1426  {
1427  .chipid_cidr = 0x29380560,
1428  .name = "at91sam3n1a",
1429  .total_flash_size = 64 * 1024,
1430  .total_sram_size = 8 * 1024,
1431  .n_gpnvms = 3,
1432  .n_banks = 1,
1433 
1434  /* System boots at address 0x0 */
1435  /* gpnvm[1] = selects boot code */
1436  /* if gpnvm[1] == 0 */
1437  /* boot is via "SAMBA" (rom) */
1438  /* else */
1439  /* boot is via FLASH */
1440  /* Selection is via gpnvm[2] */
1441  /* endif */
1442  /* */
1443  /* NOTE: banks 0 & 1 switch places */
1444  /* if gpnvm[2] == 0 */
1445  /* Bank0 is the boot rom */
1446  /* else */
1447  /* Bank1 is the boot rom */
1448  /* endif */
1449 /* .bank[0] = { */
1450  {
1451  {
1452  .probed = false,
1453  .chip = NULL,
1454  .bank = NULL,
1455  .bank_number = 0,
1456  .base_address = FLASH_BANK_BASE_N,
1457  .controller_address = 0x400e0A00,
1458  .flash_wait_states = 6, /* workaround silicon bug */
1459  .present = 1,
1460  .size_bytes = 64 * 1024,
1461  .nsectors = 4,
1462  .sector_size = 16384,
1463  .page_size = 256,
1464  },
1465 
1466 /* .bank[1] = { */
1467  {
1468  .present = 0,
1469  .probed = false,
1470  .bank_number = 1,
1471  },
1472  },
1473  },
1474 
1475  {
1476  .chipid_cidr = 0x29480360,
1477  .name = "at91sam3n0b",
1478  .total_flash_size = 32 * 1024,
1479  .total_sram_size = 8 * 1024,
1480  .n_gpnvms = 3,
1481  .n_banks = 1,
1482 
1483 /* .bank[0] = { */
1484  {
1485  {
1486  .probed = false,
1487  .chip = NULL,
1488  .bank = NULL,
1489  .bank_number = 0,
1490  .base_address = FLASH_BANK_BASE_N,
1491  .controller_address = 0x400e0A00,
1492  .flash_wait_states = 6, /* workaround silicon bug */
1493  .present = 1,
1494  .size_bytes = 32 * 1024,
1495  .nsectors = 2,
1496  .sector_size = 16384,
1497  .page_size = 256,
1498  },
1499 
1500 /* .bank[1] = { */
1501  {
1502  .present = 0,
1503  .probed = false,
1504  .bank_number = 1,
1505  },
1506  },
1507  },
1508 
1509  {
1510  .chipid_cidr = 0x29380360,
1511  .name = "at91sam3n0a",
1512  .total_flash_size = 32 * 1024,
1513  .total_sram_size = 8 * 1024,
1514  .n_gpnvms = 3,
1515  .n_banks = 1,
1516 
1517 /* .bank[0] = { */
1518  {
1519  {
1520  .probed = false,
1521  .chip = NULL,
1522  .bank = NULL,
1523  .bank_number = 0,
1524  .base_address = FLASH_BANK_BASE_N,
1525  .controller_address = 0x400e0A00,
1526  .flash_wait_states = 6, /* workaround silicon bug */
1527  .present = 1,
1528  .size_bytes = 32 * 1024,
1529  .nsectors = 2,
1530  .sector_size = 16384,
1531  .page_size = 256,
1532  },
1533 
1534 /* .bank[1] = { */
1535  {
1536  .present = 0,
1537  .probed = false,
1538  .bank_number = 1,
1539  },
1540  },
1541  },
1542 
1543  {
1544  .chipid_cidr = 0x29450260,
1545  .name = "at91sam3n00b",
1546  .total_flash_size = 16 * 1024,
1547  .total_sram_size = 4 * 1024,
1548  .n_gpnvms = 3,
1549  .n_banks = 1,
1550 
1551 /* .bank[0] = { */
1552  {
1553  {
1554  .probed = false,
1555  .chip = NULL,
1556  .bank = NULL,
1557  .bank_number = 0,
1558  .base_address = FLASH_BANK_BASE_N,
1559  .controller_address = 0x400e0A00,
1560  .flash_wait_states = 6, /* workaround silicon bug */
1561  .present = 1,
1562  .size_bytes = 16 * 1024,
1563  .nsectors = 1,
1564  .sector_size = 16384,
1565  .page_size = 256,
1566  },
1567 
1568 /* .bank[1] = { */
1569  {
1570  .present = 0,
1571  .probed = false,
1572  .bank_number = 1,
1573  },
1574  },
1575  },
1576 
1577  {
1578  .chipid_cidr = 0x29350260,
1579  .name = "at91sam3n00a",
1580  .total_flash_size = 16 * 1024,
1581  .total_sram_size = 4 * 1024,
1582  .n_gpnvms = 3,
1583  .n_banks = 1,
1584 
1585 /* .bank[0] = { */
1586  {
1587  {
1588  .probed = false,
1589  .chip = NULL,
1590  .bank = NULL,
1591  .bank_number = 0,
1592  .base_address = FLASH_BANK_BASE_N,
1593  .controller_address = 0x400e0A00,
1594  .flash_wait_states = 6, /* workaround silicon bug */
1595  .present = 1,
1596  .size_bytes = 16 * 1024,
1597  .nsectors = 1,
1598  .sector_size = 16384,
1599  .page_size = 256,
1600  },
1601 
1602 /* .bank[1] = { */
1603  {
1604  .present = 0,
1605  .probed = false,
1606  .bank_number = 1,
1607  },
1608  },
1609  },
1610 
1611 
1612  /* Start at91sam3a series*/
1613  /* System boots at address 0x0 */
1614  /* gpnvm[1] = selects boot code */
1615  /* if gpnvm[1] == 0 */
1616  /* boot is via "SAMBA" (rom) */
1617  /* else */
1618  /* boot is via FLASH */
1619  /* Selection is via gpnvm[2] */
1620  /* endif */
1621  /* */
1622  /* NOTE: banks 0 & 1 switch places */
1623  /* if gpnvm[2] == 0 */
1624  /* Bank0 is the boot rom */
1625  /* else */
1626  /* Bank1 is the boot rom */
1627  /* endif */
1628 
1629  {
1630  .chipid_cidr = 0x283E0A60,
1631  .name = "at91sam3a8c",
1632  .total_flash_size = 512 * 1024,
1633  .total_sram_size = 96 * 1024,
1634  .n_gpnvms = 3,
1635  .n_banks = 2,
1636  {
1637 /* .bank[0] = { */
1638  {
1639  .probed = false,
1640  .chip = NULL,
1641  .bank = NULL,
1642  .bank_number = 0,
1643  .base_address = FLASH_BANK0_BASE_AX,
1644  .controller_address = 0x400e0a00,
1645  .flash_wait_states = 6, /* workaround silicon bug */
1646  .present = 1,
1647  .size_bytes = 256 * 1024,
1648  .nsectors = 16,
1649  .sector_size = 16384,
1650  .page_size = 256,
1651  },
1652 /* .bank[1] = { */
1653  {
1654  .probed = false,
1655  .chip = NULL,
1656  .bank = NULL,
1657  .bank_number = 1,
1658  .base_address = FLASH_BANK1_BASE_512K_AX,
1659  .controller_address = 0x400e0c00,
1660  .flash_wait_states = 6, /* workaround silicon bug */
1661  .present = 1,
1662  .size_bytes = 256 * 1024,
1663  .nsectors = 16,
1664  .sector_size = 16384,
1665  .page_size = 256,
1666 
1667  },
1668  },
1669  },
1670  {
1671  .chipid_cidr = 0x283B0960,
1672  .name = "at91sam3a4c",
1673  .total_flash_size = 256 * 1024,
1674  .total_sram_size = 64 * 1024,
1675  .n_gpnvms = 3,
1676  .n_banks = 2,
1677  {
1678 /* .bank[0] = { */
1679  {
1680  .probed = false,
1681  .chip = NULL,
1682  .bank = NULL,
1683  .bank_number = 0,
1684  .base_address = FLASH_BANK0_BASE_AX,
1685  .controller_address = 0x400e0a00,
1686  .flash_wait_states = 6, /* workaround silicon bug */
1687  .present = 1,
1688  .size_bytes = 128 * 1024,
1689  .nsectors = 8,
1690  .sector_size = 16384,
1691  .page_size = 256,
1692  },
1693 /* .bank[1] = { */
1694  {
1695  .probed = false,
1696  .chip = NULL,
1697  .bank = NULL,
1698  .bank_number = 1,
1699  .base_address = FLASH_BANK1_BASE_256K_AX,
1700  .controller_address = 0x400e0c00,
1701  .flash_wait_states = 6, /* workaround silicon bug */
1702  .present = 1,
1703  .size_bytes = 128 * 1024,
1704  .nsectors = 8,
1705  .sector_size = 16384,
1706  .page_size = 256,
1707 
1708  },
1709  },
1710  },
1711 
1712  /* Start at91sam3x* series */
1713  /* System boots at address 0x0 */
1714  /* gpnvm[1] = selects boot code */
1715  /* if gpnvm[1] == 0 */
1716  /* boot is via "SAMBA" (rom) */
1717  /* else */
1718  /* boot is via FLASH */
1719  /* Selection is via gpnvm[2] */
1720  /* endif */
1721  /* */
1722  /* NOTE: banks 0 & 1 switch places */
1723  /* if gpnvm[2] == 0 */
1724  /* Bank0 is the boot rom */
1725  /* else */
1726  /* Bank1 is the boot rom */
1727  /* endif */
1728  /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1729  {
1730  .chipid_cidr = 0x286E0A20,
1731  .name = "at91sam3x8h - ES",
1732  .total_flash_size = 512 * 1024,
1733  .total_sram_size = 96 * 1024,
1734  .n_gpnvms = 3,
1735  .n_banks = 2,
1736  {
1737 /* .bank[0] = { */
1738  {
1739  .probed = false,
1740  .chip = NULL,
1741  .bank = NULL,
1742  .bank_number = 0,
1743  .base_address = FLASH_BANK0_BASE_AX,
1744  .controller_address = 0x400e0a00,
1745  .flash_wait_states = 6, /* workaround silicon bug */
1746  .present = 1,
1747  .size_bytes = 256 * 1024,
1748  .nsectors = 16,
1749  .sector_size = 16384,
1750  .page_size = 256,
1751  },
1752 /* .bank[1] = { */
1753  {
1754  .probed = false,
1755  .chip = NULL,
1756  .bank = NULL,
1757  .bank_number = 1,
1758  .base_address = FLASH_BANK1_BASE_512K_AX,
1759  .controller_address = 0x400e0c00,
1760  .flash_wait_states = 6, /* workaround silicon bug */
1761  .present = 1,
1762  .size_bytes = 256 * 1024,
1763  .nsectors = 16,
1764  .sector_size = 16384,
1765  .page_size = 256,
1766 
1767  },
1768  },
1769  },
1770  /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1771  {
1772  .chipid_cidr = 0x286E0A60,
1773  .name = "at91sam3x8h",
1774  .total_flash_size = 512 * 1024,
1775  .total_sram_size = 96 * 1024,
1776  .n_gpnvms = 3,
1777  .n_banks = 2,
1778  {
1779 /* .bank[0] = { */
1780  {
1781  .probed = false,
1782  .chip = NULL,
1783  .bank = NULL,
1784  .bank_number = 0,
1785  .base_address = FLASH_BANK0_BASE_AX,
1786  .controller_address = 0x400e0a00,
1787  .flash_wait_states = 6, /* workaround silicon bug */
1788  .present = 1,
1789  .size_bytes = 256 * 1024,
1790  .nsectors = 16,
1791  .sector_size = 16384,
1792  .page_size = 256,
1793  },
1794 /* .bank[1] = { */
1795  {
1796  .probed = false,
1797  .chip = NULL,
1798  .bank = NULL,
1799  .bank_number = 1,
1800  .base_address = FLASH_BANK1_BASE_512K_AX,
1801  .controller_address = 0x400e0c00,
1802  .flash_wait_states = 6, /* workaround silicon bug */
1803  .present = 1,
1804  .size_bytes = 256 * 1024,
1805  .nsectors = 16,
1806  .sector_size = 16384,
1807  .page_size = 256,
1808 
1809  },
1810  },
1811  },
1812  {
1813  .chipid_cidr = 0x285E0A60,
1814  .name = "at91sam3x8e",
1815  .total_flash_size = 512 * 1024,
1816  .total_sram_size = 96 * 1024,
1817  .n_gpnvms = 3,
1818  .n_banks = 2,
1819  {
1820 /* .bank[0] = { */
1821  {
1822  .probed = false,
1823  .chip = NULL,
1824  .bank = NULL,
1825  .bank_number = 0,
1826  .base_address = FLASH_BANK0_BASE_AX,
1827  .controller_address = 0x400e0a00,
1828  .flash_wait_states = 6, /* workaround silicon bug */
1829  .present = 1,
1830  .size_bytes = 256 * 1024,
1831  .nsectors = 16,
1832  .sector_size = 16384,
1833  .page_size = 256,
1834  },
1835 /* .bank[1] = { */
1836  {
1837  .probed = false,
1838  .chip = NULL,
1839  .bank = NULL,
1840  .bank_number = 1,
1841  .base_address = FLASH_BANK1_BASE_512K_AX,
1842  .controller_address = 0x400e0c00,
1843  .flash_wait_states = 6, /* workaround silicon bug */
1844  .present = 1,
1845  .size_bytes = 256 * 1024,
1846  .nsectors = 16,
1847  .sector_size = 16384,
1848  .page_size = 256,
1849 
1850  },
1851  },
1852  },
1853  {
1854  .chipid_cidr = 0x284E0A60,
1855  .name = "at91sam3x8c",
1856  .total_flash_size = 512 * 1024,
1857  .total_sram_size = 96 * 1024,
1858  .n_gpnvms = 3,
1859  .n_banks = 2,
1860  {
1861 /* .bank[0] = { */
1862  {
1863  .probed = false,
1864  .chip = NULL,
1865  .bank = NULL,
1866  .bank_number = 0,
1867  .base_address = FLASH_BANK0_BASE_AX,
1868  .controller_address = 0x400e0a00,
1869  .flash_wait_states = 6, /* workaround silicon bug */
1870  .present = 1,
1871  .size_bytes = 256 * 1024,
1872  .nsectors = 16,
1873  .sector_size = 16384,
1874  .page_size = 256,
1875  },
1876 /* .bank[1] = { */
1877  {
1878  .probed = false,
1879  .chip = NULL,
1880  .bank = NULL,
1881  .bank_number = 1,
1882  .base_address = FLASH_BANK1_BASE_512K_AX,
1883  .controller_address = 0x400e0c00,
1884  .flash_wait_states = 6, /* workaround silicon bug */
1885  .present = 1,
1886  .size_bytes = 256 * 1024,
1887  .nsectors = 16,
1888  .sector_size = 16384,
1889  .page_size = 256,
1890 
1891  },
1892  },
1893  },
1894  {
1895  .chipid_cidr = 0x285B0960,
1896  .name = "at91sam3x4e",
1897  .total_flash_size = 256 * 1024,
1898  .total_sram_size = 64 * 1024,
1899  .n_gpnvms = 3,
1900  .n_banks = 2,
1901  {
1902 /* .bank[0] = { */
1903  {
1904  .probed = false,
1905  .chip = NULL,
1906  .bank = NULL,
1907  .bank_number = 0,
1908  .base_address = FLASH_BANK0_BASE_AX,
1909  .controller_address = 0x400e0a00,
1910  .flash_wait_states = 6, /* workaround silicon bug */
1911  .present = 1,
1912  .size_bytes = 128 * 1024,
1913  .nsectors = 8,
1914  .sector_size = 16384,
1915  .page_size = 256,
1916  },
1917 /* .bank[1] = { */
1918  {
1919  .probed = false,
1920  .chip = NULL,
1921  .bank = NULL,
1922  .bank_number = 1,
1923  .base_address = FLASH_BANK1_BASE_256K_AX,
1924  .controller_address = 0x400e0c00,
1925  .flash_wait_states = 6, /* workaround silicon bug */
1926  .present = 1,
1927  .size_bytes = 128 * 1024,
1928  .nsectors = 8,
1929  .sector_size = 16384,
1930  .page_size = 256,
1931 
1932  },
1933  },
1934  },
1935  {
1936  .chipid_cidr = 0x284B0960,
1937  .name = "at91sam3x4c",
1938  .total_flash_size = 256 * 1024,
1939  .total_sram_size = 64 * 1024,
1940  .n_gpnvms = 3,
1941  .n_banks = 2,
1942  {
1943 /* .bank[0] = { */
1944  {
1945  .probed = false,
1946  .chip = NULL,
1947  .bank = NULL,
1948  .bank_number = 0,
1949  .base_address = FLASH_BANK0_BASE_AX,
1950  .controller_address = 0x400e0a00,
1951  .flash_wait_states = 6, /* workaround silicon bug */
1952  .present = 1,
1953  .size_bytes = 128 * 1024,
1954  .nsectors = 8,
1955  .sector_size = 16384,
1956  .page_size = 256,
1957  },
1958 /* .bank[1] = { */
1959  {
1960  .probed = false,
1961  .chip = NULL,
1962  .bank = NULL,
1963  .bank_number = 1,
1964  .base_address = FLASH_BANK1_BASE_256K_AX,
1965  .controller_address = 0x400e0c00,
1966  .flash_wait_states = 6, /* workaround silicon bug */
1967  .present = 1,
1968  .size_bytes = 128 * 1024,
1969  .nsectors = 8,
1970  .sector_size = 16384,
1971  .page_size = 256,
1972 
1973  },
1974  },
1975  },
1976  /* terminate */
1977  {
1978  .chipid_cidr = 0,
1979  .name = NULL,
1980  }
1981 };
1982 
1983 /* Globals above */
1984 /***********************************************************************
1985  **********************************************************************
1986  **********************************************************************
1987  **********************************************************************
1988  **********************************************************************
1989  **********************************************************************/
1990 /* *ATMEL* style code - from the SAM3 driver code */
1991 
1998 static int efc_get_status(struct sam3_bank_private *private, uint32_t *v)
1999 {
2000  int r;
2001  r = target_read_u32(private->chip->target,
2002  private->controller_address + OFFSET_EFC_FSR,
2003  v);
2004  LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
2005  (unsigned int)(*v),
2006  ((unsigned int)((*v >> 2) & 1)),
2007  ((unsigned int)((*v >> 1) & 1)),
2008  ((unsigned int)((*v >> 0) & 1)));
2009 
2010  return r;
2011 }
2012 
2018 static int efc_get_result(struct sam3_bank_private *private, uint32_t *v)
2019 {
2020  int r;
2021  uint32_t rv;
2022  r = target_read_u32(private->chip->target,
2023  private->controller_address + OFFSET_EFC_FRR,
2024  &rv);
2025  if (v)
2026  *v = rv;
2027  LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
2028  return r;
2029 }
2030 
2031 static int efc_start_command(struct sam3_bank_private *private,
2032  unsigned int command, unsigned int argument)
2033 {
2034  uint32_t n, v;
2035  int r;
2036  int retry;
2037 
2038  retry = 0;
2039 do_retry:
2040 
2041  /* Check command & argument */
2042  switch (command) {
2043  case AT91C_EFC_FCMD_WP:
2044  case AT91C_EFC_FCMD_WPL:
2045  case AT91C_EFC_FCMD_EWP:
2046  case AT91C_EFC_FCMD_EWPL:
2047  /* case AT91C_EFC_FCMD_EPL: */
2048  /* case AT91C_EFC_FCMD_EPA: */
2049  case AT91C_EFC_FCMD_SLB:
2050  case AT91C_EFC_FCMD_CLB:
2051  n = (private->size_bytes / private->page_size);
2052  if (argument >= n)
2053  LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n);
2054  break;
2055 
2056  case AT91C_EFC_FCMD_SFB:
2057  case AT91C_EFC_FCMD_CFB:
2058  if (argument >= private->chip->details.n_gpnvms) {
2059  LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
2060  private->chip->details.n_gpnvms);
2061  }
2062  break;
2063 
2064  case AT91C_EFC_FCMD_GETD:
2065  case AT91C_EFC_FCMD_EA:
2066  case AT91C_EFC_FCMD_GLB:
2067  case AT91C_EFC_FCMD_GFB:
2068  case AT91C_EFC_FCMD_STUI:
2069  case AT91C_EFC_FCMD_SPUI:
2070  if (argument != 0)
2071  LOG_ERROR("Argument is meaningless for cmd: %d", command);
2072  break;
2073  default:
2074  LOG_ERROR("Unknown command %d", command);
2075  break;
2076  }
2077 
2078  if (command == AT91C_EFC_FCMD_SPUI) {
2079  /* this is a very special situation. */
2080  /* Situation (1) - error/retry - see below */
2081  /* And we are being called recursively */
2082  /* Situation (2) - normal, finished reading unique id */
2083  } else {
2084  /* it should be "ready" */
2085  efc_get_status(private, &v);
2086  if (v & 1) {
2087  /* then it is ready */
2088  /* we go on */
2089  } else {
2090  if (retry) {
2091  /* we have done this before */
2092  /* the controller is not responding. */
2093  LOG_ERROR("flash controller(%d) is not ready! Error",
2094  private->bank_number);
2095  return ERROR_FAIL;
2096  } else {
2097  retry++;
2098  LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
2099  private->bank_number);
2100  /* we do that by issuing the *STOP* command */
2101  efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
2102  /* above is recursive, and further recursion is blocked by */
2103  /* if (command == AT91C_EFC_FCMD_SPUI) above */
2104  goto do_retry;
2105  }
2106  }
2107  }
2108 
2109  v = (0x5A << 24) | (argument << 8) | command;
2110  LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
2111  r = target_write_u32(private->bank->target,
2112  private->controller_address + OFFSET_EFC_FCR, v);
2113  if (r != ERROR_OK)
2114  LOG_DEBUG("Error Write failed");
2115  return r;
2116 }
2117 
2125 static int efc_perform_command(struct sam3_bank_private *private,
2126  unsigned int command,
2127  unsigned int argument,
2128  uint32_t *status)
2129 {
2130 
2131  int r;
2132  uint32_t v;
2133  int64_t ms_now, ms_end;
2134 
2135  /* default */
2136  if (status)
2137  *status = 0;
2138 
2139  r = efc_start_command(private, command, argument);
2140  if (r != ERROR_OK)
2141  return r;
2142 
2143  ms_end = 500 + timeval_ms();
2144 
2145  do {
2146  r = efc_get_status(private, &v);
2147  if (r != ERROR_OK)
2148  return r;
2149  ms_now = timeval_ms();
2150  if (ms_now > ms_end) {
2151  /* error */
2152  LOG_ERROR("Command timeout");
2153  return ERROR_FAIL;
2154  }
2155  } while ((v & 1) == 0);
2156 
2157  /* error bits.. */
2158  if (status)
2159  *status = (v & 0x6);
2160  return ERROR_OK;
2161 
2162 }
2163 
2169 static int flashd_read_uid(struct sam3_bank_private *private)
2170 {
2171  int r;
2172  uint32_t v;
2173  int x;
2174  /* assume 0 */
2175  private->chip->cfg.unique_id[0] = 0;
2176  private->chip->cfg.unique_id[1] = 0;
2177  private->chip->cfg.unique_id[2] = 0;
2178  private->chip->cfg.unique_id[3] = 0;
2179 
2180  LOG_DEBUG("Begin");
2181  r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
2182  if (r < 0)
2183  return r;
2184 
2185  for (x = 0; x < 4; x++) {
2186  r = target_read_u32(private->chip->target,
2187  private->bank->base + (x * 4),
2188  &v);
2189  if (r < 0)
2190  return r;
2191  private->chip->cfg.unique_id[x] = v;
2192  }
2193 
2194  r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
2195  LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2196  r,
2197  (unsigned int)(private->chip->cfg.unique_id[0]),
2198  (unsigned int)(private->chip->cfg.unique_id[1]),
2199  (unsigned int)(private->chip->cfg.unique_id[2]),
2200  (unsigned int)(private->chip->cfg.unique_id[3]));
2201  return r;
2202 
2203 }
2204 
2209 static int flashd_erase_entire_bank(struct sam3_bank_private *private)
2210 {
2211  LOG_DEBUG("Here");
2212  return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
2213 }
2214 
2221 /* ------------------------------------------------------------------------------ */
2222 static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm, unsigned int *puthere)
2223 {
2224  uint32_t v;
2225  int r;
2226 
2227  LOG_DEBUG("Here");
2228  if (private->bank_number != 0) {
2229  LOG_ERROR("GPNVM only works with Bank0");
2230  return ERROR_FAIL;
2231  }
2232 
2233  if (gpnvm >= private->chip->details.n_gpnvms) {
2234  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2235  gpnvm, private->chip->details.n_gpnvms);
2236  return ERROR_FAIL;
2237  }
2238 
2239  /* Get GPNVMs status */
2240  r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
2241  if (r != ERROR_OK) {
2242  LOG_ERROR("Failed");
2243  return r;
2244  }
2245 
2246  r = efc_get_result(private, &v);
2247 
2248  if (puthere) {
2249  /* Check if GPNVM is set */
2250  /* get the bit and make it a 0/1 */
2251  *puthere = (v >> gpnvm) & 1;
2252  }
2253 
2254  return r;
2255 }
2256 
2263 static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
2264 {
2265  int r;
2266  unsigned int v;
2267 
2268  LOG_DEBUG("Here");
2269  if (private->bank_number != 0) {
2270  LOG_ERROR("GPNVM only works with Bank0");
2271  return ERROR_FAIL;
2272  }
2273 
2274  if (gpnvm >= private->chip->details.n_gpnvms) {
2275  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2276  gpnvm, private->chip->details.n_gpnvms);
2277  return ERROR_FAIL;
2278  }
2279 
2280  r = flashd_get_gpnvm(private, gpnvm, &v);
2281  if (r != ERROR_OK) {
2282  LOG_DEBUG("Failed: %d", r);
2283  return r;
2284  }
2285  r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2286  LOG_DEBUG("End: %d", r);
2287  return r;
2288 }
2289 
2295 static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
2296 {
2297  int r;
2298  unsigned int v;
2299 
2300  if (private->bank_number != 0) {
2301  LOG_ERROR("GPNVM only works with Bank0");
2302  return ERROR_FAIL;
2303  }
2304 
2305  if (gpnvm >= private->chip->details.n_gpnvms) {
2306  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2307  gpnvm, private->chip->details.n_gpnvms);
2308  return ERROR_FAIL;
2309  }
2310 
2311  r = flashd_get_gpnvm(private, gpnvm, &v);
2312  if (r != ERROR_OK)
2313  return r;
2314  if (v) {
2315  /* already set */
2316  r = ERROR_OK;
2317  } else {
2318  /* set it */
2319  r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2320  }
2321  return r;
2322 }
2323 
2329 static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v)
2330 {
2331  int r;
2332  LOG_DEBUG("Here");
2333  r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
2334  if (r == ERROR_OK)
2335  r = efc_get_result(private, v);
2336  LOG_DEBUG("End: %d", r);
2337  return r;
2338 }
2339 
2347 static int flashd_unlock(struct sam3_bank_private *private,
2348  unsigned int start_sector,
2349  unsigned int end_sector)
2350 {
2351  int r;
2352  uint32_t status;
2353  uint32_t pg;
2354  uint32_t pages_per_sector;
2355 
2356  pages_per_sector = private->sector_size / private->page_size;
2357 
2358  /* Unlock all pages */
2359  while (start_sector <= end_sector) {
2360  pg = start_sector * pages_per_sector;
2361 
2362  r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
2363  if (r != ERROR_OK)
2364  return r;
2365  start_sector++;
2366  }
2367 
2368  return ERROR_OK;
2369 }
2370 
2377 static int flashd_lock(struct sam3_bank_private *private,
2378  unsigned int start_sector,
2379  unsigned int end_sector)
2380 {
2381  uint32_t status;
2382  uint32_t pg;
2383  uint32_t pages_per_sector;
2384  int r;
2385 
2386  pages_per_sector = private->sector_size / private->page_size;
2387 
2388  /* Lock all pages */
2389  while (start_sector <= end_sector) {
2390  pg = start_sector * pages_per_sector;
2391 
2392  r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
2393  if (r != ERROR_OK)
2394  return r;
2395  start_sector++;
2396  }
2397  return ERROR_OK;
2398 }
2399 
2400 /****** END SAM3 CODE ********/
2401 
2402 /* begin helpful debug code */
2403 /* print the fieldname, the field value, in dec & hex, and return field value */
2404 static uint32_t sam3_reg_fieldname(struct sam3_chip *chip,
2405  const char *regname,
2406  uint32_t value,
2407  unsigned int shift,
2408  unsigned int width)
2409 {
2410  uint32_t v;
2411  int hwidth, dwidth;
2412 
2413 
2414  /* extract the field */
2415  v = value >> shift;
2416  v = v & ((1 << width)-1);
2417  if (width <= 16) {
2418  hwidth = 4;
2419  dwidth = 5;
2420  } else {
2421  hwidth = 8;
2422  dwidth = 12;
2423  }
2424 
2425  /* show the basics */
2426  LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
2427  REG_NAME_WIDTH, regname,
2428  dwidth, v,
2429  hwidth, v);
2430  return v;
2431 }
2432 
2433 static const char _unknown[] = "unknown";
2434 static const char *const eproc_names[] = {
2435  _unknown, /* 0 */
2436  "arm946es", /* 1 */
2437  "arm7tdmi", /* 2 */
2438  "Cortex-M3", /* 3 */
2439  "arm920t", /* 4 */
2440  "arm926ejs", /* 5 */
2441  _unknown, /* 6 */
2442  _unknown, /* 7 */
2443  _unknown, /* 8 */
2444  _unknown, /* 9 */
2445  _unknown, /* 10 */
2446  _unknown, /* 11 */
2447  _unknown, /* 12 */
2448  _unknown, /* 13 */
2449  _unknown, /* 14 */
2450  _unknown, /* 15 */
2451 };
2452 
2453 #define nvpsize2 nvpsize /* these two tables are identical */
2454 static const char *const nvpsize[] = {
2455  "none", /* 0 */
2456  "8K bytes", /* 1 */
2457  "16K bytes", /* 2 */
2458  "32K bytes", /* 3 */
2459  _unknown, /* 4 */
2460  "64K bytes", /* 5 */
2461  _unknown, /* 6 */
2462  "128K bytes", /* 7 */
2463  _unknown, /* 8 */
2464  "256K bytes", /* 9 */
2465  "512K bytes", /* 10 */
2466  _unknown, /* 11 */
2467  "1024K bytes", /* 12 */
2468  _unknown, /* 13 */
2469  "2048K bytes", /* 14 */
2470  _unknown, /* 15 */
2471 };
2472 
2473 static const char *const sramsize[] = {
2474  "48K Bytes", /* 0 */
2475  "1K Bytes", /* 1 */
2476  "2K Bytes", /* 2 */
2477  "6K Bytes", /* 3 */
2478  "112K Bytes", /* 4 */
2479  "4K Bytes", /* 5 */
2480  "80K Bytes", /* 6 */
2481  "160K Bytes", /* 7 */
2482  "8K Bytes", /* 8 */
2483  "16K Bytes", /* 9 */
2484  "32K Bytes", /* 10 */
2485  "64K Bytes", /* 11 */
2486  "128K Bytes", /* 12 */
2487  "256K Bytes", /* 13 */
2488  "96K Bytes", /* 14 */
2489  "512K Bytes", /* 15 */
2490 
2491 };
2492 
2493 static const struct archnames { unsigned int value; const char *name; } archnames[] = {
2494  { 0x19, "AT91SAM9xx Series" },
2495  { 0x29, "AT91SAM9XExx Series" },
2496  { 0x34, "AT91x34 Series" },
2497  { 0x37, "CAP7 Series" },
2498  { 0x39, "CAP9 Series" },
2499  { 0x3B, "CAP11 Series" },
2500  { 0x40, "AT91x40 Series" },
2501  { 0x42, "AT91x42 Series" },
2502  { 0x55, "AT91x55 Series" },
2503  { 0x60, "AT91SAM7Axx Series" },
2504  { 0x61, "AT91SAM7AQxx Series" },
2505  { 0x63, "AT91x63 Series" },
2506  { 0x70, "AT91SAM7Sxx Series" },
2507  { 0x71, "AT91SAM7XCxx Series" },
2508  { 0x72, "AT91SAM7SExx Series" },
2509  { 0x73, "AT91SAM7Lxx Series" },
2510  { 0x75, "AT91SAM7Xxx Series" },
2511  { 0x76, "AT91SAM7SLxx Series" },
2512  { 0x80, "ATSAM3UxC Series (100-pin version)" },
2513  { 0x81, "ATSAM3UxE Series (144-pin version)" },
2514  { 0x83, "ATSAM3AxC Series (100-pin version)" },
2515  { 0x84, "ATSAM3XxC Series (100-pin version)" },
2516  { 0x85, "ATSAM3XxE Series (144-pin version)" },
2517  { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2518  { 0x88, "ATSAM3SxA Series (48-pin version)" },
2519  { 0x89, "ATSAM3SxB Series (64-pin version)" },
2520  { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2521  { 0x92, "AT91x92 Series" },
2522  { 0x93, "ATSAM3NxA Series (48-pin version)" },
2523  { 0x94, "ATSAM3NxB Series (64-pin version)" },
2524  { 0x95, "ATSAM3NxC Series (100-pin version)" },
2525  { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2526  { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2527  { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2528  { 0xA5, "ATSAM5A" },
2529  { 0xF0, "AT75Cxx Series" },
2530  { -1, NULL },
2531 };
2532 
2533 static const char *const nvptype[] = {
2534  "rom", /* 0 */
2535  "romless or onchip flash", /* 1 */
2536  "embedded flash memory",/* 2 */
2537  "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2538  "sram emulating flash", /* 4 */
2539  _unknown, /* 5 */
2540  _unknown, /* 6 */
2541  _unknown, /* 7 */
2542 };
2543 
2544 static const char *_yes_or_no(uint32_t v)
2545 {
2546  if (v)
2547  return "YES";
2548  else
2549  return "NO";
2550 }
2551 
2552 static const char *const _rc_freq[] = {
2553  "4 MHz", "8 MHz", "12 MHz", "reserved"
2554 };
2555 
2556 static void sam3_explain_ckgr_mor(struct sam3_chip *chip)
2557 {
2558  uint32_t v;
2559  uint32_t rcen;
2560 
2561  v = sam3_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
2562  LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2563  v = sam3_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
2564  LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2565  rcen = sam3_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
2566  LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2567  v = sam3_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
2568  LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2569 
2570  chip->cfg.rc_freq = 0;
2571  if (rcen) {
2572  switch (v) {
2573  case 0:
2574  chip->cfg.rc_freq = 4 * 1000 * 1000;
2575  break;
2576  case 1:
2577  chip->cfg.rc_freq = 8 * 1000 * 1000;
2578  break;
2579  case 2:
2580  chip->cfg.rc_freq = 12 * 1000 * 1000;
2581  break;
2582  default:
2583  chip->cfg.rc_freq = 0;
2584  break;
2585  }
2586  }
2587 
2588  v = sam3_reg_fieldname(chip, "MOSCXTST", chip->cfg.CKGR_MOR, 8, 8);
2589  LOG_USER("(startup clks, time= %f uSecs)",
2590  ((float)(v * 1000000)) / ((float)(chip->cfg.slow_freq)));
2591  v = sam3_reg_fieldname(chip, "MOSCSEL", chip->cfg.CKGR_MOR, 24, 1);
2592  LOG_USER("(mainosc source: %s)",
2593  v ? "external xtal" : "internal RC");
2594 
2595  v = sam3_reg_fieldname(chip, "CFDEN", chip->cfg.CKGR_MOR, 25, 1);
2596  LOG_USER("(clock failure enabled: %s)",
2597  _yes_or_no(v));
2598 }
2599 
2600 static void sam3_explain_chipid_cidr(struct sam3_chip *chip)
2601 {
2602  int x;
2603  uint32_t v;
2604  const char *cp;
2605 
2606  sam3_reg_fieldname(chip, "Version", chip->cfg.CHIPID_CIDR, 0, 5);
2607  LOG_USER_N("\n");
2608 
2609  v = sam3_reg_fieldname(chip, "EPROC", chip->cfg.CHIPID_CIDR, 5, 3);
2610  LOG_USER("%s", eproc_names[v]);
2611 
2612  v = sam3_reg_fieldname(chip, "NVPSIZE", chip->cfg.CHIPID_CIDR, 8, 4);
2613  LOG_USER("%s", nvpsize[v]);
2614 
2615  v = sam3_reg_fieldname(chip, "NVPSIZE2", chip->cfg.CHIPID_CIDR, 12, 4);
2616  LOG_USER("%s", nvpsize2[v]);
2617 
2618  v = sam3_reg_fieldname(chip, "SRAMSIZE", chip->cfg.CHIPID_CIDR, 16, 4);
2619  LOG_USER("%s", sramsize[v]);
2620 
2621  v = sam3_reg_fieldname(chip, "ARCH", chip->cfg.CHIPID_CIDR, 20, 8);
2622  cp = _unknown;
2623  for (x = 0; archnames[x].name; x++) {
2624  if (v == archnames[x].value) {
2625  cp = archnames[x].name;
2626  break;
2627  }
2628  }
2629 
2630  LOG_USER("%s", cp);
2631 
2632  v = sam3_reg_fieldname(chip, "NVPTYP", chip->cfg.CHIPID_CIDR, 28, 3);
2633  LOG_USER("%s", nvptype[v]);
2634 
2635  v = sam3_reg_fieldname(chip, "EXTID", chip->cfg.CHIPID_CIDR, 31, 1);
2636  LOG_USER("(exists: %s)", _yes_or_no(v));
2637 }
2638 
2639 static void sam3_explain_ckgr_mcfr(struct sam3_chip *chip)
2640 {
2641  uint32_t v;
2642 
2643  v = sam3_reg_fieldname(chip, "MAINFRDY", chip->cfg.CKGR_MCFR, 16, 1);
2644  LOG_USER("(main ready: %s)", _yes_or_no(v));
2645 
2646  v = sam3_reg_fieldname(chip, "MAINF", chip->cfg.CKGR_MCFR, 0, 16);
2647 
2648  v = (v * chip->cfg.slow_freq) / 16;
2649  chip->cfg.mainosc_freq = v;
2650 
2651  LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2652  _tomhz(v),
2653  (uint32_t)(chip->cfg.slow_freq / 1000),
2654  (uint32_t)(chip->cfg.slow_freq % 1000));
2655 }
2656 
2657 static void sam3_explain_ckgr_plla(struct sam3_chip *chip)
2658 {
2659  uint32_t mula, diva;
2660 
2661  diva = sam3_reg_fieldname(chip, "DIVA", chip->cfg.CKGR_PLLAR, 0, 8);
2662  LOG_USER_N("\n");
2663  mula = sam3_reg_fieldname(chip, "MULA", chip->cfg.CKGR_PLLAR, 16, 11);
2664  LOG_USER_N("\n");
2665  chip->cfg.plla_freq = 0;
2666  if (mula == 0)
2667  LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2668  else if (diva == 0)
2669  LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2670  else if (diva >= 1) {
2671  chip->cfg.plla_freq = (chip->cfg.mainosc_freq * (mula + 1) / diva);
2672  LOG_USER("\tPLLA Freq: %3.03f MHz",
2673  _tomhz(chip->cfg.plla_freq));
2674  }
2675 }
2676 
2677 static void sam3_explain_mckr(struct sam3_chip *chip)
2678 {
2679  uint32_t css, pres, fin = 0;
2680  int pdiv = 0;
2681  const char *cp = NULL;
2682 
2683  css = sam3_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2);
2684  switch (css & 3) {
2685  case 0:
2686  fin = chip->cfg.slow_freq;
2687  cp = "slowclk";
2688  break;
2689  case 1:
2690  fin = chip->cfg.mainosc_freq;
2691  cp = "mainosc";
2692  break;
2693  case 2:
2694  fin = chip->cfg.plla_freq;
2695  cp = "plla";
2696  break;
2697  case 3:
2698  if (chip->cfg.CKGR_UCKR & (1 << 16)) {
2699  fin = 480 * 1000 * 1000;
2700  cp = "upll";
2701  } else {
2702  fin = 0;
2703  cp = "upll (*ERROR* UPLL is disabled)";
2704  }
2705  break;
2706  default:
2707  assert(0);
2708  break;
2709  }
2710 
2711  LOG_USER("%s (%3.03f Mhz)",
2712  cp,
2713  _tomhz(fin));
2714  pres = sam3_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3);
2715  switch (pres & 0x07) {
2716  case 0:
2717  pdiv = 1;
2718  cp = "selected clock";
2719  break;
2720  case 1:
2721  pdiv = 2;
2722  cp = "clock/2";
2723  break;
2724  case 2:
2725  pdiv = 4;
2726  cp = "clock/4";
2727  break;
2728  case 3:
2729  pdiv = 8;
2730  cp = "clock/8";
2731  break;
2732  case 4:
2733  pdiv = 16;
2734  cp = "clock/16";
2735  break;
2736  case 5:
2737  pdiv = 32;
2738  cp = "clock/32";
2739  break;
2740  case 6:
2741  pdiv = 64;
2742  cp = "clock/64";
2743  break;
2744  case 7:
2745  pdiv = 6;
2746  cp = "clock/6";
2747  break;
2748  default:
2749  assert(0);
2750  break;
2751  }
2752  LOG_USER("(%s)", cp);
2753  fin = fin / pdiv;
2754  /* sam3 has a *SINGLE* clock - */
2755  /* other at91 series parts have divisors for these. */
2756  chip->cfg.cpu_freq = fin;
2757  chip->cfg.mclk_freq = fin;
2758  chip->cfg.fclk_freq = fin;
2759  LOG_USER("\t\tResult CPU Freq: %3.03f",
2760  _tomhz(fin));
2761 }
2762 
2763 #if 0
2764 static struct sam3_chip *target2sam3(struct target *target)
2765 {
2766  struct sam3_chip *chip;
2767 
2768  if (!target)
2769  return NULL;
2770 
2771  chip = all_sam3_chips;
2772  while (chip) {
2773  if (chip->target == target)
2774  break; /* return below */
2775  else
2776  chip = chip->next;
2777  }
2778  return chip;
2779 }
2780 #endif
2781 
2782 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *cfg, const struct sam3_reg_list *list)
2783 {
2784  /* this function exists to help */
2785  /* keep funky offsetof() errors */
2786  /* and casting from causing bugs */
2787 
2788  /* By using prototypes - we can detect what would */
2789  /* be casting errors. */
2790 
2791  return (uint32_t *)(void *)(((char *)(cfg)) + list->struct_offset);
2792 }
2793 
2794 
2795 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2796  struct sam3_cfg, \
2797  NAME), # NAME, FUNC }
2798 static const struct sam3_reg_list sam3_all_regs[] = {
2799  SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2800  SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2801  SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2802  SAM3_ENTRY(CKGR_UCKR, NULL),
2803  SAM3_ENTRY(PMC_FSMR, NULL),
2804  SAM3_ENTRY(PMC_FSPR, NULL),
2805  SAM3_ENTRY(PMC_IMR, NULL),
2806  SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2807  SAM3_ENTRY(PMC_PCK0, NULL),
2808  SAM3_ENTRY(PMC_PCK1, NULL),
2809  SAM3_ENTRY(PMC_PCK2, NULL),
2810  SAM3_ENTRY(PMC_PCSR, NULL),
2811  SAM3_ENTRY(PMC_SCSR, NULL),
2812  SAM3_ENTRY(PMC_SR, NULL),
2813  SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2814  SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2815  SAM3_ENTRY(CHIPID_EXID, NULL),
2816  SAM3_ENTRY(CHIPID_EXID2, NULL),
2817  /* TERMINATE THE LIST */
2818  { .name = NULL }
2819 };
2820 #undef SAM3_ENTRY
2821 
2822 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2823 {
2824  return bank->driver_priv;
2825 }
2826 
2831 static const struct sam3_reg_list *sam3_get_reg(struct sam3_chip *chip, uint32_t *goes_here)
2832 {
2833  const struct sam3_reg_list *reg;
2834 
2835  reg = &(sam3_all_regs[0]);
2836  while (reg->name) {
2837  uint32_t *possible;
2838 
2839  /* calculate where this one go.. */
2840  /* it is "possibly" this register. */
2841 
2842  possible = ((uint32_t *)(void *)(((char *)(&(chip->cfg))) + reg->struct_offset));
2843 
2844  /* well? Is it this register */
2845  if (possible == goes_here) {
2846  /* Jump for joy! */
2847  return reg;
2848  }
2849 
2850  /* next... */
2851  reg++;
2852  }
2853  /* This is *TOTAL*PANIC* - we are totally screwed. */
2854  LOG_ERROR("INVALID SAM3 REGISTER");
2855  return NULL;
2856 }
2857 
2858 static int sam3_read_this_reg(struct sam3_chip *chip, uint32_t *goes_here)
2859 {
2860  const struct sam3_reg_list *reg;
2861  int r;
2862 
2863  reg = sam3_get_reg(chip, goes_here);
2864  if (!reg)
2865  return ERROR_FAIL;
2866 
2867  r = target_read_u32(chip->target, reg->address, goes_here);
2868  if (r != ERROR_OK) {
2869  LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08" PRIx32 ", Err: %d",
2870  reg->name, reg->address, r);
2871  }
2872  return r;
2873 }
2874 
2875 static int sam3_read_all_regs(struct sam3_chip *chip)
2876 {
2877  int r;
2878  const struct sam3_reg_list *reg;
2879 
2880  reg = &(sam3_all_regs[0]);
2881  while (reg->name) {
2882  r = sam3_read_this_reg(chip,
2883  sam3_get_reg_ptr(&(chip->cfg), reg));
2884  if (r != ERROR_OK) {
2885  LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08" PRIx32 ", Error: %d",
2886  reg->name, reg->address, r);
2887  return r;
2888  }
2889  reg++;
2890  }
2891 
2892  /* Chip identification register
2893  *
2894  * Unfortunately, the chip identification register is not at
2895  * a constant address across all of the SAM3 series'. As a
2896  * consequence, a simple heuristic is used to find where it's
2897  * at...
2898  *
2899  * If the contents at the first address is zero, then we know
2900  * that the second address is where the chip id register is.
2901  * We can deduce this because for those SAM's that have the
2902  * chip id @ 0x400e0940, the first address, 0x400e0740, is
2903  * located in the memory map of the Power Management Controller
2904  * (PMC). Furthermore, the address is not used by the PMC.
2905  * So when read, the memory controller returns zero.*/
2906  if (chip->cfg.CHIPID_CIDR == 0) {
2907  /*Put the correct CIDR and EXID values in the chip structure */
2908  chip->cfg.CHIPID_CIDR = chip->cfg.CHIPID_CIDR2;
2909  chip->cfg.CHIPID_EXID = chip->cfg.CHIPID_EXID2;
2910  }
2911  return ERROR_OK;
2912 }
2913 
2914 static int sam3_get_info(struct sam3_chip *chip)
2915 {
2916  const struct sam3_reg_list *reg;
2917  uint32_t regval;
2918 
2919  reg = &(sam3_all_regs[0]);
2920  while (reg->name) {
2921  /* display all regs */
2922  LOG_DEBUG("Start: %s", reg->name);
2923  regval = *sam3_get_reg_ptr(&(chip->cfg), reg);
2924  LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2925  REG_NAME_WIDTH,
2926  reg->name,
2927  reg->address,
2928  regval);
2929  if (reg->explain_func)
2930  (*(reg->explain_func))(chip);
2931  LOG_DEBUG("End: %s", reg->name);
2932  reg++;
2933  }
2934  LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
2935  LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
2936  LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
2937  LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
2938  LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
2939 
2940  LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32,
2941  chip->cfg.unique_id[0],
2942  chip->cfg.unique_id[1],
2943  chip->cfg.unique_id[2],
2944  chip->cfg.unique_id[3]);
2945 
2946  return ERROR_OK;
2947 }
2948 
2949 static int sam3_protect_check(struct flash_bank *bank)
2950 {
2951  int r;
2952  uint32_t v = 0;
2953  unsigned int x;
2954  struct sam3_bank_private *private;
2955 
2956  LOG_DEBUG("Begin");
2957  if (bank->target->state != TARGET_HALTED) {
2958  LOG_ERROR("Target not halted");
2959  return ERROR_TARGET_NOT_HALTED;
2960  }
2961 
2962  private = get_sam3_bank_private(bank);
2963  if (!private) {
2964  LOG_ERROR("no private for this bank?");
2965  return ERROR_FAIL;
2966  }
2967  if (!(private->probed))
2968  return ERROR_FLASH_BANK_NOT_PROBED;
2969 
2970  r = flashd_get_lock_bits(private, &v);
2971  if (r != ERROR_OK) {
2972  LOG_DEBUG("Failed: %d", r);
2973  return r;
2974  }
2975 
2976  for (x = 0; x < private->nsectors; x++)
2977  bank->sectors[x].is_protected = (!!(v & (1 << x)));
2978  LOG_DEBUG("Done");
2979  return ERROR_OK;
2980 }
2981 
2982 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2983 {
2984  struct sam3_chip *chip;
2985 
2986  chip = all_sam3_chips;
2987 
2988  /* is this an existing chip? */
2989  while (chip) {
2990  if (chip->target == bank->target)
2991  break;
2992  chip = chip->next;
2993  }
2994 
2995  if (!chip) {
2996  /* this is a *NEW* chip */
2997  chip = calloc(1, sizeof(struct sam3_chip));
2998  if (!chip) {
2999  LOG_ERROR("NO RAM!");
3000  return ERROR_FAIL;
3001  }
3002  chip->target = bank->target;
3003  /* insert at head */
3004  chip->next = all_sam3_chips;
3005  all_sam3_chips = chip;
3006  chip->target = bank->target;
3007  /* assumption is this runs at 32khz */
3008  chip->cfg.slow_freq = 32768;
3009  chip->probed = false;
3010  }
3011 
3012  switch (bank->base) {
3013  /* at91sam3s and at91sam3n series only has bank 0*/
3014  /* at91sam3u and at91sam3ax series has the same address for bank 0*/
3015  case FLASH_BANK_BASE_S:
3016  case FLASH_BANK0_BASE_U:
3017  bank->driver_priv = &chip->details.bank[0];
3018  bank->bank_number = 0;
3019  chip->details.bank[0].chip = chip;
3020  chip->details.bank[0].bank = bank;
3021  break;
3022 
3023  /* Bank 1 of at91sam3u or at91sam3ax series */
3024  case FLASH_BANK1_BASE_U:
3025  case FLASH_BANK1_BASE_256K_AX:
3026  case FLASH_BANK1_BASE_512K_AX:
3027  bank->driver_priv = &chip->details.bank[1];
3028  bank->bank_number = 1;
3029  chip->details.bank[1].chip = chip;
3030  chip->details.bank[1].bank = bank;
3031  break;
3032 
3033  default:
3034  LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x or 0x%08x "
3035  "[at91sam3u series] or 0x%08x [at91sam3s series] or "
3036  "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
3037  bank->base,
3038  FLASH_BANK0_BASE_U,
3039  FLASH_BANK1_BASE_U,
3040  FLASH_BANK_BASE_S,
3041  FLASH_BANK_BASE_N,
3042  FLASH_BANK0_BASE_AX,
3043  FLASH_BANK1_BASE_256K_AX,
3044  FLASH_BANK1_BASE_512K_AX);
3045  return ERROR_FAIL;
3046  }
3047 
3048  /* we initialize after probing. */
3049  return ERROR_OK;
3050 }
3051 
3057 static void sam3_free_driver_priv(struct flash_bank *bank)
3058 {
3059  struct sam3_chip *chip = all_sam3_chips;
3060  while (chip) {
3061  struct sam3_chip *next = chip->next;
3062  free(chip);
3063  chip = next;
3064  }
3065  all_sam3_chips = NULL;
3066 }
3067 
3068 static int sam3_get_details(struct sam3_bank_private *private)
3069 {
3070  const struct sam3_chip_details *details;
3071  struct sam3_chip *chip;
3072  struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
3073  unsigned int x;
3074 
3075  LOG_DEBUG("Begin");
3076  details = all_sam3_details;
3077  while (details->name) {
3078  /* Compare cidr without version bits */
3079  if (((details->chipid_cidr ^ private->chip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
3080  break;
3081  else
3082  details++;
3083  }
3084  if (!details->name) {
3085  LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
3086  (unsigned int)(private->chip->cfg.CHIPID_CIDR));
3087  /* Help the victim, print details about the chip */
3088  LOG_INFO("SAM3 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
3089  private->chip->cfg.CHIPID_CIDR);
3090  sam3_explain_chipid_cidr(private->chip);
3091  return ERROR_FAIL;
3092  }
3093 
3094  /* DANGER: THERE ARE DRAGONS HERE */
3095 
3096  /* get our chip - it is going */
3097  /* to be over-written shortly */
3098  chip = private->chip;
3099 
3100  /* Note that, in reality: */
3101  /* */
3102  /* private = &(chip->details.bank[0]) */
3103  /* or private = &(chip->details.bank[1]) */
3104  /* */
3105 
3106  /* save the "bank" pointers */
3107  for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
3108  saved_banks[x] = chip->details.bank[x].bank;
3109 
3110  /* Overwrite the "details" structure. */
3111  memcpy(&(private->chip->details),
3112  details,
3113  sizeof(private->chip->details));
3114 
3115  /* now fix the ghosted pointers */
3116  for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3117  chip->details.bank[x].chip = chip;
3118  chip->details.bank[x].bank = saved_banks[x];
3119  }
3120 
3121  /* update the *BANK*SIZE* */
3122 
3123  LOG_DEBUG("End");
3124  return ERROR_OK;
3125 }
3126 
3127 static int _sam3_probe(struct flash_bank *bank, int noise)
3128 {
3129  int r;
3130  struct sam3_bank_private *private;
3131 
3132 
3133  LOG_DEBUG("Begin: Bank: %u, Noise: %d", bank->bank_number, noise);
3134  if (bank->target->state != TARGET_HALTED) {
3135  LOG_ERROR("Target not halted");
3136  return ERROR_TARGET_NOT_HALTED;
3137  }
3138 
3139  private = get_sam3_bank_private(bank);
3140  if (!private) {
3141  LOG_ERROR("Invalid/unknown bank number");
3142  return ERROR_FAIL;
3143  }
3144 
3145  r = sam3_read_all_regs(private->chip);
3146  if (r != ERROR_OK)
3147  return r;
3148 
3149  LOG_DEBUG("Here");
3150  if (private->chip->probed)
3151  r = sam3_get_info(private->chip);
3152  else
3153  r = sam3_get_details(private);
3154  if (r != ERROR_OK)
3155  return r;
3156 
3157  /* update the flash bank size */
3158  for (unsigned int x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3159  if (bank->base == private->chip->details.bank[x].base_address) {
3160  bank->size = private->chip->details.bank[x].size_bytes;
3161  break;
3162  }
3163  }
3164 
3165  if (!bank->sectors) {
3166  bank->sectors = calloc(private->nsectors, (sizeof((bank->sectors)[0])));
3167  if (!bank->sectors) {
3168  LOG_ERROR("No memory!");
3169  return ERROR_FAIL;
3170  }
3171  bank->num_sectors = private->nsectors;
3172 
3173  for (unsigned int x = 0; x < bank->num_sectors; x++) {
3174  bank->sectors[x].size = private->sector_size;
3175  bank->sectors[x].offset = x * (private->sector_size);
3176  /* mark as unknown */
3177  bank->sectors[x].is_erased = -1;
3178  bank->sectors[x].is_protected = -1;
3179  }
3180  }
3181 
3182  private->probed = true;
3183 
3184  r = sam3_protect_check(bank);
3185  if (r != ERROR_OK)
3186  return r;
3187 
3188  LOG_DEBUG("Bank = %d, nbanks = %d",
3189  private->bank_number, private->chip->details.n_banks);
3190  if ((private->bank_number + 1) == private->chip->details.n_banks) {
3191  /* read unique id, */
3192  /* it appears to be associated with the *last* flash bank. */
3193  flashd_read_uid(private);
3194  }
3195 
3196  return r;
3197 }
3198 
3199 static int sam3_probe(struct flash_bank *bank)
3200 {
3201  return _sam3_probe(bank, 1);
3202 }
3203 
3204 static int sam3_auto_probe(struct flash_bank *bank)
3205 {
3206  return _sam3_probe(bank, 0);
3207 }
3208 
3209 static int sam3_erase(struct flash_bank *bank, unsigned int first,
3210  unsigned int last)
3211 {
3212  struct sam3_bank_private *private;
3213  int r;
3214 
3215  LOG_DEBUG("Here");
3216  if (bank->target->state != TARGET_HALTED) {
3217  LOG_ERROR("Target not halted");
3218  return ERROR_TARGET_NOT_HALTED;
3219  }
3220 
3221  r = sam3_auto_probe(bank);
3222  if (r != ERROR_OK) {
3223  LOG_DEBUG("Here,r=%d", r);
3224  return r;
3225  }
3226 
3227  private = get_sam3_bank_private(bank);
3228  if (!(private->probed))
3229  return ERROR_FLASH_BANK_NOT_PROBED;
3230 
3231  if ((first == 0) && ((last + 1) == private->nsectors)) {
3232  /* whole chip */
3233  LOG_DEBUG("Here");
3234  return flashd_erase_entire_bank(private);
3235  }
3236  LOG_INFO("sam3 auto-erases while programming (request ignored)");
3237  return ERROR_OK;
3238 }
3239 
3240 static int sam3_protect(struct flash_bank *bank, int set, unsigned int first,
3241  unsigned int last)
3242 {
3243  struct sam3_bank_private *private;
3244  int r;
3245 
3246  LOG_DEBUG("Here");
3247  if (bank->target->state != TARGET_HALTED) {
3248  LOG_ERROR("Target not halted");
3249  return ERROR_TARGET_NOT_HALTED;
3250  }
3251 
3252  private = get_sam3_bank_private(bank);
3253  if (!(private->probed))
3254  return ERROR_FLASH_BANK_NOT_PROBED;
3255 
3256  if (set)
3257  r = flashd_lock(private, first, last);
3258  else
3259  r = flashd_unlock(private, first, last);
3260  LOG_DEBUG("End: r=%d", r);
3261 
3262  return r;
3263 
3264 }
3265 
3266 static int sam3_page_read(struct sam3_bank_private *private, unsigned int pagenum, uint8_t *buf)
3267 {
3268  uint32_t adr;
3269  int r;
3270 
3271  adr = pagenum * private->page_size;
3272  adr += private->base_address;
3273 
3274  r = target_read_memory(private->chip->target,
3275  adr,
3276  4, /* THIS*MUST*BE* in 32bit values */
3277  private->page_size / 4,
3278  buf);
3279  if (r != ERROR_OK)
3280  LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3281  (unsigned int)(adr));
3282  return r;
3283 }
3284 
3285 static int sam3_page_write(struct sam3_bank_private *private, unsigned int pagenum, const uint8_t *buf)
3286 {
3287  uint32_t adr;
3288  uint32_t status;
3289  uint32_t fmr; /* EEFC Flash Mode Register */
3290  int r;
3291 
3292  adr = pagenum * private->page_size;
3293  adr += private->base_address;
3294 
3295  /* Get flash mode register value */
3296  r = target_read_u32(private->chip->target, private->controller_address, &fmr);
3297  if (r != ERROR_OK)
3298  LOG_DEBUG("Error Read failed: read flash mode register");
3299 
3300  /* Clear flash wait state field */
3301  fmr &= 0xfffff0ff;
3302 
3303  /* set FWS (flash wait states) field in the FMR (flash mode register) */
3304  fmr |= (private->flash_wait_states << 8);
3305 
3306  LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3307  r = target_write_u32(private->bank->target, private->controller_address, fmr);
3308  if (r != ERROR_OK)
3309  LOG_DEBUG("Error Write failed: set flash mode register");
3310 
3311  LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3312  r = target_write_memory(private->chip->target,
3313  adr,
3314  4, /* THIS*MUST*BE* in 32bit values */
3315  private->page_size / 4,
3316  buf);
3317  if (r != ERROR_OK) {
3318  LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3319  (unsigned int)(adr));
3320  return r;
3321  }
3322 
3323  r = efc_perform_command(private,
3324  /* send Erase & Write Page */
3325  AT91C_EFC_FCMD_EWP,
3326  pagenum,
3327  &status);
3328 
3329  if (r != ERROR_OK)
3330  LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3331  (unsigned int)(adr));
3332  if (status & (1 << 2)) {
3333  LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3334  return ERROR_FAIL;
3335  }
3336  if (status & (1 << 1)) {
3337  LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3338  return ERROR_FAIL;
3339  }
3340  return ERROR_OK;
3341 }
3342 
3343 static int sam3_write(struct flash_bank *bank,
3344  const uint8_t *buffer,
3345  uint32_t offset,
3346  uint32_t count)
3347 {
3348  int n;
3349  unsigned int page_cur;
3350  unsigned int page_end;
3351  int r;
3352  unsigned int page_offset;
3353  struct sam3_bank_private *private;
3354  uint8_t *pagebuffer;
3355 
3356  /* in case we bail further below, set this to null */
3357  pagebuffer = NULL;
3358 
3359  /* ignore dumb requests */
3360  if (count == 0) {
3361  r = ERROR_OK;
3362  goto done;
3363  }
3364 
3365  if (bank->target->state != TARGET_HALTED) {
3366  LOG_ERROR("Target not halted");
3367  r = ERROR_TARGET_NOT_HALTED;
3368  goto done;
3369  }
3370 
3371  private = get_sam3_bank_private(bank);
3372  if (!(private->probed)) {
3373  r = ERROR_FLASH_BANK_NOT_PROBED;
3374  goto done;
3375  }
3376 
3377  if ((offset + count) > private->size_bytes) {
3378  LOG_ERROR("Flash write error - past end of bank");
3379  LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3380  (unsigned int)(offset),
3381  (unsigned int)(count),
3382  (unsigned int)(private->size_bytes));
3383  r = ERROR_FAIL;
3384  goto done;
3385  }
3386 
3387  pagebuffer = malloc(private->page_size);
3388  if (!pagebuffer) {
3389  LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size));
3390  r = ERROR_FAIL;
3391  goto done;
3392  }
3393 
3394  /* what page do we start & end in? */
3395  page_cur = offset / private->page_size;
3396  page_end = (offset + count - 1) / private->page_size;
3397 
3398  LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3399  LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3400 
3401  /* Special case: all one page */
3402  /* */
3403  /* Otherwise: */
3404  /* (1) non-aligned start */
3405  /* (2) body pages */
3406  /* (3) non-aligned end. */
3407 
3408  /* Handle special case - all one page. */
3409  if (page_cur == page_end) {
3410  LOG_DEBUG("Special case, all in one page");
3411  r = sam3_page_read(private, page_cur, pagebuffer);
3412  if (r != ERROR_OK)
3413  goto done;
3414 
3415  page_offset = (offset & (private->page_size-1));
3416  memcpy(pagebuffer + page_offset,
3417  buffer,
3418  count);
3419 
3420  r = sam3_page_write(private, page_cur, pagebuffer);
3421  if (r != ERROR_OK)
3422  goto done;
3423  r = ERROR_OK;
3424  goto done;
3425  }
3426 
3427  /* non-aligned start */
3428  page_offset = offset & (private->page_size - 1);
3429  if (page_offset) {
3430  LOG_DEBUG("Not-Aligned start");
3431  /* read the partial */
3432  r = sam3_page_read(private, page_cur, pagebuffer);
3433  if (r != ERROR_OK)
3434  goto done;
3435 
3436  /* over-write with new data */
3437  n = (private->page_size - page_offset);
3438  memcpy(pagebuffer + page_offset,
3439  buffer,
3440  n);
3441 
3442  r = sam3_page_write(private, page_cur, pagebuffer);
3443  if (r != ERROR_OK)
3444  goto done;
3445 
3446  count -= n;
3447  offset += n;
3448  buffer += n;
3449  page_cur++;
3450  }
3451 
3452  /* By checking that offset is correct here, we also
3453  fix a clang warning */
3454  assert(offset % private->page_size == 0);
3455 
3456  /* intermediate large pages */
3457  /* also - the final *terminal* */
3458  /* if that terminal page is a full page */
3459  LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3460  (int)page_cur, (int)page_end, (unsigned int)(count));
3461 
3462  while ((page_cur < page_end) &&
3463  (count >= private->page_size)) {
3464  r = sam3_page_write(private, page_cur, buffer);
3465  if (r != ERROR_OK)
3466  goto done;
3467  count -= private->page_size;
3468  buffer += private->page_size;
3469  page_cur += 1;
3470  }
3471 
3472  /* terminal partial page? */
3473  if (count) {
3474  LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3475  /* we have a partial page */
3476  r = sam3_page_read(private, page_cur, pagebuffer);
3477  if (r != ERROR_OK)
3478  goto done;
3479  /* data goes at start */
3480  memcpy(pagebuffer, buffer, count);
3481  r = sam3_page_write(private, page_cur, pagebuffer);
3482  if (r != ERROR_OK)
3483  goto done;
3484  }
3485  LOG_DEBUG("Done!");
3486  r = ERROR_OK;
3487 done:
3488  free(pagebuffer);
3489  return r;
3490 }
3491 
3492 COMMAND_HANDLER(sam3_handle_info_command)
3493 {
3494  struct sam3_chip *chip;
3495  chip = get_current_sam3(CMD);
3496  if (!chip)
3497  return ERROR_OK;
3498 
3499  unsigned int x;
3500  int r;
3501 
3502  /* bank0 must exist before we can do anything */
3503  if (!chip->details.bank[0].bank) {
3504  x = 0;
3505 need_define:
3506  command_print(CMD,
3507  "Please define bank %d via command: flash bank %s ... ",
3508  x,
3509  at91sam3_flash.name);
3510  return ERROR_FAIL;
3511  }
3512 
3513  /* if bank 0 is not probed, then probe it */
3514  if (!(chip->details.bank[0].probed)) {
3515  r = sam3_auto_probe(chip->details.bank[0].bank);
3516  if (r != ERROR_OK)
3517  return ERROR_FAIL;
3518  }
3519  /* above guarantees the "chip details" structure is valid */
3520  /* and thus, bank private areas are valid */
3521  /* and we have a SAM3 chip, what a concept! */
3522 
3523  /* auto-probe other banks, 0 done above */
3524  for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3525  /* skip banks not present */
3526  if (!(chip->details.bank[x].present))
3527  continue;
3528 
3529  if (!chip->details.bank[x].bank)
3530  goto need_define;
3531 
3532  if (chip->details.bank[x].probed)
3533  continue;
3534 
3535  r = sam3_auto_probe(chip->details.bank[x].bank);
3536  if (r != ERROR_OK)
3537  return r;
3538  }
3539 
3540  r = sam3_get_info(chip);
3541  if (r != ERROR_OK) {
3542  LOG_DEBUG("Sam3Info, Failed %d", r);
3543  return r;
3544  }
3545 
3546  return ERROR_OK;
3547 }
3548 
3549 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3550 {
3551  unsigned int x, v;
3552  int r, who;
3553  struct sam3_chip *chip;
3554 
3555  chip = get_current_sam3(CMD);
3556  if (!chip)
3557  return ERROR_OK;
3558 
3559  if (chip->target->state != TARGET_HALTED) {
3560  LOG_ERROR("sam3 - target not halted");
3561  return ERROR_TARGET_NOT_HALTED;
3562  }
3563 
3564  if (!chip->details.bank[0].bank) {
3565  command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
3566  at91sam3_flash.name);
3567  return ERROR_FAIL;
3568  }
3569  if (!chip->details.bank[0].probed) {
3570  r = sam3_auto_probe(chip->details.bank[0].bank);
3571  if (r != ERROR_OK)
3572  return r;
3573  }
3574 
3575  switch (CMD_ARGC) {
3576  case 0:
3577  goto showall;
3578  case 1:
3579  who = -1;
3580  break;
3581  case 2:
3582  if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) {
3583  who = -1;
3584  } else {
3585  uint32_t v32;
3586  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3587  who = v32;
3588  }
3589  break;
3590  default:
3591  return ERROR_COMMAND_SYNTAX_ERROR;
3592  }
3593 
3594  if (strcmp("show", CMD_ARGV[0]) == 0) {
3595  if (who == -1) {
3596 showall:
3597  r = ERROR_OK;
3598  for (x = 0; x < chip->details.n_gpnvms; x++) {
3599  r = flashd_get_gpnvm(&(chip->details.bank[0]), x, &v);
3600  if (r != ERROR_OK)
3601  break;
3602  command_print(CMD, "sam3-gpnvm%u: %u", x, v);
3603  }
3604  return r;
3605  }
3606  if ((who >= 0) && (((unsigned)(who)) < chip->details.n_gpnvms)) {
3607  r = flashd_get_gpnvm(&(chip->details.bank[0]), who, &v);
3608  if (r == ERROR_OK)
3609  command_print(CMD, "sam3-gpnvm%u: %u", who, v);
3610  return r;
3611  } else {
3612  command_print(CMD, "sam3-gpnvm invalid GPNVM: %u", who);
3613  return ERROR_COMMAND_SYNTAX_ERROR;
3614  }
3615  }
3616 
3617  if (who == -1) {
3618  command_print(CMD, "Missing GPNVM number");
3619  return ERROR_COMMAND_SYNTAX_ERROR;
3620  }
3621 
3622  if (strcmp("set", CMD_ARGV[0]) == 0)
3623  r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
3624  else if ((strcmp("clr", CMD_ARGV[0]) == 0) ||
3625  (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */
3626  r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
3627  else {
3628  command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
3629  r = ERROR_COMMAND_SYNTAX_ERROR;
3630  }
3631  return r;
3632 }
3633 
3634 COMMAND_HANDLER(sam3_handle_slowclk_command)
3635 {
3636  struct sam3_chip *chip;
3637 
3638  chip = get_current_sam3(CMD);
3639  if (!chip)
3640  return ERROR_OK;
3641 
3642  switch (CMD_ARGC) {
3643  case 0:
3644  /* show */
3645  break;
3646  case 1:
3647  {
3648  /* set */
3649  uint32_t v;
3650  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3651  if (v > 200000) {
3652  /* absurd slow clock of 200Khz? */
3653  command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3654  return ERROR_COMMAND_SYNTAX_ERROR;
3655  }
3656  chip->cfg.slow_freq = v;
3657  break;
3658  }
3659  default:
3660  /* error */
3661  command_print(CMD, "Too many parameters");
3662  return ERROR_COMMAND_SYNTAX_ERROR;
3663  }
3664  command_print(CMD, "Slowclk freq: %d.%03dkhz",
3665  (int)(chip->cfg.slow_freq / 1000),
3666  (int)(chip->cfg.slow_freq % 1000));
3667  return ERROR_OK;
3668 }
3669 
3670 static const struct command_registration at91sam3_exec_command_handlers[] = {
3671  {
3672  .name = "gpnvm",
3673  .handler = sam3_handle_gpnvm_command,
3674  .mode = COMMAND_EXEC,
3675  .usage = "[('clr'|'set'|'show') bitnum]",
3676  .help = "Without arguments, shows all bits in the gpnvm "
3677  "register. Otherwise, clears, sets, or shows one "
3678  "General Purpose Non-Volatile Memory (gpnvm) bit.",
3679  },
3680  {
3681  .name = "info",
3682  .handler = sam3_handle_info_command,
3683  .mode = COMMAND_EXEC,
3684  .help = "Print information about the current at91sam3 chip "
3685  "and its flash configuration.",
3686  .usage = "",
3687  },
3688  {
3689  .name = "slowclk",
3690  .handler = sam3_handle_slowclk_command,
3691  .mode = COMMAND_EXEC,
3692  .usage = "[clock_hz]",
3693  .help = "Display or set the slowclock frequency "
3694  "(default 32768 Hz).",
3695  },
3696  COMMAND_REGISTRATION_DONE
3697 };
3698 static const struct command_registration at91sam3_command_handlers[] = {
3699  {
3700  .name = "at91sam3",
3701  .mode = COMMAND_ANY,
3702  .help = "at91sam3 flash command group",
3703  .usage = "",
3704  .chain = at91sam3_exec_command_handlers,
3705  },
3706  COMMAND_REGISTRATION_DONE
3707 };
3708 
3709 const struct flash_driver at91sam3_flash = {
3710  .name = "at91sam3",
3711  .commands = at91sam3_command_handlers,
3712  .flash_bank_command = sam3_flash_bank_command,
3713  .erase = sam3_erase,
3714  .protect = sam3_protect,
3715  .write = sam3_write,
3716  .read = default_flash_read,
3717  .probe = sam3_probe,
3718  .auto_probe = sam3_auto_probe,
3719  .erase_check = default_flash_blank_check,
3720  .protect_check = sam3_protect_check,
3721  .free_driver_priv = sam3_free_driver_priv,
3722 };
FLASH_BANK1_BASE_512K_AX
#define FLASH_BANK1_BASE_512K_AX
Definition: at91sam3.c:44
FLASH_BANK0_BASE_U
#define FLASH_BANK0_BASE_U
Definition: at91sam3.c:26
FLASH_BANK1_BASE_256K_AX
#define FLASH_BANK1_BASE_256K_AX
Definition: at91sam3.c:43
sam3_get_info
static int sam3_get_info(struct sam3_chip *chip)
Definition: at91sam3.c:2914
SAM3_N_NVM_BITS
#define SAM3_N_NVM_BITS
Definition: at91sam3.c:180
get_current_sam3
static struct sam3_chip * get_current_sam3(struct command_invocation *cmd)
Definition: at91sam3.c:208
sam3_explain_ckgr_mcfr
static void sam3_explain_ckgr_mcfr(struct sam3_chip *chip)
Definition: at91sam3.c:2639
sam3_explain_mckr
static void sam3_explain_mckr(struct sam3_chip *chip)
Definition: at91sam3.c:2677
AT91C_EFC_FCMD_WPL
#define AT91C_EFC_FCMD_WPL
Definition: at91sam3.c:48
AT91C_EFC_FCMD_GLB
#define AT91C_EFC_FCMD_GLB
Definition: at91sam3.c:58
FLASH_BANK_BASE_S
#define FLASH_BANK_BASE_S
Definition: at91sam3.c:30
sam3_read_this_reg
static int sam3_read_this_reg(struct sam3_chip *chip, uint32_t *goes_here)
Definition: at91sam3.c:2858
sam3_explain_ckgr_plla
static void sam3_explain_ckgr_plla(struct sam3_chip *chip)
Definition: at91sam3.c:2657
eproc_names
static const char *const eproc_names[]
Definition: at91sam3.c:2434
AT91C_EFC_FCMD_EWPL
#define AT91C_EFC_FCMD_EWPL
Definition: at91sam3.c:50
REG_NAME_WIDTH
#define REG_NAME_WIDTH
Definition: at91sam3.c:23
_unknown
static const char _unknown[]
Definition: at91sam3.c:2433
FLASH_BANK1_BASE_512K_SD
#define FLASH_BANK1_BASE_512K_SD
Definition: at91sam3.c:34
efc_perform_command
static int efc_perform_command(struct sam3_bank_private *private, unsigned int command, unsigned int argument, uint32_t *status)
Performs the given command and wait until its completion (or an error).
Definition: at91sam3.c:2125
OFFSET_EFC_FRR
#define OFFSET_EFC_FRR
Definition: at91sam3.c:68
_yes_or_no
static const char * _yes_or_no(uint32_t v)
Definition: at91sam3.c:2544
flashd_get_gpnvm
static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm, unsigned int *puthere)
Gets current GPNVM state.
Definition: at91sam3.c:2222
AT91C_EFC_FCMD_SFB
#define AT91C_EFC_FCMD_SFB
Definition: at91sam3.c:59
sam3_write
static int sam3_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: at91sam3.c:3343
sam3_probe
static int sam3_probe(struct flash_bank *bank)
Definition: at91sam3.c:3199
flashd_get_lock_bits
static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v)
Returns a bit field (at most 64) of locked regions within a page.
Definition: at91sam3.c:2329
AT91C_EFC_FCMD_EA
#define AT91C_EFC_FCMD_EA
Definition: at91sam3.c:51
sam3_reg_fieldname
static uint32_t sam3_reg_fieldname(struct sam3_chip *chip, const char *regname, uint32_t value, unsigned int shift, unsigned int width)
Definition: at91sam3.c:2404
all_sam3_details
static const struct sam3_chip_details all_sam3_details[]
Definition: at91sam3.c:237
sam3_get_reg
static const struct sam3_reg_list * sam3_get_reg(struct sam3_chip *chip, uint32_t *goes_here)
Given a pointer to where it goes in the structure, determine the register name, address from the all ...
Definition: at91sam3.c:2831
flashd_read_uid
static int flashd_read_uid(struct sam3_bank_private *private)
Read the unique ID.
Definition: at91sam3.c:2169
get_sam3_bank_private
static struct sam3_bank_private * get_sam3_bank_private(struct flash_bank *bank)
Definition: at91sam3.c:2822
at91sam3_exec_command_handlers
static const struct command_registration at91sam3_exec_command_handlers[]
Definition: at91sam3.c:3670
flashd_unlock
static int flashd_unlock(struct sam3_bank_private *private, unsigned int start_sector, unsigned int end_sector)
Unlocks all the regions in the given address range.
Definition: at91sam3.c:2347
AT91C_EFC_FCMD_GFB
#define AT91C_EFC_FCMD_GFB
Definition: at91sam3.c:61
sam3_protect
static int sam3_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: at91sam3.c:3240
sam3_page_write
static int sam3_page_write(struct sam3_bank_private *private, unsigned int pagenum, const uint8_t *buf)
Definition: at91sam3.c:3285
flashd_clr_gpnvm
static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
Clears the selected GPNVM bit.
Definition: at91sam3.c:2263
flashd_set_gpnvm
static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
Sets the selected GPNVM bit.
Definition: at91sam3.c:2295
efc_start_command
static int efc_start_command(struct sam3_bank_private *private, unsigned int command, unsigned int argument)
Definition: at91sam3.c:2031
nvpsize
static const char *const nvpsize[]
Definition: at91sam3.c:2454
AT91C_EFC_FCMD_EWP
#define AT91C_EFC_FCMD_EWP
Definition: at91sam3.c:49
at91sam3_flash
const struct flash_driver at91sam3_flash
Definition: at91sam3.c:3709
FLASH_BANK_BASE_N
#define FLASH_BANK_BASE_N
Definition: at91sam3.c:38
_tomhz
static float _tomhz(uint32_t freq_hz)
Definition: at91sam3.c:70
AT91C_EFC_FCMD_WP
#define AT91C_EFC_FCMD_WP
Definition: at91sam3.c:47
all_sam3_chips
static struct sam3_chip * all_sam3_chips
Definition: at91sam3.c:206
_sam3_probe
static int _sam3_probe(struct flash_bank *bank, int noise)
Definition: at91sam3.c:3127
at91sam3_command_handlers
static const struct command_registration at91sam3_command_handlers[]
Definition: at91sam3.c:3698
sam3_free_driver_priv
static void sam3_free_driver_priv(struct flash_bank *bank)
Remove all chips from the internal list without distinguishing which one is owned by this bank.
Definition: at91sam3.c:3057
sam3_get_details
static int sam3_get_details(struct sam3_bank_private *private)
Definition: at91sam3.c:3068
nvptype
static const char *const nvptype[]
Definition: at91sam3.c:2533
efc_get_result
static int efc_get_result(struct sam3_bank_private *private, uint32_t *v)
Get the result of the last executed command.
Definition: at91sam3.c:2018
sam3_explain_chipid_cidr
static void sam3_explain_chipid_cidr(struct sam3_chip *chip)
Definition: at91sam3.c:2600
sam3_page_read
static int sam3_page_read(struct sam3_bank_private *private, unsigned int pagenum, uint8_t *buf)
Definition: at91sam3.c:3266
OFFSET_EFC_FCR
#define OFFSET_EFC_FCR
Definition: at91sam3.c:66
FLASH_BANK0_BASE_SD
#define FLASH_BANK0_BASE_SD
Definition: at91sam3.c:33
nvpsize2
#define nvpsize2
Definition: at91sam3.c:2453
flashd_lock
static int flashd_lock(struct sam3_bank_private *private, unsigned int start_sector, unsigned int end_sector)
Locks regions.
Definition: at91sam3.c:2377
sam3_get_reg_ptr
static uint32_t * sam3_get_reg_ptr(struct sam3_cfg *cfg, const struct sam3_reg_list *list)
Definition: at91sam3.c:2782
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static const struct sam3_reg_list sam3_all_regs[]
Definition: at91sam3.c:2798
OFFSET_EFC_FSR
#define OFFSET_EFC_FSR
Definition: at91sam3.c:67
FLASH_BANK0_BASE_AX
#define FLASH_BANK0_BASE_AX
Definition: at91sam3.c:41
sam3_explain_ckgr_mor
static void sam3_explain_ckgr_mor(struct sam3_chip *chip)
Definition: at91sam3.c:2556
SAM3_ENTRY
#define SAM3_ENTRY(NAME, FUNC)
Definition: at91sam3.c:2795
AT91C_EFC_FCMD_STUI
#define AT91C_EFC_FCMD_STUI
Definition: at91sam3.c:62
AT91C_EFC_FCMD_GETD
#define AT91C_EFC_FCMD_GETD
Definition: at91sam3.c:46
sam3_auto_probe
static int sam3_auto_probe(struct flash_bank *bank)
Definition: at91sam3.c:3204
efc_get_status
static int efc_get_status(struct sam3_bank_private *private, uint32_t *v)
Get the current status of the EEFC and the value of some status bits (LOCKE, PROGE).
Definition: at91sam3.c:1998
sam3_erase
static int sam3_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: at91sam3.c:3209
sam3_read_all_regs
static int sam3_read_all_regs(struct sam3_chip *chip)
Definition: at91sam3.c:2875
FLASH_BANK_COMMAND_HANDLER
FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
Definition: at91sam3.c:2982
sramsize
static const char *const sramsize[]
Definition: at91sam3.c:2473
AT91C_EFC_FCMD_SPUI
#define AT91C_EFC_FCMD_SPUI
Definition: at91sam3.c:63
FLASH_BANK1_BASE_U
#define FLASH_BANK1_BASE_U
Definition: at91sam3.c:27
AT91C_EFC_FCMD_CLB
#define AT91C_EFC_FCMD_CLB
Definition: at91sam3.c:57
flashd_erase_entire_bank
static int flashd_erase_entire_bank(struct sam3_bank_private *private)
Erases the entire flash.
Definition: at91sam3.c:2209
sam3_protect_check
static int sam3_protect_check(struct flash_bank *bank)
Definition: at91sam3.c:2949
AT91C_EFC_FCMD_SLB
#define AT91C_EFC_FCMD_SLB
Definition: at91sam3.c:56
_rc_freq
static const char *const _rc_freq[]
Definition: at91sam3.c:2552
AT91C_EFC_FCMD_CFB
#define AT91C_EFC_FCMD_CFB
Definition: at91sam3.c:60
SAM3_MAX_FLASH_BANKS
#define SAM3_MAX_FLASH_BANKS
Definition: at91sam3.c:185
COMMAND_HANDLER
COMMAND_HANDLER(sam3_handle_info_command)
Definition: at91sam3.c:3492
CKGR_MOR
#define CKGR_MOR
Definition: at91sam7.c:45
PMC_MCKR
#define PMC_MCKR
Definition: at91sam7.c:50
CKGR_MCFR
#define CKGR_MCFR
Definition: at91sam7.c:44
command_print_sameline
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:348
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:371
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:400
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:440
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:251
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
buffer
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
width
unsigned short width
Definition: embeddedice.c:47
bank
uint8_t bank
Definition: esirisc.c:135
ERROR_FLASH_BANK_NOT_PROBED
#define ERROR_FLASH_BANK_NOT_PROBED
Definition: flash/common.h:35
default_flash_blank_check
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
Definition: flash/nor/core.c:380
default_flash_read
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
Definition: flash/nor/core.c:121
LOG_USER
#define LOG_USER(expr ...)
Definition: log.h:136
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:174
LOG_USER_N
#define LOG_USER_N(expr ...)
Definition: log.h:139
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:133
LOG_INFO
#define LOG_INFO(expr ...)
Definition: log.h:127
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:110
ERROR_OK
#define ERROR_OK
Definition: log.h:168
archnames::name
const char * name
Definition: at91sam3.c:2493
archnames::value
unsigned int value
Definition: at91sam3.c:2493
command_invocation
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
command_registration
Definition: command.h:233
command_registration::name
const char * name
Definition: command.h:234
flash_bank
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
flash_driver
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
flash_driver::name
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
reg
Definition: register.h:111
reg::name
const char * name
Definition: register.h:113
sam3_bank_private
Definition: at91sam3.c:145
sam3_bank_private::controller_address
uint32_t controller_address
Definition: at91sam3.c:158
sam3_bank_private::probed
bool probed
Definition: at91sam3.c:146
sam3_bank_private::sector_size
unsigned int sector_size
Definition: at91sam3.c:164
sam3_bank_private::bank
struct flash_bank * bank
Definition: at91sam3.c:156
sam3_bank_private::present
bool present
Definition: at91sam3.c:161
sam3_bank_private::size_bytes
unsigned int size_bytes
Definition: at91sam3.c:162
sam3_bank_private::bank_number
unsigned int bank_number
Definition: at91sam3.c:157
sam3_bank_private::page_size
unsigned int page_size
Definition: at91sam3.c:165
sam3_bank_private::flash_wait_states
uint32_t flash_wait_states
Definition: at91sam3.c:160
sam3_bank_private::nsectors
unsigned int nsectors
Definition: at91sam3.c:163
sam3_bank_private::chip
struct sam3_chip * chip
Definition: at91sam3.c:154
sam3_bank_private::base_address
uint32_t base_address
Definition: at91sam3.c:159
sam3_cfg
Definition: at91sam3.c:79
sam3_cfg::PMC_IMR
uint32_t PMC_IMR
Definition: at91sam3.c:128
sam3_cfg::PMC_SCSR
uint32_t PMC_SCSR
Definition: at91sam3.c:106
sam3_cfg::CKGR_PLLAR
uint32_t CKGR_PLLAR
Definition: at91sam3.c:116
sam3_cfg::pclk0_freq
uint32_t pclk0_freq
Definition: at91sam3.c:89
sam3_cfg::PMC_MCKR
uint32_t PMC_MCKR
Definition: at91sam3.c:118
sam3_cfg::CHIPID_CIDR2
uint32_t CHIPID_CIDR2
Definition: at91sam3.c:97
sam3_cfg::PMC_SR
uint32_t PMC_SR
Definition: at91sam3.c:126
sam3_cfg::unique_id
uint32_t unique_id[4]
Definition: at91sam3.c:80
sam3_cfg::pclk1_freq
uint32_t pclk1_freq
Definition: at91sam3.c:90
sam3_cfg::PMC_FSPR
uint32_t PMC_FSPR
Definition: at91sam3.c:132
sam3_cfg::slow_freq
uint32_t slow_freq
Definition: at91sam3.c:82
sam3_cfg::PMC_PCSR
uint32_t PMC_PCSR
Definition: at91sam3.c:108
sam3_cfg::mclk_freq
uint32_t mclk_freq
Definition: at91sam3.c:86
sam3_cfg::mainosc_freq
uint32_t mainosc_freq
Definition: at91sam3.c:84
sam3_cfg::pclk2_freq
uint32_t pclk2_freq
Definition: at91sam3.c:91
sam3_cfg::CKGR_UCKR
uint32_t CKGR_UCKR
Definition: at91sam3.c:110
sam3_cfg::CHIPID_EXID2
uint32_t CHIPID_EXID2
Definition: at91sam3.c:101
sam3_cfg::CKGR_MOR
uint32_t CKGR_MOR
Definition: at91sam3.c:112
sam3_cfg::plla_freq
uint32_t plla_freq
Definition: at91sam3.c:85
sam3_cfg::cpu_freq
uint32_t cpu_freq
Definition: at91sam3.c:87
sam3_cfg::fclk_freq
uint32_t fclk_freq
Definition: at91sam3.c:88
sam3_cfg::CKGR_MCFR
uint32_t CKGR_MCFR
Definition: at91sam3.c:114
sam3_cfg::CHIPID_EXID
uint32_t CHIPID_EXID
Definition: at91sam3.c:99
sam3_cfg::PMC_PCK0
uint32_t PMC_PCK0
Definition: at91sam3.c:120
sam3_cfg::CHIPID_CIDR
uint32_t CHIPID_CIDR
Definition: at91sam3.c:95
sam3_cfg::PMC_FSMR
uint32_t PMC_FSMR
Definition: at91sam3.c:130
sam3_cfg::rc_freq
uint32_t rc_freq
Definition: at91sam3.c:83
sam3_cfg::PMC_PCK2
uint32_t PMC_PCK2
Definition: at91sam3.c:124
sam3_cfg::PMC_PCK1
uint32_t PMC_PCK1
Definition: at91sam3.c:122
sam3_chip_details
Definition: at91sam3.c:168
sam3_chip_details::n_banks
unsigned int n_banks
Definition: at91sam3.c:184
sam3_chip_details::total_flash_size
unsigned int total_flash_size
Definition: at91sam3.c:182
sam3_chip_details::n_gpnvms
unsigned int n_gpnvms
Definition: at91sam3.c:179
sam3_chip_details::name
const char * name
Definition: at91sam3.c:177
sam3_chip_details::gpnvm
unsigned int gpnvm[SAM3_N_NVM_BITS]
Definition: at91sam3.c:181
sam3_chip_details::bank
struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS]
Definition: at91sam3.c:187
sam3_chip_details::total_sram_size
unsigned int total_sram_size
Definition: at91sam3.c:183
sam3_chip_details::chipid_cidr
uint32_t chipid_cidr
Definition: at91sam3.c:176
sam3_chip
Definition: at91sam3.c:190
sam3_chip::next
struct sam3_chip * next
Definition: at91sam3.c:191
sam3_chip::probed
bool probed
Definition: at91sam3.c:192
sam3_chip::target
struct target * target
Definition: at91sam3.c:196
sam3_chip::details
struct sam3_chip_details details
Definition: at91sam3.c:195
sam3_chip::cfg
struct sam3_cfg cfg
Definition: at91sam3.c:197
sam3_reg_list
Definition: at91sam3.c:201
sam3_reg_list::name
const char * name
Definition: at91sam3.c:202
sam3_reg_list::address
uint32_t address
Definition: at91sam3.c:202
sam3_reg_list::struct_offset
size_t struct_offset
Definition: at91sam3.c:202
sam3_reg_list::explain_func
void(* explain_func)(struct sam3_chip *chip)
Definition: at91sam3.c:203
target
Definition: target.h:119
target::state
enum target_state state
Definition: target.h:160
target_write_memory
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1275
target_write_u32
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2650
target_read_u32
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2559
target_read_memory
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1247
get_current_target
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:467
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:786
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:58
time_support.h
timeval_ms
int64_t timeval_ms(void)
Definition: time_support_common.c:23
TARGET_ADDR_FMT
#define TARGET_ADDR_FMT
Definition: types.h:286
NULL
#define NULL
Definition: usb.h:16
status
uint8_t status[4]
Definition: vdebug.c:17
cmd
uint8_t cmd
Definition: vdebug.c:1
offset
uint8_t offset[4]
Definition: vdebug.c:9
count
uint8_t count[4]
Definition: vdebug.c:22