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Programmable Logic Devices (PLDs) and the more flexible Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware. OpenOCD can support programming them. Although PLDs are generally restrictive (cells are less functional, and there are no special purpose cells for memory or computational tasks), they share the same OpenOCD infrastructure. Accordingly, both are called PLDs here.
As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND), OpenOCD maintains a list of PLDs available for use in various commands. Also, each such PLD requires a driver. PLD drivers may also be needed to program SPI flash connected to the FPGA to store the bitstream (See jtagspi for details).
They are referenced by the name which was given when the pld was created or
the number shown by the pld devices command.
New PLDs are defined by pld create pld_name driver_name -chain-position tap_name [driver_options].
Creates a new PLD device, supported by driver driver_name,
assigning pld_name for further reference.
-chain-position tap_name names the TAP
used to access this target.
The driver may make use of any driver_options to configure its behavior.
List the known PLDs with their name.
Loads the file filename into the PLD identified by pld_name. The file format must be inferred by the driver.
Drivers may support PLD-specific options to the pld create
command, and may also define commands usable only with
that particular type of PLD.
Virtex-II is a family of FPGAs sold by Xilinx. This driver can also be used to load Series3, Series6, Series7 and Zynq 7000 devices. It supports the IEEE 1532 standard for In-System Configuration (ISC).
If -no_jstart is given, the JSTART instruction is not used after loading the bitstream. While required for Series2, Series3, and Series6, it breaks bitstream loading on Series7.
openocd -f board/digilent_zedboard.cfg -c "init" \ -c "pld load 0 zedboard_bitstream.bit"
Reads and displays the Virtex-II status register (STAT) for FPGA pld_name.
Change values for boundary scan instructions. Default are values for Virtex 2, devices Virtex 4/5/6 and SSI devices are using different values. pld_name is the name of the pld device. cfg_out is the value used to select CFG_OUT instruction. cfg_in is the value used to select CFG_IN instruction. jprogb is the value used to select JPROGRAM instruction. jstart is the value used to select JSTART instruction. jshutdown is the value used to select JSHUTDOWN instruction. user1 to user4 are the intruction used to select the user registers USER1 to USER4.
Change values for boundary scan instructions selecting the registers USER1 to USER4.
Description of the arguments can be found at command virtex2 set_instr_codes.
Load the bitstream from external memory for FPGA pld_name. A.k.a. program.
The FGPA families ECP2, ECP3, ECP5, Certus and CertusPro by Lattice are supported. This driver can be used to load the bitstream into the FPGA or read the status register and read/write the usercode register.
For the option -family name is one of ecp2 ecp3 ecp5 certus. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices).
Reads and displays the status register for FPGA pld_name.
Reads and displays the user register for FPGA pld_name.
Writes the user register. for FPGA pld_name with value val.
Set the length of the register for the preload. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices). The load command for the FPGA pld_name will use a length for the preload of length.
Load the bitstream from external memory for FPGA pld_name. A.k.a program.
Both families (Trion and Titanium) sold by Efinix are supported as both use the same protocol for In-System Configuration. This driver can be used to load the bitstream into the FPGA. For the option -family name is one of trion|titanium.
This driver can be used to load the bitstream into Intel (former Altera) FPGAs. The families Cyclone III, Cyclone IV, Cyclone V, Cyclone 10 and Arria II are supported.
The option -family name is one of cycloneiii cycloneiv cyclonev cyclone10 arriaii.
As input file format the driver supports a ’.rbf’ (raw bitstream file) file. The ’.rbf’ file can be generated from a ’.sof’ file with quartus_cpf -c blinker.sof blinker.rbf
Creates a new PLD device, an FPGA of the Cyclone III family, using the TAP named cycloneiii.tap:
pld create cycloneiii.pld intel -chain-position cycloneiii.tap -family cycloneiii
Set boundary scan register length of FPGA pld_name to len. This is needed because the length can vary between chips with the same JTAG ID.
Selects the position pos in the boundary-scan register. The bit at this position is checked after loading the bitstream and must be ’1’, which is the case when no error occurred. With a value of -1 for pos the check will be omitted.
This driver can be used to load the bitstream into FPGAs from Gowin. It is possible to program the SRAM. Programming the flash is not supported. The files .fs and .bin generated by Gowin FPGA Designer are supported.
Reads and displays the status register for FPGA pld_name.
Reads and displays the user register for FPGA pld_name.
Load the bitstream from external memory for FPGA pld_name. A.k.a. reload.
This driver can be used to load the bitstream into GateMate FPGAs form CologneChip. The files .bit and .cfg both generated by p_r tool from CologneChip are supported.
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